456 lines
14 KiB
C
456 lines
14 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* based on Ralink SDK3.3
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* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
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*/
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#ifndef FE_ETH_H
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#define FE_ETH_H
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#include <linux/mii.h>
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#include <linux/interrupt.h>
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#include <linux/netdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/phy.h>
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#include <linux/ethtool.h>
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enum fe_reg {
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FE_REG_PDMA_GLO_CFG = 0,
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FE_REG_PDMA_RST_CFG,
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FE_REG_DLY_INT_CFG,
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FE_REG_TX_BASE_PTR0,
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FE_REG_TX_MAX_CNT0,
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FE_REG_TX_CTX_IDX0,
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FE_REG_RX_BASE_PTR0,
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FE_REG_RX_MAX_CNT0,
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FE_REG_RX_CALC_IDX0,
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FE_REG_FE_INT_ENABLE,
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FE_REG_FE_INT_STATUS,
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FE_REG_FE_DMA_VID_BASE,
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FE_REG_FE_COUNTER_BASE,
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FE_REG_FE_RST_GL,
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FE_REG_COUNT
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};
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#define FE_DRV_VERSION "0.1.0"
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/* power of 2 to let NEXT_TX_DESP_IDX work */
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#define NUM_DMA_DESC (1 << 7)
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#define MAX_DMA_DESC 0xfff
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#define FE_DELAY_EN_INT 0x80
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#define FE_DELAY_MAX_INT 0x04
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#define FE_DELAY_MAX_TOUT 0x04
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#define FE_DELAY_TIME 20
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#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
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#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
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#define FE_PSE_FQFC_CFG_INIT 0x80504000
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#define FE_PSE_FQFC_CFG_256Q 0xff908000
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/* interrupt bits */
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#define FE_CNT_PPE_AF BIT(31)
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#define FE_CNT_GDM_AF BIT(29)
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#define FE_PSE_P2_FC BIT(26)
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#define FE_PSE_BUF_DROP BIT(24)
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#define FE_GDM_OTHER_DROP BIT(23)
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#define FE_PSE_P1_FC BIT(22)
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#define FE_PSE_P0_FC BIT(21)
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#define FE_PSE_FQ_EMPTY BIT(20)
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#define FE_GE1_STA_CHG BIT(18)
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#define FE_TX_COHERENT BIT(17)
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#define FE_RX_COHERENT BIT(16)
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#define FE_TX_DONE_INT3 BIT(11)
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#define FE_TX_DONE_INT2 BIT(10)
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#define FE_TX_DONE_INT1 BIT(9)
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#define FE_TX_DONE_INT0 BIT(8)
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#define FE_RX_DONE_INT0 BIT(2)
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#define FE_TX_DLY_INT BIT(1)
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#define FE_RX_DLY_INT BIT(0)
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#define RT5350_RX_DLY_INT BIT(30)
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#define RT5350_TX_DLY_INT BIT(28)
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/* registers */
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#define FE_FE_OFFSET 0x0000
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#define FE_GDMA_OFFSET 0x0020
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#define FE_PSE_OFFSET 0x0040
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#define FE_GDMA2_OFFSET 0x0060
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#define FE_CDMA_OFFSET 0x0080
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#define FE_DMA_VID0 0x00a8
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#define FE_PDMA_OFFSET 0x0100
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#define FE_PPE_OFFSET 0x0200
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#define FE_CMTABLE_OFFSET 0x0400
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#define FE_POLICYTABLE_OFFSET 0x1000
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#define RT5350_PDMA_OFFSET 0x0800
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#define RT5350_SDM_OFFSET 0x0c00
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#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
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#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
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#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
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#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
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#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
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#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
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#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
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#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
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#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
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#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
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#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
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#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
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#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
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#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
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#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
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#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
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#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
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#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
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#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
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#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
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#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
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#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
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#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
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#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
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#ifdef CONFIG_SOC_MT7621
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#define MT7620A_GDMA_OFFSET 0x0500
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#else
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#define MT7620A_GDMA_OFFSET 0x0600
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#endif
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#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
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#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
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#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
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#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
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#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
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#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
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#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
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#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
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#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
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#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
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#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
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#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
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#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
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#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
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#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
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#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
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#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
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#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
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#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
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#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
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#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
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#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
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#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
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#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
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#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
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#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
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#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
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#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
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#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
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#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
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#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
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#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
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#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
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#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
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#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
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#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
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#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
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#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
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#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
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#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
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#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
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#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
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#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
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#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
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#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
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#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
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#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
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#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
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#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
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#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
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#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
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#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
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#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
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#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
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#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
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#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
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#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
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#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
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#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
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#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
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#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
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#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
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#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
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#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
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#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
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#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
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#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
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#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
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#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
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#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
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#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
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#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
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#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
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#define RT5350_SDM_ICS_EN BIT(16)
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#define RT5350_SDM_TCS_EN BIT(17)
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#define RT5350_SDM_UCS_EN BIT(18)
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/* MDIO_CFG register bits */
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#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
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#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
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#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
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#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
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#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
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#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
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#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
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#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
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#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
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#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
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#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
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#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
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#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
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#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
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#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
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#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
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#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
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#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
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#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
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#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
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#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
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#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
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#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
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#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
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#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
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/* uni-cast port */
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#define FE_GDM1_JMB_LEN_MASK 0xf
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#define FE_GDM1_JMB_LEN_SHIFT 28
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#define FE_GDM1_ICS_EN BIT(22)
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#define FE_GDM1_TCS_EN BIT(21)
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#define FE_GDM1_UCS_EN BIT(20)
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#define FE_GDM1_JMB_EN BIT(19)
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#define FE_GDM1_STRPCRC BIT(16)
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#define FE_GDM1_UFRC_P_CPU (0 << 12)
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#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
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#define FE_GDM1_UFRC_P_PPE (6 << 12)
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/* checksums */
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#define FE_ICS_GEN_EN BIT(2)
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#define FE_UCS_GEN_EN BIT(1)
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#define FE_TCS_GEN_EN BIT(0)
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/* dma ring */
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#define FE_PST_DRX_IDX0 BIT(16)
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#define FE_PST_DTX_IDX3 BIT(3)
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#define FE_PST_DTX_IDX2 BIT(2)
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#define FE_PST_DTX_IDX1 BIT(1)
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#define FE_PST_DTX_IDX0 BIT(0)
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#define FE_TX_WB_DDONE BIT(6)
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#define FE_RX_DMA_BUSY BIT(3)
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#define FE_TX_DMA_BUSY BIT(1)
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#define FE_RX_DMA_EN BIT(2)
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#define FE_TX_DMA_EN BIT(0)
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#define FE_PDMA_SIZE_4DWORDS (0 << 4)
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#define FE_PDMA_SIZE_8DWORDS (1 << 4)
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#define FE_PDMA_SIZE_16DWORDS (2 << 4)
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#define FE_US_CYC_CNT_MASK 0xff
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#define FE_US_CYC_CNT_SHIFT 0x8
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#define FE_US_CYC_CNT_DIVISOR 1000000
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#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
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#define RX_DMA_LSO BIT(30)
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#define RX_DMA_DONE BIT(31)
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#define RX_DMA_L4VALID BIT(30)
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struct fe_rx_dma {
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unsigned int rxd1;
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unsigned int rxd2;
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unsigned int rxd3;
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unsigned int rxd4;
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} __packed __aligned(4);
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#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
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#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
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#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
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#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
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#define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
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#define TX_DMA_LS1 BIT(14)
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#define TX_DMA_LS0 BIT(30)
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#define TX_DMA_DONE BIT(31)
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#define TX_DMA_INS_VLAN_MT7621 BIT(16)
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#define TX_DMA_INS_VLAN BIT(7)
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#define TX_DMA_INS_PPPOE BIT(12)
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#define TX_DMA_QN(_x) ((_x) << 16)
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#define TX_DMA_PN(_x) ((_x) << 24)
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#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
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#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
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#define TX_DMA_UDF BIT(20)
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#define TX_DMA_CHKSUM (0x7 << 29)
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#define TX_DMA_TSO BIT(28)
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/* frame engine counters */
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#define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
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#define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
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#define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
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/* phy device flags */
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#define FE_PHY_FLAG_PORT BIT(0)
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#define FE_PHY_FLAG_ATTACH BIT(1)
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struct fe_tx_dma {
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unsigned int txd1;
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unsigned int txd2;
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unsigned int txd3;
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unsigned int txd4;
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} __packed __aligned(4);
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struct fe_priv;
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struct fe_phy {
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struct phy_device *phy[8];
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struct device_node *phy_node[8];
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const __be32 *phy_fixed[8];
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int duplex[8];
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int speed[8];
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int tx_fc[8];
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int rx_fc[8];
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spinlock_t lock;
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int (*connect)(struct fe_priv *priv);
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void (*disconnect)(struct fe_priv *priv);
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void (*start)(struct fe_priv *priv);
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void (*stop)(struct fe_priv *priv);
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};
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struct fe_soc_data
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{
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unsigned char mac[6];
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const u32 *reg_table;
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void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
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void (*reset_fe)(void);
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void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
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int (*fwd_config)(struct fe_priv *priv);
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|
void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
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|
void (*rx_dma)(struct fe_priv *priv, int idx, int len);
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|
int (*switch_init)(struct fe_priv *priv);
|
|
int (*switch_config)(struct fe_priv *priv);
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|
void (*port_init)(struct fe_priv *priv, struct device_node *port);
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|
int (*has_carrier)(struct fe_priv *priv);
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|
int (*mdio_init)(struct fe_priv *priv);
|
|
void (*mdio_cleanup)(struct fe_priv *priv);
|
|
int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
|
|
int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
|
|
void (*mdio_adjust_link)(struct fe_priv *priv, int port);
|
|
|
|
void *swpriv;
|
|
u32 pdma_glo_cfg;
|
|
u32 rx_dly_int;
|
|
u32 tx_dly_int;
|
|
u32 checksum_bit;
|
|
u32 tx_udf_bit;
|
|
};
|
|
|
|
#define FE_FLAG_PADDING_64B BIT(0)
|
|
#define FE_FLAG_PADDING_BUG BIT(1)
|
|
#define FE_FLAG_JUMBO_FRAME BIT(2)
|
|
|
|
#define FE_STAT_REG_DECLARE \
|
|
_FE(tx_bytes) \
|
|
_FE(tx_packets) \
|
|
_FE(tx_skip) \
|
|
_FE(tx_collisions) \
|
|
_FE(rx_bytes) \
|
|
_FE(rx_packets) \
|
|
_FE(rx_overflow) \
|
|
_FE(rx_fcs_errors) \
|
|
_FE(rx_short_errors) \
|
|
_FE(rx_long_errors) \
|
|
_FE(rx_checksum_errors) \
|
|
_FE(rx_flow_control_packets)
|
|
|
|
struct fe_hw_stats
|
|
{
|
|
spinlock_t stats_lock;
|
|
struct u64_stats_sync syncp;
|
|
#define _FE(x) u64 x;
|
|
FE_STAT_REG_DECLARE
|
|
#undef _FE
|
|
};
|
|
|
|
struct fe_priv
|
|
{
|
|
spinlock_t page_lock;
|
|
|
|
struct fe_soc_data *soc;
|
|
struct net_device *netdev;
|
|
u32 msg_enable;
|
|
u32 flags;
|
|
|
|
struct device *device;
|
|
unsigned long sysclk;
|
|
|
|
u16 frag_size;
|
|
u16 rx_buf_size;
|
|
struct fe_rx_dma *rx_dma;
|
|
u8 **rx_data;
|
|
dma_addr_t rx_phys;
|
|
struct napi_struct rx_napi;
|
|
|
|
struct fe_tx_dma *tx_dma;
|
|
struct sk_buff **tx_skb;
|
|
dma_addr_t tx_phys;
|
|
unsigned int tx_free_idx;
|
|
|
|
struct fe_phy *phy;
|
|
struct mii_bus *mii_bus;
|
|
struct phy_device *phy_dev;
|
|
u32 phy_flags;
|
|
|
|
int link[8];
|
|
|
|
struct fe_hw_stats *hw_stats;
|
|
unsigned long vlan_map;
|
|
};
|
|
|
|
extern const struct of_device_id of_fe_match[];
|
|
|
|
void fe_w32(u32 val, unsigned reg);
|
|
u32 fe_r32(unsigned reg);
|
|
|
|
int fe_set_clock_cycle(struct fe_priv *priv);
|
|
void fe_csum_config(struct fe_priv *priv);
|
|
void fe_stats_update(struct fe_priv *priv);
|
|
void fe_fwd_config(struct fe_priv *priv);
|
|
void fe_reg_w32(u32 val, enum fe_reg reg);
|
|
u32 fe_reg_r32(enum fe_reg reg);
|
|
|
|
static inline void *priv_netdev(struct fe_priv *priv)
|
|
{
|
|
return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
|
|
}
|
|
|
|
#endif /* FE_ETH_H */
|