215 lines
6.0 KiB
Diff
215 lines
6.0 KiB
Diff
Index: linux-3.10.49/drivers/gpio/Kconfig
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===================================================================
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--- linux-3.10.49.orig/drivers/gpio/Kconfig 2014-07-18 00:58:15.000000000 +0200
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+++ linux-3.10.49/drivers/gpio/Kconfig 2014-08-07 11:41:16.517169817 +0200
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@@ -171,6 +171,14 @@
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Qualcomm MSM chips. Most of the pins on the MSM can be
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selected for GPIO, and are controlled by this driver.
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+config GPIO_OCTEON
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+ tristate "Cavium OCTEON GPIO"
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+ depends on GPIOLIB && CPU_CAVIUM_OCTEON
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+ default y
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+ help
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+ Say yes here to support the on-chip GPIO lines on the OCTEON
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+ family of SOCs.
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+
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config GPIO_MVEBU
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def_bool y
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depends on PLAT_ORION
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Index: linux-3.10.49/drivers/gpio/Makefile
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===================================================================
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--- linux-3.10.49.orig/drivers/gpio/Makefile 2014-07-18 00:58:15.000000000 +0200
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+++ linux-3.10.49/drivers/gpio/Makefile 2014-08-07 11:41:16.517169817 +0200
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@@ -10,6 +10,7 @@
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# Device drivers. Generally keep list sorted alphabetically
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obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
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+obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
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obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
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obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
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obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
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Index: linux-3.10.49/drivers/gpio/gpio-octeon.c
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===================================================================
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--- /dev/null 1970-01-01 00:00:00.000000000 +0000
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+++ linux-3.10.49/drivers/gpio/gpio-octeon.c 2014-08-07 11:53:14.733161106 +0200
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@@ -0,0 +1,166 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2011,2012 Cavium Inc.
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+ */
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+
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+#include <linux/platform_device.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/gpio.h>
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+#include <linux/io.h>
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+
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+#include <asm/octeon/octeon.h>
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+#include <asm/octeon/cvmx-gpio-defs.h>
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+
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+#define DRV_VERSION "1.0"
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+#define DRV_DESCRIPTION "Cavium Inc. OCTEON GPIO Driver"
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+
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+#define RX_DAT 0x80
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+#define TX_SET 0x88
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+#define TX_CLEAR 0x90
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+
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+int gpio_to_irq(unsigned gpio)
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+{
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+ return -EINVAL;
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+}
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+EXPORT_SYMBOL(gpio_to_irq);
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+
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+/*
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+ * The address offset of the GPIO configuration register for a given
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+ * line.
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+ */
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+static unsigned int bit_cfg_reg(unsigned int gpio)
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+{
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+ if (gpio < 16)
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+ return 8 * gpio;
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+ else
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+ return 8 * (gpio - 16) + 0x100;
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+}
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+
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+struct octeon_gpio {
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+ struct gpio_chip chip;
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+ u64 register_base;
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+};
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+
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+static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
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+
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+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
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+ return 0;
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+}
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+
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+static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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+{
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+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
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+ u64 mask = 1ull << offset;
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+ u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
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+ cvmx_write_csr(reg, mask);
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+}
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+
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+static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
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+ int value)
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+{
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+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
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+ union cvmx_gpio_bit_cfgx cfgx;
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+
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+
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+ octeon_gpio_set(chip, offset, value);
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+
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+ cfgx.u64 = 0;
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+ cfgx.s.tx_oe = 1;
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+
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+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
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+ return 0;
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+}
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+
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+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
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+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
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+
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+ return ((1ull << offset) & read_bits) != 0;
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+}
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+
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+static int octeon_gpio_probe(struct platform_device *pdev)
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+{
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+ struct octeon_gpio *gpio;
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+ struct gpio_chip *chip;
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+ struct resource *res_mem;
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+ int err = 0;
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+
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+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
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+ if (!gpio)
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+ return -ENOMEM;
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+ chip = &gpio->chip;
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+
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+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (res_mem == NULL) {
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+ dev_err(&pdev->dev, "found no memory resource\n");
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+ err = -ENXIO;
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+ goto out;
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+ }
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+ if (!devm_request_mem_region(&pdev->dev, res_mem->start,
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+ resource_size(res_mem),
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+ res_mem->name)) {
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+ dev_err(&pdev->dev, "request_mem_region failed\n");
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+ err = -ENXIO;
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+ goto out;
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+ }
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+ gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
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+ resource_size(res_mem));
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+
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+
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+ pdev->dev.platform_data = chip;
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+ chip->label = "octeon-gpio";
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+ chip->dev = &pdev->dev;
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+ chip->owner = THIS_MODULE;
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+ chip->base = 0;
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+ chip->can_sleep = 0;
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+ chip->ngpio = 20;
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+ chip->direction_input = octeon_gpio_dir_in;
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+ chip->get = octeon_gpio_get;
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+ chip->direction_output = octeon_gpio_dir_out;
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+ chip->set = octeon_gpio_set;
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+ err = gpiochip_add(chip);
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+ if (err)
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+ goto out;
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+
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+ dev_info(&pdev->dev, "version: " DRV_VERSION "\n");
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+out:
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+ return err;
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+}
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+
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+static int octeon_gpio_remove(struct platform_device *pdev)
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+{
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+ struct gpio_chip *chip = pdev->dev.platform_data;
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+ return gpiochip_remove(chip);
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+}
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+
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+static struct of_device_id octeon_gpio_match[] = {
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+ {
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+ .compatible = "cavium,octeon-3860-gpio",
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+ },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, octeon_gpio_match);
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+
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+static struct platform_driver octeon_gpio_driver = {
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+ .probe = octeon_gpio_probe,
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+ .remove = octeon_gpio_remove,
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+ .driver = {
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+ .name = "octeon_gpio",
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+ .owner = THIS_MODULE,
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+ .of_match_table = octeon_gpio_match,
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+ },
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+};
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+
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+module_platform_driver(octeon_gpio_driver);
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+
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+MODULE_DESCRIPTION(DRV_DESCRIPTION);
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+MODULE_AUTHOR("David Daney");
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+MODULE_LICENSE("GPL");
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+MODULE_VERSION(DRV_VERSION);
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Index: linux-3.10.49/arch/mips/Kconfig
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===================================================================
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--- linux-3.10.49.orig/arch/mips/Kconfig 2014-08-07 11:41:14.809169838 +0200
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+++ linux-3.10.49/arch/mips/Kconfig 2014-08-07 11:41:16.521169817 +0200
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@@ -769,6 +769,7 @@
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select USB_ARCH_HAS_OHCI
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select USB_ARCH_HAS_EHCI
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select HOLES_IN_ZONE
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+ select ARCH_REQUIRE_GPIOLIB
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help
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This option supports all of the Octeon reference boards from Cavium
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Networks. It builds a kernel that dynamically determines the Octeon
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