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Major restructuring to match STM peripherals library; added auto flash programming via OpenOCD

master
Mike Szczys 10 years ago
parent
commit
61b6afcbcc
  1. 0
      Device/startup_stm32f0xx.s
  2. 31
      Device/stm32f0xx_conf.h
  3. BIN
      Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf
  4. 454
      Libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h
  5. 4
      Libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h
  6. 146
      Libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html
  7. 305
      Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s
  8. 256
      Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s
  9. 292
      Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s
  10. 330
      Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s
  11. 353
      Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c
  12. 274
      Libraries/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
  13. 3809
      Libraries/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
  14. 1470
      Libraries/CMSIS/Documentation/CMSIS_Core.htm
  15. 240
      Libraries/CMSIS/Documentation/CMSIS_DebugSupport.htm
  16. 472
      Libraries/CMSIS/Documentation/CMSIS_History.htm
  17. BIN
      Libraries/CMSIS/Documentation/CMSIS_Logo_Final.jpg
  18. 1157
      Libraries/CMSIS/Documentation/CMSIS_System_View_Description.htm
  19. 0
      Libraries/CMSIS/Include/arm_common_tables.h
  20. 0
      Libraries/CMSIS/Include/arm_math.h
  21. 0
      Libraries/CMSIS/Include/core_cm0.h
  22. 0
      Libraries/CMSIS/Include/core_cm3.h
  23. 0
      Libraries/CMSIS/Include/core_cm4.h
  24. 0
      Libraries/CMSIS/Include/core_cm4_simd.h
  25. 0
      Libraries/CMSIS/Include/core_cmFunc.h
  26. 0
      Libraries/CMSIS/Include/core_cmInstr.h
  27. 34
      Libraries/CMSIS/README.txt
  28. 115
      Libraries/CMSIS/index.htm
  29. 5
      Libraries/Makefile
  30. 340
      Libraries/STM32F0xx_StdPeriph_Driver/Release_Notes.html
  31. 6
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h
  32. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h
  33. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h
  34. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h
  35. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h
  36. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h
  37. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h
  38. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h
  39. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h
  40. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h
  41. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h
  42. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h
  43. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h
  44. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h
  45. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h
  46. 21
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h
  47. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h
  48. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h
  49. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h
  50. 23
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h
  51. 4
      Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h
  52. 242
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c
  53. 150
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c
  54. 54
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c
  55. 16
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crc.c
  56. 0
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c
  57. 20
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c
  58. 214
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c
  59. 21
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c
  60. 129
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c
  61. 59
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c
  62. 272
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c
  63. 40
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c
  64. 20
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c
  65. 51
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c
  66. 442
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c
  67. 384
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c
  68. 249
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c
  69. 71
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c
  70. 832
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c
  71. 472
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c
  72. 24
      Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c
  73. 20
      Makefile
  74. 56
      README.md
  75. 22
      extra/stm32f0-openocd.cfg
  76. 156
      lib/inc/stm32f0_discovery.h
  77. 256
      lib/src/stm32f0_discovery.c
  78. 33
      src/main.c
  79. 0
      src/system_stm32f0xx.c

0
lib/startup_stm32f0xx.s → Device/startup_stm32f0xx.s

31
lib/inc/stm32f0xx_conf.h → Device/stm32f0xx_conf.h

@ -1,6 +1,6 @@
/**
******************************************************************************
* @file IO_Toggle/stm32f0xx_conf.h
* @file stm32F0xx_conf.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
@ -23,7 +23,7 @@
* limitations under the License.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0XX_CONF_H
@ -31,26 +31,26 @@
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "stm32f0xx_adc.h"
#include "stm32f0xx_cec.h"
/* #include "stm32f0xx_adc.h" */
#include "stm32f0xx_cec.h"
#include "stm32f0xx_crc.h"
#include "stm32f0xx_comp.h"
#include "stm32f0xx_dac.h"
#include "stm32f0xx_comp.h"
#include "stm32f0xx_dac.h"
#include "stm32f0xx_dbgmcu.h"
#include "stm32f0xx_dma.h"
#include "stm32f0xx_exti.h"
#include "stm32f0xx_dma.h"
#include "stm32f0xx_exti.h"
#include "stm32f0xx_flash.h"
#include "stm32f0xx_gpio.h"
#include "stm32f0xx_syscfg.h"
#include "stm32f0xx_gpio.h"
#include "stm32f0xx_syscfg.h"
#include "stm32f0xx_i2c.h"
#include "stm32f0xx_iwdg.h"
#include "stm32f0xx_pwr.h"
#include "stm32f0xx_rcc.h"
#include "stm32f0xx_rtc.h"
#include "stm32f0xx_pwr.h"
#include "stm32f0xx_rcc.h"
#include "stm32f0xx_rtc.h"
#include "stm32f0xx_spi.h"
#include "stm32f0xx_tim.h"
#include "stm32f0xx_usart.h"
#include "stm32f0xx_wwdg.h"
#include "stm32f0xx_usart.h"
#include "stm32f0xx_wwdg.h"
#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Exported types ------------------------------------------------------------*/
@ -58,7 +58,6 @@
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT

BIN
Libraries/CMSIS/CMSIS END USER LICENCE AGREEMENT.pdf

Binary file not shown.

454
lib/inc/stm32f0xx.h → Libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.
@ -61,7 +61,7 @@
* @{
*/
/* Uncomment the line below according to the target STM32F-0 device used in your
/* Uncomment the line below according to the target STM32F0 device used in your
application
*/
@ -71,8 +71,9 @@
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
- STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory
density ranges between 32 and 64 Kbytes.
STM32F0xx devices are:
- STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes.
- STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes.
*/
#if !defined (STM32F0XX)
@ -138,11 +139,11 @@
#endif /* LSE_VALUE */
/**
* @brief STM32F0xx Standard Peripheral Library version number V1.0.0
* @brief STM32F0xx Standard Peripheral Library version number V1.0.1
*/
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
@ -2176,266 +2177,263 @@ typedef struct
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM ((uint32_t)0x00400000) /*!< */
#define RTC_TR_HT ((uint32_t)0x00300000) /*!< */
#define RTC_TR_HT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_TR_HT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_TR_HU ((uint32_t)0x000F0000) /*!< */
#define RTC_TR_HU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_TR_HU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_TR_HU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_TR_HU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_TR_MNT ((uint32_t)0x00007000) /*!< */
#define RTC_TR_MNT_0 ((uint32_t)0x00001000) /*!< */
#define RTC_TR_MNT_1 ((uint32_t)0x00002000) /*!< */
#define RTC_TR_MNT_2 ((uint32_t)0x00004000) /*!< */
#define RTC_TR_MNU ((uint32_t)0x00000F00) /*!< */
#define RTC_TR_MNU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TR_MNU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TR_MNU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TR_MNU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_TR_ST ((uint32_t)0x00000070) /*!< */
#define RTC_TR_ST_0 ((uint32_t)0x00000010) /*!< */
#define RTC_TR_ST_1 ((uint32_t)0x00000020) /*!< */
#define RTC_TR_ST_2 ((uint32_t)0x00000040) /*!< */
#define RTC_TR_SU ((uint32_t)0x0000000F) /*!< */
#define RTC_TR_SU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_TR_SU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_TR_SU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_TR_SU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_TR_PM ((uint32_t)0x00400000)
#define RTC_TR_HT ((uint32_t)0x00300000)
#define RTC_TR_HT_0 ((uint32_t)0x00100000)
#define RTC_TR_HT_1 ((uint32_t)0x00200000)
#define RTC_TR_HU ((uint32_t)0x000F0000)
#define RTC_TR_HU_0 ((uint32_t)0x00010000)
#define RTC_TR_HU_1 ((uint32_t)0x00020000)
#define RTC_TR_HU_2 ((uint32_t)0x00040000)
#define RTC_TR_HU_3 ((uint32_t)0x00080000)
#define RTC_TR_MNT ((uint32_t)0x00007000)
#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TR_MNU ((uint32_t)0x00000F00)
#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TR_ST ((uint32_t)0x00000070)
#define RTC_TR_ST_0 ((uint32_t)0x00000010)
#define RTC_TR_ST_1 ((uint32_t)0x00000020)
#define RTC_TR_ST_2 ((uint32_t)0x00000040)
#define RTC_TR_SU ((uint32_t)0x0000000F)
#define RTC_TR_SU_0 ((uint32_t)0x00000001)
#define RTC_TR_SU_1 ((uint32_t)0x00000002)
#define RTC_TR_SU_2 ((uint32_t)0x00000004)
#define RTC_TR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT ((uint32_t)0x00F00000) /*!< */
#define RTC_DR_YT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_DR_YT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_DR_YT_2 ((uint32_t)0x00400000) /*!< */
#define RTC_DR_YT_3 ((uint32_t)0x00800000) /*!< */
#define RTC_DR_YU ((uint32_t)0x000F0000) /*!< */
#define RTC_DR_YU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_DR_YU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_DR_YU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_DR_YU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_DR_WDU ((uint32_t)0x0000E000) /*!< */
#define RTC_DR_WDU_0 ((uint32_t)0x00002000) /*!< */
#define RTC_DR_WDU_1 ((uint32_t)0x00004000) /*!< */
#define RTC_DR_WDU_2 ((uint32_t)0x00008000) /*!< */
#define RTC_DR_MT ((uint32_t)0x00001000) /*!< */
#define RTC_DR_MU ((uint32_t)0x00000F00) /*!< */
#define RTC_DR_MU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_DR_MU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_DR_MU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_DR_MU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_DR_DT ((uint32_t)0x00000030) /*!< */
#define RTC_DR_DT_0 ((uint32_t)0x00000010) /*!< */
#define RTC_DR_DT_1 ((uint32_t)0x00000020) /*!< */
#define RTC_DR_DU ((uint32_t)0x0000000F) /*!< */
#define RTC_DR_DU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_DR_DU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_DR_DU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_DR_DU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_DR_YT ((uint32_t)0x00F00000)
#define RTC_DR_YT_0 ((uint32_t)0x00100000)
#define RTC_DR_YT_1 ((uint32_t)0x00200000)
#define RTC_DR_YT_2 ((uint32_t)0x00400000)
#define RTC_DR_YT_3 ((uint32_t)0x00800000)
#define RTC_DR_YU ((uint32_t)0x000F0000)
#define RTC_DR_YU_0 ((uint32_t)0x00010000)
#define RTC_DR_YU_1 ((uint32_t)0x00020000)
#define RTC_DR_YU_2 ((uint32_t)0x00040000)
#define RTC_DR_YU_3 ((uint32_t)0x00080000)
#define RTC_DR_WDU ((uint32_t)0x0000E000)
#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
#define RTC_DR_MT ((uint32_t)0x00001000)
#define RTC_DR_MU ((uint32_t)0x00000F00)
#define RTC_DR_MU_0 ((uint32_t)0x00000100)
#define RTC_DR_MU_1 ((uint32_t)0x00000200)
#define RTC_DR_MU_2 ((uint32_t)0x00000400)
#define RTC_DR_MU_3 ((uint32_t)0x00000800)
#define RTC_DR_DT ((uint32_t)0x00000030)
#define RTC_DR_DT_0 ((uint32_t)0x00000010)
#define RTC_DR_DT_1 ((uint32_t)0x00000020)
#define RTC_DR_DU ((uint32_t)0x0000000F)
#define RTC_DR_DU_0 ((uint32_t)0x00000001)
#define RTC_DR_DU_1 ((uint32_t)0x00000002)
#define RTC_DR_DU_2 ((uint32_t)0x00000004)
#define RTC_DR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_COE ((uint32_t)0x00800000) /*!< */
#define RTC_CR_OSEL ((uint32_t)0x00600000) /*!< */
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000) /*!< */
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000) /*!< */
#define RTC_CR_POL ((uint32_t)0x00100000) /*!< */
#define RTC_CR_CALSEL ((uint32_t)0x00080000) /*!< */
#define RTC_CR_BCK ((uint32_t)0x00040000) /*!< */
#define RTC_CR_SUB1H ((uint32_t)0x00020000) /*!< */
#define RTC_CR_ADD1H ((uint32_t)0x00010000) /*!< */
#define RTC_CR_TSIE ((uint32_t)0x00008000) /*!< */
#define RTC_CR_ALRAIE ((uint32_t)0x00001000) /*!< */
#define RTC_CR_TSE ((uint32_t)0x00000800) /*!< */
#define RTC_CR_ALRAE ((uint32_t)0x00000100) /*!< */
#define RTC_CR_DCE ((uint32_t)0x00000080) /*!< */
#define RTC_CR_FMT ((uint32_t)0x00000040) /*!< */
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020) /*!< */
#define RTC_CR_REFCKON ((uint32_t)0x00000010) /*!< */
#define RTC_CR_TSEDGE ((uint32_t)0x00000008) /*!< */
#define RTC_CR_COE ((uint32_t)0x00800000)
#define RTC_CR_OSEL ((uint32_t)0x00600000)
#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
#define RTC_CR_POL ((uint32_t)0x00100000)
#define RTC_CR_CALSEL ((uint32_t)0x00080000)
#define RTC_CR_BCK ((uint32_t)0x00040000)
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_DCE ((uint32_t)0x00000080)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
/******************** Bits definition for RTC_ISR register ******************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000) /*!< */
#define RTC_ISR_TAMP3F ((uint32_t)0x00008000) /*!< */
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000) /*!< */
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000) /*!< */
#define RTC_ISR_TSOVF ((uint32_t)0x00001000) /*!< */
#define RTC_ISR_TSF ((uint32_t)0x00000800) /*!< */
#define RTC_ISR_ALRAF ((uint32_t)0x00000100) /*!< */
#define RTC_ISR_INIT ((uint32_t)0x00000080) /*!< */
#define RTC_ISR_INITF ((uint32_t)0x00000040) /*!< */
#define RTC_ISR_RSF ((uint32_t)0x00000020) /*!< */
#define RTC_ISR_INITS ((uint32_t)0x00000010) /*!< */
#define RTC_ISR_SHPF ((uint32_t)0x00000008) /*!< */
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001) /*!< */
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) /*!< */
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) /*!< */
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) /*!< */
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) /*!< */
#define RTC_ALRMAR_DT ((uint32_t)0x30000000) /*!< */
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) /*!< */
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) /*!< */
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000) /*!< */
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) /*!< */
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) /*!< */
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) /*!< */
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) /*!< */
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) /*!< */
#define RTC_ALRMAR_PM ((uint32_t)0x00400000) /*!< */
#define RTC_ALRMAR_HT ((uint32_t)0x00300000) /*!< */
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000) /*!< */
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) /*!< */
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000) /*!< */
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) /*!< */
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) /*!< */
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) /*!< */
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) /*!< */
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) /*!< */
#define RTC_ALRMAR_ST ((uint32_t)0x00000070) /*!< */
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) /*!< */
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) /*!< */
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) /*!< */
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F) /*!< */
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY ((uint32_t)0x000000FF) /*!< */
#define RTC_WPR_KEY ((uint32_t)0x000000FF)
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS ((uint32_t)0x0003FFFF) /*!< */
#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) /*!< */
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) /*!< */
#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM ((uint32_t)0x00400000) /*!< */
#define RTC_TSTR_HT ((uint32_t)0x00300000) /*!< */
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000) /*!< */
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000) /*!< */
#define RTC_TSTR_HU ((uint32_t)0x000F0000) /*!< */
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000) /*!< */
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000) /*!< */
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000) /*!< */
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000) /*!< */
#define RTC_TSTR_MNT ((uint32_t)0x00007000) /*!< */
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) /*!< */
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) /*!< */
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) /*!< */
#define RTC_TSTR_MNU ((uint32_t)0x00000F00) /*!< */
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_TSTR_ST ((uint32_t)0x00000070) /*!< */
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010) /*!< */
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020) /*!< */
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040) /*!< */
#define RTC_TSTR_SU ((uint32_t)0x0000000F) /*!< */
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_TSTR_PM ((uint32_t)0x00400000)
#define RTC_TSTR_HT ((uint32_t)0x00300000)
#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
#define RTC_TSTR_HU ((uint32_t)0x000F0000)
#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
#define RTC_TSTR_MNT ((uint32_t)0x00007000)
#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
#define RTC_TSTR_ST ((uint32_t)0x00000070)
#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
#define RTC_TSTR_SU ((uint32_t)0x0000000F)
#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU ((uint32_t)0x0000E000) /*!< */
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) /*!< */
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) /*!< */
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) /*!< */
#define RTC_TSDR_MT ((uint32_t)0x00001000) /*!< */
#define RTC_TSDR_MU ((uint32_t)0x00000F00) /*!< */
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800) /*!< */
#define RTC_TSDR_DT ((uint32_t)0x00000030) /*!< */
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010) /*!< */
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020) /*!< */
#define RTC_TSDR_DU ((uint32_t)0x0000000F) /*!< */
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001) /*!< */
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002) /*!< */
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004) /*!< */
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008) /*!< */
#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
#define RTC_TSDR_MT ((uint32_t)0x00001000)
#define RTC_TSDR_MU ((uint32_t)0x00000F00)
#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
#define RTC_TSDR_DT ((uint32_t)0x00000030)
#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
#define RTC_TSDR_DU ((uint32_t)0x0000000F)
#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
/******************** Bits definition for RTC_CAL register *****************/
#define RTC_CAL_CALP ((uint32_t)0x00008000) /*!< */
#define RTC_CAL_CALW8 ((uint32_t)0x00004000) /*!< */
#define RTC_CAL_CALW16 ((uint32_t)0x00002000) /*!< */
#define RTC_CAL_CALM ((uint32_t)0x000001FF) /*!< */
#define RTC_CAL_CALM_0 ((uint32_t)0x00000001) /*!< */
#define RTC_CAL_CALM_1 ((uint32_t)0x00000002) /*!< */
#define RTC_CAL_CALM_2 ((uint32_t)0x00000004) /*!< */
#define RTC_CAL_CALM_3 ((uint32_t)0x00000008) /*!< */
#define RTC_CAL_CALM_4 ((uint32_t)0x00000010) /*!< */
#define RTC_CAL_CALM_5 ((uint32_t)0x00000020) /*!< */
#define RTC_CAL_CALM_6 ((uint32_t)0x00000040) /*!< */
#define RTC_CAL_CALM_7 ((uint32_t)0x00000080) /*!< */
#define RTC_CAL_CALM_8 ((uint32_t)0x00000100) /*!< */
#define RTC_CAL_CALP ((uint32_t)0x00008000)
#define RTC_CAL_CALW8 ((uint32_t)0x00004000)
#define RTC_CAL_CALW16 ((uint32_t)0x00002000)
#define RTC_CAL_CALM ((uint32_t)0x000001FF)
#define RTC_CAL_CALM_0 ((uint32_t)0x00000001)
#define RTC_CAL_CALM_1 ((uint32_t)0x00000002)
#define RTC_CAL_CALM_2 ((uint32_t)0x00000004)
#define RTC_CAL_CALM_3 ((uint32_t)0x00000008)
#define RTC_CAL_CALM_4 ((uint32_t)0x00000010)
#define RTC_CAL_CALM_5 ((uint32_t)0x00000020)
#define RTC_CAL_CALM_6 ((uint32_t)0x00000040)
#define RTC_CAL_CALM_7 ((uint32_t)0x00000080)
#define RTC_CAL_CALM_8 ((uint32_t)0x00000100)
/******************** Bits definition for RTC_TAFCR register ****************/
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) /*!< */
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) /*!< */
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) /*!< */
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) /*!< */
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) /*!< */
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) /*!< */
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) /*!< */
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) /*!< */
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) /*!< */
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) /*!< */
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) /*!< */
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) /*!< */
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) /*!< */
#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040) /*!< */
#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) /*!< */
#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) /*!< */
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) /*!< */
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) /*!< */
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) /*!< */
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) /*!< */
#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) /*!< */
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) /*!< */
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) /*!< */
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) /*!< */
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) /*!< */
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) /*!< */
#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_BKP0R register ****************/
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP1R register ****************/
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP2R register ****************/
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP3R register ****************/
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
/******************** Bits definition for RTC_BKP4R register ****************/
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF) /*!< */
#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
/******************************************************************************/
/* */

4
lib/inc/system_stm32f0xx.h → Libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V1.0.0
* @date 23-March-2012
* @version V1.0.1
* @date 20-April-2012
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention

146
Libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html

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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for STM32F0xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
<ol style="margin-top: 0cm;" start="1" type="1">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F0xx&nbsp;CMSIS
update History</a><o:p></o:p></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F0xx CMSIS
update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 20-April-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add reference to STM32F050xx (Flash memory up to 32 Kbytes) and STM32F051xx (</span><span style="font-size: 10pt; font-family: Verdana;">Flash memory up to 64 Kbytes</span><span style="font-size: 10pt; font-family: Verdana;">) devices</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RTC register bits definition: remove reference to Tamper3</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 23-March-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release&nbsp;for <span style="font-weight: bold; font-style: italic;">STM32F0xx devices</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change MCO bits value:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change <span style="font-style: italic;">RCC_CFGR_MCO_HSI14</span> value from 0x03000000 to 0x01000000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RCC_CFGR_MCO_LSI</span> having value 0x02000000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RCC_CFGR_MCO_LSE</span> having value 0x03000000</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new bit <span style="font-style: italic;">RCC_CSR_V18PWRRSTF</span> having value 0x00800000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_OR</span> bits definition values corrected</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_ISR_EOS</span> to <span style="font-style: italic;">ADC_ISR_EOSEQ</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_IER_EOSIE</span> to <span style="font-style: italic;">ADC_IER_EOSEQIE</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_CFGR1_AUTDLY</span> to <span style="font-style: italic;">ADC_CFGR1_WAIT</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename option bit <span style="font-style: italic;">FLASH_OBR_BOOT1</span> to <span style="font-style: italic;">FLASH_OBR_nBOOT1</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">FLASH_OBR_VDDA_ANALOG</span> to <span style="font-style: italic;">FLASH_OBR_VDDA_MONITOR</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Flash and OB keys (removed from Flash driver)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SetSysClock()</span> function: code optimized&nbsp;</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous&nbsp;formatting<br></span></li></ul></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 27-January-2012<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate 1</span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">All source
files: update disclaimer to add reference to the&nbsp;new license agreement</span></li>
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all peripherals bits definitions<br>
</span></li>
</ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>
<ul style="margin-top: 0in;" type="disc">
</ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">package</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"></span></div><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; color: black;"><br>Unless
required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
the License for the specific language governing permissions and
limitations under the License.</span>
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complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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305
Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s

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/**
******************************************************************************
* @file startup_stm32f0xx.s
* @author MCD Application Team
* @version V1.0.1
* @date 20-April-2012
* @brief STM32F0xx Devices vector table for Atollic toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF108F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_1_IRQHandler
.word EXTI2_3_IRQHandler
.word EXTI4_15_IRQHandler
.word TS_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_3_IRQHandler
.word DMA1_Channel4_5_IRQHandler
.word ADC1_COMP_IRQHandler
.word TIM1_BRK_UP_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM6_DAC_IRQHandler
.word 0
.word TIM14_IRQHandler
.word TIM15_IRQHandler
.word TIM16_IRQHandler
.word TIM17_IRQHandler
.word I2C1_IRQHandler
.word I2C2_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word CEC_IRQHandler
.word 0
.word BootRAM /* @0x108. This is for boot in RAM mode for
STM32F0xx devices. */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak TS_IRQHandler
.thumb_set TS_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_COMP_IRQHandler
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak I2C2_IRQHandler
.thumb_set I2C2_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

256
Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s

@ -0,0 +1,256 @@
;******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
;* File Name : startup_stm32f0xx.s
;* Author : MCD Application Team
;* Version : V1.0.1
;* Date : 20-April-2012
;* Description : STM32F0xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; @attention
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
;
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD TS_IRQHandler ; TS
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD TIM15_IRQHandler ; TIM15
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD I2C2_IRQHandler ; I2C2
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2