2009-01-30 11:56:28 +00:00
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <cfi_flash.h>
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#include <init.h>
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#include <environment.h>
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#include <asm/arch/imx-regs.h>
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#include <fec.h>
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#include <asm/arch/gpio.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <asm/arch/pmic.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <spi/spi.h>
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#include <asm/io.h>
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#include <asm/arch/imx-nand.h>
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2009-04-07 10:00:47 +00:00
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#include <asm/arch/iomux-mx35.h>
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2009-01-30 11:56:28 +00:00
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static struct device_d cfi_dev = {
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.name = "cfi_flash",
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.map_base = 0xa0000000,
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.size = 64 * 1024 * 1024,
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};
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2009-06-10 22:12:02 +00:00
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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2009-01-30 11:56:28 +00:00
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2009-06-10 22:12:02 +00:00
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static struct device_d sdram_dev = {
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.name = "mem",
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2009-01-30 11:56:28 +00:00
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.map_base = 0x80000000,
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.size = 128 * 1024 * 1024,
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2009-06-10 22:12:02 +00:00
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.platform_data = &ram_pdata,
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2009-01-30 11:56:28 +00:00
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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static struct device_d fec_dev = {
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2009-02-21 00:31:59 +00:00
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.name = "fec_imx",
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2009-01-30 11:56:28 +00:00
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.map_base = 0x50038000,
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.platform_data = &fec_info,
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};
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/*
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* SMSC 9217 network controller
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*/
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static struct device_d smc911x_dev = {
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.name = "smc911x",
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.map_base = IMX_CS5_BASE,
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.size = IMX_CS5_RANGE, /* area size */
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};
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static int f3s_devices_init(void)
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{
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register_device(&cfi_dev);
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register_device(&sdram_dev);
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register_device(&smc911x_dev);
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/* FEC is currently broken. It seems to work
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* shortly but after a few moments the board
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* goes to nirvana
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*/
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// register_device(&fec_dev);
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/*
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* Create partitions that should be
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* not touched by any regular user
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*/
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2009-09-29 06:49:20 +00:00
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devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); /* ourself */
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devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); /* environment */
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2009-01-30 11:56:28 +00:00
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2009-06-10 18:24:54 +00:00
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armlinux_add_dram(&sdram_dev);
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2009-01-30 11:56:28 +00:00
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_PCM037); /* FIXME */
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return 0;
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}
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device_initcall(f3s_devices_init);
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static struct device_d f3s_serial_device = {
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.name = "imx_serial",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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};
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2009-04-07 10:00:47 +00:00
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static struct pad_desc f3s_pads[] = {
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MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
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MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
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MX35_PAD_FEC_RX_DV__FEC_RX_DV,
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MX35_PAD_FEC_COL__FEC_COL,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_TX_EN__FEC_TX_EN,
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MX35_PAD_FEC_MDC__FEC_MDC,
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MX35_PAD_FEC_MDIO__FEC_MDIO,
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MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
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MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
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MX35_PAD_FEC_CRS__FEC_CRS,
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MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
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MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
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MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
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MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
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MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
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MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
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MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
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MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
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MX35_PAD_RXD1__UART1_RXD_MUX,
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MX35_PAD_TXD1__UART1_TXD_MUX,
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MX35_PAD_RTS1__UART1_RTS,
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MX35_PAD_CTS1__UART1_CTS,
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};
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2009-01-30 11:56:28 +00:00
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static int f3s_console_init(void)
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{
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2009-04-07 10:00:47 +00:00
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mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads));
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2009-01-30 11:56:28 +00:00
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register_device(&f3s_serial_device);
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return 0;
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}
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console_initcall(f3s_console_init);
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static int f3s_core_setup(void)
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{
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u32 tmp;
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writel(0x0000D843, CSCR_U(5)); /* CS5: smc9117 */
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writel(0x22252521, CSCR_L(5));
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writel(0x22220A00, CSCR_A(5));
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/* FIXME: The rest is currently done in Assembler. Remove assembler
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* config once the board is running stable
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*/
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return 0;
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, IMX_AIPS1_BASE);
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writel(0x77777777, IMX_AIPS1_BASE + 0x4);
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writel(0x77777777, IMX_AIPS2_BASE);
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writel(0x77777777, IMX_AIPS2_BASE + 0x4);
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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writel(0x0, IMX_AIPS1_BASE + 0x40);
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writel(0x0, IMX_AIPS1_BASE + 0x44);
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writel(0x0, IMX_AIPS1_BASE + 0x48);
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writel(0x0, IMX_AIPS1_BASE + 0x4C);
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tmp = readl(IMX_AIPS1_BASE + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, IMX_AIPS1_BASE + 0x50);
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writel(0x0, IMX_AIPS2_BASE + 0x40);
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writel(0x0, IMX_AIPS2_BASE + 0x44);
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writel(0x0, IMX_AIPS2_BASE + 0x48);
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writel(0x0, IMX_AIPS2_BASE + 0x4C);
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tmp = readl(IMX_AIPS2_BASE + 0x50);
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tmp &= 0x00FFFFFF;
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writel(tmp, IMX_AIPS2_BASE + 0x50);
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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#define MAX_PARAM1 0x00302154
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
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writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
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/* SGPCR - always park on last master */
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writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
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writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
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writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
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writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
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writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
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/* MGPCR - restore default values */
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writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
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writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
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writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
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writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
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writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
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writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
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return 0;
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}
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core_initcall(f3s_core_setup);
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