2012-07-31 12:08:00 +00:00
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/*
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* Copyright (C) 2012 Steffen Trumtrar, Pengutronix
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*
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* based on arch/arm/boards/freescale-mx6-arm2/board.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation.
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <environment.h>
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#include <mach/imx-regs.h>
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#include <fec.h>
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#include <mach/gpio.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <miidev.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <mach/generic.h>
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#include <sizes.h>
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#include <net.h>
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#include <mach/imx6.h>
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#include <mach/devices-imx6.h>
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#include <mach/iomux-mx6.h>
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#include <mach/gpio.h>
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#include <spi/spi.h>
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#include <mach/spi.h>
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#define SABRELITE_SD3_WP IMX_GPIO_NR(7, 1)
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#define SABRELITE_SD3_CD IMX_GPIO_NR(7, 0)
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#define SABRELITE_SD4_CD IMX_GPIO_NR(2, 6)
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static iomux_v3_cfg_t sabrelite_pads[] = {
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/* UART1 */
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MX6Q_PAD_SD3_DAT6__UART1_RXD,
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MX6Q_PAD_SD3_DAT7__UART1_TXD,
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MX6Q_PAD_EIM_D26__UART2_TXD,
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MX6Q_PAD_EIM_D27__UART2_RXD,
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/* SD3 (bottom) */
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MX6Q_PAD_SD3_CMD__USDHC3_CMD,
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MX6Q_PAD_SD3_CLK__USDHC3_CLK,
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MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
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MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
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MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
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MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
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MX6Q_PAD_SD3_DAT4__GPIO_7_1, /* WP */
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MX6Q_PAD_SD3_DAT5__GPIO_7_0, /* CD */
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/* SD4 (top) */
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MX6Q_PAD_SD4_CLK__USDHC4_CLK,
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MX6Q_PAD_SD4_CMD__USDHC4_CMD,
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MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
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MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
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MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
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MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
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MX6Q_PAD_NANDF_D6__GPIO_2_6, /* CD */
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/* ECSPI */
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MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
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MX6Q_PAD_EIM_D17__ECSPI1_MISO,
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MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
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MX6Q_PAD_EIM_D19__GPIO_3_19, /* CS1 */
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2012-08-30 12:58:37 +00:00
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2012-08-30 12:58:38 +00:00
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/* I2C0 */
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MX6Q_PAD_EIM_D21__I2C1_SCL,
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MX6Q_PAD_EIM_D28__I2C1_SDA,
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/* I2C1 */
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MX6Q_PAD_KEY_COL3__I2C2_SCL,
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MX6Q_PAD_KEY_ROW3__I2C2_SDA,
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/* I2C2 */
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MX6Q_PAD_GPIO_5__I2C3_SCL,
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MX6Q_PAD_GPIO_16__I2C3_SDA,
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2012-08-30 12:58:37 +00:00
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/* USB */
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MX6Q_PAD_GPIO_17__GPIO_7_12,
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MX6Q_PAD_EIM_D22__GPIO_3_22,
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MX6Q_PAD_EIM_D30__USBOH3_USBH1_OC,
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2012-07-31 12:08:00 +00:00
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};
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static iomux_v3_cfg_t sabrelite_enet_pads[] = {
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/* Ethernet */
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MX6Q_PAD_ENET_MDC__ENET_MDC,
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MX6Q_PAD_ENET_MDIO__ENET_MDIO,
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MX6Q_PAD_ENET_REF_CLK__GPIO_1_23, // LED mode
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
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MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
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MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
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MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
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MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
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MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
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MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
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MX6Q_PAD_EIM_D23__GPIO_3_23, /* RGMII_nRST */
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MX6Q_PAD_RGMII_RXC__GPIO_6_30, /* PHYAD */
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MX6Q_PAD_RGMII_RD0__GPIO_6_25, /* MODE0 */
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MX6Q_PAD_RGMII_RD1__GPIO_6_27, /* MODE1 */
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MX6Q_PAD_RGMII_RD2__GPIO_6_28, /* MODE2 */
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MX6Q_PAD_RGMII_RD3__GPIO_6_29, /* MODE3 */
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MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
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};
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static iomux_v3_cfg_t sabrelite_enet2_pads[] = {
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MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
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MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
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MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
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MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
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MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
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MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
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MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
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};
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static int sabrelite_mem_init(void)
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{
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arm_add_mem_device("ram0", 0x10000000, SZ_1G);
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return 0;
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}
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mem_initcall(sabrelite_mem_init);
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static struct fec_platform_data fec_info = {
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.xcv_type = RGMII,
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.phy_addr = 6,
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};
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int mx6_rgmii_rework(void)
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{
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struct mii_device *mdev;
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mdev = mii_open("phy0");
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if (!mdev) {
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printf("unable to open phy0\n");
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return -ENODEV;
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}
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mii_write(mdev, mdev->address, 0x09, 0x0f00);
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/* do same as linux kernel */
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/* min rx data delay */
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mii_write(mdev, mdev->address, 0x0b, 0x8105);
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mii_write(mdev, mdev->address, 0x0c, 0x0000);
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/* max rx/tx clock delay, min rx/tx control delay */
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mii_write(mdev, mdev->address, 0x0b, 0x8104);
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mii_write(mdev, mdev->address, 0x0c, 0xf0f0);
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mii_write(mdev, mdev->address, 0x0b, 0x104);
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mii_close(mdev);
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return 0;
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}
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static int sabrelite_ksz9021rn_setup(void)
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{
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mxc_iomux_v3_setup_multiple_pads(sabrelite_enet_pads, ARRAY_SIZE(sabrelite_enet_pads));
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gpio_direction_output(87, 0); /* GPIO 3-23 */
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gpio_direction_output(190, 1); /* GPIO 6-30: PHYAD2 */
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/* LED-Mode: Tri-Color Dual LED Mode */
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gpio_direction_output(23 , 0); /* GPIO 1-23 */
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/* MODE strap-in pins: advertise all capabilities */
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gpio_direction_output(185, 1); /* GPIO 6-25 */
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gpio_direction_output(187, 1); /* GPIO 6-27 */
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gpio_direction_output(188, 1); /* GPIO 6-28*/
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gpio_direction_output(189, 1); /* GPIO 6-29 */
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/* Enable 125 MHz clock output */
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gpio_direction_output(184, 1); /* GPIO 6-24 */
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mdelay(10);
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gpio_set_value(87, 1);
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mxc_iomux_v3_setup_multiple_pads(sabrelite_enet2_pads, ARRAY_SIZE(sabrelite_enet2_pads));
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return 0;
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}
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static inline int imx6_iim_register_fec_ethaddr(void)
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{
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u32 value;
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u8 buf[6];
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value = readl(MX6_OCOTP_BASE_ADDR + 0x630);
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buf[0] = (value >> 8);
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buf[1] = value;
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value = readl(MX6_OCOTP_BASE_ADDR + 0x620);
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buf[2] = value >> 24;
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buf[3] = value >> 16;
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buf[4] = value >> 8;
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buf[5] = value;
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eth_register_ethaddr(0, buf);
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return 0;
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}
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static int sabrelite_spi_cs[] = {GPIO_PORTC + 19};
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static struct spi_imx_master sabrelite_spi_0_data = {
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.chipselect = sabrelite_spi_cs,
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.num_chipselect = ARRAY_SIZE(sabrelite_spi_cs),
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};
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static const struct spi_board_info sabrelite_spi_board_info[] = {
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{
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.name = "m25p",
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.max_speed_hz = 40000000,
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.bus_num = 0,
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.chip_select = 0,
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}
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};
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static struct esdhc_platform_data sabrelite_sd3_data = {
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.cd_gpio = SABRELITE_SD3_CD,
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.cd_type = ESDHC_CD_GPIO,
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.wp_gpio = SABRELITE_SD3_WP,
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.wp_type = ESDHC_WP_GPIO,
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};
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static struct esdhc_platform_data sabrelite_sd4_data = {
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.cd_gpio = SABRELITE_SD4_CD,
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.cd_type = ESDHC_CD_GPIO,
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.wp_type = ESDHC_WP_NONE,
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};
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2012-08-30 12:58:37 +00:00
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static void sabrelite_ehci_init(void)
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{
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imx6_usb_phy1_disable_oc();
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imx6_usb_phy1_enable();
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/* hub reset */
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gpio_direction_output(204, 0);
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udelay(2000);
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gpio_set_value(204, 1);
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add_generic_usb_ehci_device(1, MX6_USBOH3_USB_BASE_ADDR + 0x200, NULL);
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}
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2012-07-31 12:08:00 +00:00
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static int sabrelite_devices_init(void)
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{
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imx6_add_mmc2(&sabrelite_sd3_data);
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imx6_add_mmc3(&sabrelite_sd4_data);
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sabrelite_ksz9021rn_setup();
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imx6_iim_register_fec_ethaddr();
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imx6_add_fec(&fec_info);
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mx6_rgmii_rework();
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2012-08-30 12:58:37 +00:00
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sabrelite_ehci_init();
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2012-07-31 12:08:00 +00:00
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spi_register_board_info(sabrelite_spi_board_info,
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ARRAY_SIZE(sabrelite_spi_board_info));
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imx6_add_spi0(&sabrelite_spi_0_data);
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armlinux_set_bootparams((void *)0x10000100);
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armlinux_set_architecture(3769);
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devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
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devfs_add_partition("m25p0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
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return 0;
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}
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device_initcall(sabrelite_devices_init);
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static int sabrelite_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(sabrelite_pads, ARRAY_SIZE(sabrelite_pads));
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imx6_init_lowlevel();
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imx6_add_uart1();
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return 0;
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}
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console_initcall(sabrelite_console_init);
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