2004-08-01 22:48:16 +00:00
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/*
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* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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2009-10-22 12:21:25 +00:00
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#include <mach/imx-regs.h>
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#include <mach/clock.h>
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2007-07-05 16:01:54 +00:00
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#include <driver.h>
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#include <init.h>
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#include <malloc.h>
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2009-05-18 07:10:12 +00:00
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#include <notifier.h>
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2010-06-21 13:19:09 +00:00
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#include <asm/io.h>
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#define URXD0 0x0 /* Receiver Register */
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#define URTX0 0x40 /* Transmitter Register */
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#define UCR1 0x80 /* Control Register 1 */
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#define UCR2 0x84 /* Control Register 2 */
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#define UCR3 0x88 /* Control Register 3 */
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#define UCR4 0x8c /* Control Register 4 */
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#define UFCR 0x90 /* FIFO Control Register */
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#define USR1 0x94 /* Status Register 1 */
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#define USR2 0x98 /* Status Register 2 */
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#define UESC 0x9c /* Escape Character Register */
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#define UTIM 0xa0 /* Escape Timer Register */
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#define UBIR 0xa4 /* BRM Incremental Register */
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#define UBMR 0xa8 /* BRM Modulator Register */
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#define UBRC 0xac /* Baud Rate Count Register */
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2007-10-09 15:18:08 +00:00
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#ifdef CONFIG_ARCH_IMX1
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2010-06-21 13:19:09 +00:00
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#define BIPR1 0xb0 /* Incremental Preset Register 1 */
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#define BIPR2 0xb4 /* Incremental Preset Register 2 */
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#define BIPR3 0xb8 /* Incremental Preset Register 3 */
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#define BIPR4 0xbc /* Incremental Preset Register 4 */
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#define BMPR1 0xc0 /* BRM Modulator Register 1 */
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#define BMPR2 0xc4 /* BRM Modulator Register 2 */
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#define BMPR3 0xc8 /* BRM Modulator Register 3 */
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#define BMPR4 0xcc /* BRM Modulator Register 4 */
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#define UTS 0xd0 /* UART Test Register */
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2009-03-31 09:16:46 +00:00
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#else
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2010-06-21 13:19:09 +00:00
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#define ONEMS 0xb0 /* One Millisecond register */
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#define UTS 0xb4 /* UART Test Register */
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2007-10-17 15:57:55 +00:00
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#endif
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2007-07-05 16:01:24 +00:00
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2007-10-07 22:52:44 +00:00
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/* UART Control Register Bit Fields.*/
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#define URXD_CHARRDY (1<<15)
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#define URXD_ERR (1<<14)
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#define URXD_OVRRUN (1<<13)
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#define URXD_FRMERR (1<<12)
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#define URXD_BRK (1<<11)
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#define URXD_PRERR (1<<10)
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#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
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#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
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#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
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#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
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#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
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#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
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#define UCR1_IREN (1<<7) /* Infrared interface enable */
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#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
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#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
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#define UCR1_SNDBRK (1<<4) /* Send break */
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#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
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#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
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#define UCR1_DOZE (1<<1) /* Doze */
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#define UCR1_UARTEN (1<<0) /* UART enabled */
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#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
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#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
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#define UCR2_CTSC (1<<13) /* CTS pin control */
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#define UCR2_CTS (1<<12) /* Clear to send */
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#define UCR2_ESCEN (1<<11) /* Escape enable */
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#define UCR2_PREN (1<<8) /* Parity enable */
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#define UCR2_PROE (1<<7) /* Parity odd/even */
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#define UCR2_STPB (1<<6) /* Stop */
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#define UCR2_WS (1<<5) /* Word size */
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#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
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#define UCR2_TXEN (1<<2) /* Transmitter enabled */
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#define UCR2_RXEN (1<<1) /* Receiver enabled */
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#define UCR2_SRST (1<<0) /* SW reset */
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#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
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#define UCR3_PARERREN (1<<12) /* Parity enable */
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#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
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#define UCR3_DSR (1<<10) /* Data set ready */
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#define UCR3_DCD (1<<9) /* Data carrier detect */
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#define UCR3_RI (1<<8) /* Ring indicator */
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#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
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#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
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#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
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#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
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2007-10-09 15:18:08 +00:00
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#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz (i.MXL / i.MX1) */
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#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz (i.MXL / i.MX1) */
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#define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed input select (i.MX27) */
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2007-10-07 22:52:44 +00:00
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#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
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#define UCR3_BPEN (1<<0) /* Preset registers enable */
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#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
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#define UCR4_INVR (1<<9) /* Inverted infrared reception */
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#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
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#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
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#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
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#define UCR4_IRSC (1<<5) /* IR special case */
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#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
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#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
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#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
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#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
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#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
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#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
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#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
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#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
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#define USR1_RTSS (1<<14) /* RTS pin status */
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#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
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#define USR1_RTSD (1<<12) /* RTS delta */
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#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
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#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
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#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
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#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
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#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
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#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
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#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
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#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
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#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
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#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
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#define USR2_IDLE (1<<12) /* Idle condition */
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#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
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#define USR2_WAKE (1<<7) /* Wake */
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#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
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#define USR2_TXDC (1<<3) /* Transmitter complete */
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#define USR2_BRCD (1<<2) /* Break condition */
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#define USR2_ORE (1<<1) /* Overrun error */
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#define USR2_RDR (1<<0) /* Recv data ready */
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#define UTS_FRCPERR (1<<13) /* Force parity error */
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#define UTS_LOOP (1<<12) /* Loop tx and rx */
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#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
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#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
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#define UTS_TXFULL (1<<4) /* TxFIFO full */
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#define UTS_RXFULL (1<<3) /* RxFIFO full */
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#define UTS_SOFTRST (1<<0) /* Software reset */
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2004-08-01 22:48:16 +00:00
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2007-10-17 15:57:55 +00:00
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/*
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* create default values for different platforms
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*/
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2007-10-09 15:18:08 +00:00
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#ifdef CONFIG_ARCH_IMX1
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2007-10-17 22:00:02 +00:00
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# define UCR1_VAL (UCR1_UARTCLKEN)
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2007-10-17 15:57:55 +00:00
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# define UCR3_VAL 0
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# define UCR4_VAL (UCR4_CTSTL_32 | UCR4_REF16)
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2007-10-09 15:18:08 +00:00
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#endif
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2009-04-07 06:55:04 +00:00
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#if defined CONFIG_ARCH_IMX21 || defined CONFIG_ARCH_IMX27
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2007-10-17 22:00:02 +00:00
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# define UCR1_VAL (UCR1_UARTCLKEN)
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2007-10-17 15:57:55 +00:00
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# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL)
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# define UCR4_VAL UCR4_CTSTL_32
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#endif
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2009-11-17 10:24:09 +00:00
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#if defined CONFIG_ARCH_IMX31 || defined CONFIG_ARCH_IMX35 || \
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defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51
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2007-10-17 22:00:02 +00:00
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# define UCR1_VAL (0)
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2007-10-17 15:57:55 +00:00
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# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL)
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# define UCR4_VAL UCR4_CTSTL_32
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2007-10-09 15:18:08 +00:00
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#endif
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2009-05-18 07:10:12 +00:00
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struct imx_serial_priv {
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struct console_device cdev;
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int baudrate;
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struct notifier_block notify;
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2010-10-15 07:01:59 +00:00
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void __iomem *regs;
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2009-05-18 07:10:12 +00:00
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};
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2010-10-15 07:01:59 +00:00
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static int imx_serial_reffreq(void __iomem *regs)
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2007-10-09 15:18:08 +00:00
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{
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ulong rfdiv;
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2010-10-15 07:01:59 +00:00
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rfdiv = (readl(regs + UFCR) >> 7) & 7;
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2007-10-09 15:18:08 +00:00
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rfdiv = rfdiv < 6 ? 6 - rfdiv : 7;
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2009-01-07 16:07:48 +00:00
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return imx_get_uartclk() / rfdiv;
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2007-10-09 15:18:08 +00:00
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}
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2004-08-01 22:48:16 +00:00
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*
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*/
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2007-07-05 16:01:54 +00:00
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static int imx_serial_init_port(struct console_device *cdev)
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2004-08-01 22:48:16 +00:00
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{
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2010-10-15 07:01:59 +00:00
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struct imx_serial_priv *priv = container_of(cdev,
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struct imx_serial_priv, cdev);
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void __iomem *regs = priv->regs;
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2010-06-21 13:19:09 +00:00
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uint32_t val;
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2010-10-15 07:01:59 +00:00
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writel(UCR1_VAL, regs + UCR1);
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writel(UCR2_WS | UCR2_IRTS, regs + UCR2);
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writel(UCR3_VAL, regs + UCR3);
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writel(UCR4_VAL, regs + UCR4);
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writel(0x0000002B, regs + UESC);
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writel(0, regs + UTIM);
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writel(0, regs + UBIR);
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writel(0, regs + UBMR);
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writel(0, regs + UTS);
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2007-10-07 22:52:44 +00:00
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2004-08-01 22:48:16 +00:00
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/* Configure FIFOs */
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2010-10-15 07:01:59 +00:00
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writel(0xa81, regs + UFCR);
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2004-08-01 22:48:16 +00:00
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2009-01-30 11:55:35 +00:00
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#ifdef ONEMS
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2010-10-15 07:01:59 +00:00
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writel(imx_serial_reffreq(regs) / 1000, regs + ONEMS);
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2007-10-09 15:18:08 +00:00
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#endif
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2004-08-01 22:48:16 +00:00
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/* Enable FIFOs */
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2010-10-15 07:01:59 +00:00
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val = readl(regs + UCR2);
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2010-06-21 13:19:09 +00:00
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val |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
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2010-10-15 07:01:59 +00:00
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writel(val, regs + UCR2);
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2004-08-01 22:48:16 +00:00
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/* Clear status flags */
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2010-10-15 07:01:59 +00:00
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val = readl(regs + USR2);
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2010-06-21 13:19:09 +00:00
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val |= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_IRINT | USR2_WAKE |
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USR2_RTSF | USR2_BRCD | USR2_ORE | USR2_RDR;
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2010-10-15 07:01:59 +00:00
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writel(val, regs + USR2);
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2004-08-01 22:48:16 +00:00
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/* Clear status flags */
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2010-10-15 07:01:59 +00:00
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val = readl(regs + USR2);
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2010-06-21 13:19:09 +00:00
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val |= USR1_PARITYERR | USR1_RTSD | USR1_ESCF | USR1_FRAMERR | USR1_AIRINT |
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USR1_AWAKE;
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2010-10-15 07:01:59 +00:00
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writel(val, regs + USR2);
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2007-10-07 22:52:44 +00:00
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2007-07-05 16:01:24 +00:00
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return 0;
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2004-08-01 22:48:16 +00:00
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}
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2007-07-05 16:01:54 +00:00
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static void imx_serial_putc(struct console_device *cdev, char c)
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2007-07-05 16:01:39 +00:00
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{
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2010-10-15 07:01:59 +00:00
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struct imx_serial_priv *priv = container_of(cdev,
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struct imx_serial_priv, cdev);
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2007-07-05 16:01:54 +00:00
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/* Wait for Tx FIFO not full */
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2010-10-15 07:01:59 +00:00
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while (readl(priv->regs + UTS) & UTS_TXFULL);
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2007-07-05 16:01:54 +00:00
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2010-10-15 07:01:59 +00:00
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writel(c, priv->regs + URTX0);
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2007-07-05 16:01:39 +00:00
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}
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2007-07-05 16:01:54 +00:00
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static int imx_serial_tstc(struct console_device *cdev)
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{
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2010-10-15 07:01:59 +00:00
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struct imx_serial_priv *priv = container_of(cdev,
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struct imx_serial_priv, cdev);
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2007-07-05 16:01:54 +00:00
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/* If receive fifo is empty, return false */
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2010-10-15 07:01:59 +00:00
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if (readl(priv->regs + UTS) & UTS_RXEMPTY)
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2007-07-05 16:01:54 +00:00
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return 0;
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return 1;
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|
|
}
|
|
|
|
|
|
|
|
static int imx_serial_getc(struct console_device *cdev)
|
2004-08-01 22:48:16 +00:00
|
|
|
{
|
2010-10-15 07:01:59 +00:00
|
|
|
struct imx_serial_priv *priv = container_of(cdev,
|
|
|
|
struct imx_serial_priv, cdev);
|
2004-08-01 22:48:16 +00:00
|
|
|
unsigned char ch;
|
|
|
|
|
2010-10-15 07:01:59 +00:00
|
|
|
while (readl(priv->regs + UTS) & UTS_RXEMPTY);
|
2004-08-01 22:48:16 +00:00
|
|
|
|
2010-10-15 07:01:59 +00:00
|
|
|
ch = readl(priv->regs + URXD0);
|
2004-08-01 22:48:16 +00:00
|
|
|
|
|
|
|
return ch;
|
|
|
|
}
|
|
|
|
|
2009-02-21 00:23:53 +00:00
|
|
|
static void imx_serial_flush(struct console_device *cdev)
|
|
|
|
{
|
2010-10-15 07:01:59 +00:00
|
|
|
struct imx_serial_priv *priv = container_of(cdev,
|
|
|
|
struct imx_serial_priv, cdev);
|
2009-02-21 00:23:53 +00:00
|
|
|
|
2010-10-15 07:01:59 +00:00
|
|
|
while (!(readl(priv->regs + USR2) & USR2_TXDC));
|
2009-02-21 00:23:53 +00:00
|
|
|
}
|
|
|
|
|
2007-10-07 22:52:44 +00:00
|
|
|
static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
|
|
|
|
{
|
2009-05-18 07:10:12 +00:00
|
|
|
struct imx_serial_priv *priv = container_of(cdev,
|
|
|
|
struct imx_serial_priv, cdev);
|
2010-10-15 07:01:59 +00:00
|
|
|
void __iomem *regs = priv->regs;
|
2010-06-21 13:19:09 +00:00
|
|
|
uint32_t val;
|
2010-10-15 07:01:59 +00:00
|
|
|
uint32_t ucr1 = readl(regs + UCR1);
|
2007-10-07 22:52:44 +00:00
|
|
|
|
|
|
|
/* disable UART */
|
2010-10-15 07:01:59 +00:00
|
|
|
val = readl(regs + UCR1);
|
2010-06-21 13:19:09 +00:00
|
|
|
val &= ~UCR1_UARTEN;
|
2010-10-15 07:01:59 +00:00
|
|
|
writel(val, regs + UCR1);
|
2007-10-07 22:52:44 +00:00
|
|
|
|
2007-10-09 15:18:08 +00:00
|
|
|
/* Set the numerator value minus one of the BRM ratio */
|
2010-10-15 07:01:59 +00:00
|
|
|
writel((baudrate / 100) - 1, regs + UBIR);
|
2007-10-09 15:18:08 +00:00
|
|
|
/* Set the denominator value minus one of the BRM ratio */
|
2010-10-15 07:01:59 +00:00
|
|
|
writel((imx_serial_reffreq(regs) / 1600) - 1, regs + UBMR);
|
2007-10-07 22:52:44 +00:00
|
|
|
|
2010-10-15 07:01:59 +00:00
|
|
|
writel(ucr1, regs + UCR1);
|
2007-10-07 22:52:44 +00:00
|
|
|
|
2009-05-18 07:10:12 +00:00
|
|
|
priv->baudrate = baudrate;
|
|
|
|
|
2007-10-07 22:52:44 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-05-18 07:10:12 +00:00
|
|
|
static int imx_clocksource_clock_change(struct notifier_block *nb,
|
|
|
|
unsigned long event, void *data)
|
|
|
|
{
|
|
|
|
struct imx_serial_priv *priv = container_of(nb,
|
|
|
|
struct imx_serial_priv, notify);
|
|
|
|
|
|
|
|
imx_serial_setbaudrate(&priv->cdev, priv->baudrate);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:54 +00:00
|
|
|
static int imx_serial_probe(struct device_d *dev)
|
2004-08-01 22:48:16 +00:00
|
|
|
{
|
2007-07-05 16:01:54 +00:00
|
|
|
struct console_device *cdev;
|
2009-05-18 07:10:12 +00:00
|
|
|
struct imx_serial_priv *priv;
|
2010-06-21 13:19:09 +00:00
|
|
|
uint32_t val;
|
2009-05-18 07:10:12 +00:00
|
|
|
|
2011-01-06 15:23:01 +00:00
|
|
|
priv = xmalloc(sizeof(*priv));
|
2009-05-18 07:10:12 +00:00
|
|
|
cdev = &priv->cdev;
|
2004-08-01 22:48:16 +00:00
|
|
|
|
2011-07-19 06:38:18 +00:00
|
|
|
priv->regs = dev_request_mem_region(dev, 0);
|
2007-07-05 16:01:54 +00:00
|
|
|
dev->type_data = cdev;
|
|
|
|
cdev->dev = dev;
|
2007-07-05 16:02:00 +00:00
|
|
|
cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR;
|
2007-07-05 16:01:54 +00:00
|
|
|
cdev->tstc = imx_serial_tstc;
|
|
|
|
cdev->putc = imx_serial_putc;
|
|
|
|
cdev->getc = imx_serial_getc;
|
2009-02-21 00:23:53 +00:00
|
|
|
cdev->flush = imx_serial_flush;
|
2007-10-07 22:52:44 +00:00
|
|
|
cdev->setbrg = imx_serial_setbaudrate;
|
2004-08-01 22:48:16 +00:00
|
|
|
|
2007-07-05 16:01:54 +00:00
|
|
|
imx_serial_init_port(cdev);
|
2007-10-07 22:52:44 +00:00
|
|
|
imx_serial_setbaudrate(cdev, 115200);
|
|
|
|
|
|
|
|
/* Enable UART */
|
2010-10-15 07:01:59 +00:00
|
|
|
val = readl(priv->regs + UCR1);
|
2010-06-21 13:19:09 +00:00
|
|
|
val |= UCR1_UARTEN;
|
2010-10-15 07:01:59 +00:00
|
|
|
writel(val, priv->regs + UCR1);
|
2004-08-01 22:48:16 +00:00
|
|
|
|
2007-07-05 16:01:54 +00:00
|
|
|
console_register(cdev);
|
2009-05-18 07:10:12 +00:00
|
|
|
priv->notify.notifier_call = imx_clocksource_clock_change;
|
|
|
|
clock_register_client(&priv->notify);
|
2007-07-05 16:01:54 +00:00
|
|
|
|
|
|
|
return 0;
|
2004-08-01 22:48:16 +00:00
|
|
|
}
|
|
|
|
|
2009-02-21 00:23:53 +00:00
|
|
|
static void imx_serial_remove(struct device_d *dev)
|
|
|
|
{
|
|
|
|
struct console_device *cdev = dev->type_data;
|
|
|
|
|
|
|
|
imx_serial_flush(cdev);
|
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:54 +00:00
|
|
|
static struct driver_d imx_serial_driver = {
|
2009-02-21 00:23:53 +00:00
|
|
|
.name = "imx_serial",
|
|
|
|
.probe = imx_serial_probe,
|
|
|
|
.remove = imx_serial_remove,
|
2007-07-05 16:01:54 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int imx_serial_init(void)
|
2004-08-01 22:48:16 +00:00
|
|
|
{
|
2007-07-05 16:01:54 +00:00
|
|
|
register_driver(&imx_serial_driver);
|
|
|
|
return 0;
|
2004-08-01 22:48:16 +00:00
|
|
|
}
|
2007-07-05 16:01:24 +00:00
|
|
|
|
2007-07-05 16:01:54 +00:00
|
|
|
console_initcall(imx_serial_init);
|