2008-10-27 16:20:26 +00:00
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/*
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*
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* (c) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <gpio.h>
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#define OFS_PIO_PER 0x00 /* Enable Register */
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#define OFS_PIO_PDR 0x04 /* Disable Register */
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#define OFS_PIO_PSR 0x08 /* Status Register */
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#define OFS_PIO_OER 0x10 /* Output Enable Register */
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#define OFS_PIO_ODR 0x14 /* Output Disable Register */
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#define OFS_PIO_OSR 0x18 /* Output Status Register */
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#define OFS_PIO_IFER 0x20 /* Glitch Input Filter Enable */
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#define OFS_PIO_IFDR 0x24 /* Glitch Input Filter Disable */
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#define OFS_PIO_IFSR 0x28 /* Glitch Input Filter Status */
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#define OFS_PIO_SODR 0x30 /* Set Output Data Register */
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#define OFS_PIO_CODR 0x34 /* Clear Output Data Register */
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#define OFS_PIO_ODSR 0x38 /* Output Data Status Register */
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#define OFS_PIO_PDSR 0x3c /* Pin Data Status Register */
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#define OFS_PIO_IER 0x40 /* Interrupt Enable Register */
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#define OFS_PIO_IDR 0x44 /* Interrupt Disable Register */
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#define OFS_PIO_IMR 0x48 /* Interrupt Mask Register */
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#define OFS_PIO_ISR 0x4c /* Interrupt Status Register */
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#define OFS_PIO_MDER 0x50 /* Multi-driver Enable Register */
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#define OFS_PIO_MDDR 0x54 /* Multi-driver Disable Register */
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#define OFS_PIO_MDSR 0x58 /* Multi-driver Status Register */
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#define OFS_PIO_PUDR 0x60 /* Pull-up Disable Register */
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#define OFS_PIO_PUER 0x64 /* Pull-up Enable Register */
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#define OFS_PIO_PUSR 0x68 /* Pull-up Status Register */
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#define OFS_PIO_ASR 0x70 /* Peripheral A Select Register */
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#define OFS_PIO_BSR 0x74 /* Peripheral B Select Register */
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#define OFS_PIO_ABSR 0x78 /* AB Status Register */
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#define OFS_PIO_OWER 0xa0 /* Output Write Enable Register */
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#define OFS_PIO_OWDR 0xa4 /* Output Write Disable Register */
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#define OFS_PIO_OWSR 0xa8 /* Output Write Status Register */
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static int gpio_banks;
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static struct at91_gpio_bank *gpio;
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static inline void __iomem *pin_to_controller(unsigned pin)
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{
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pin /= 32;
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if (likely(pin < gpio_banks))
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return gpio[pin].regbase;
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return NULL;
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}
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static inline unsigned pin_to_mask(unsigned pin)
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{
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return 1 << (pin % 32);
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}
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
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* configure it for an input.
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*/
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int at91_set_gpio_input(unsigned pin, int use_pullup)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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2009-06-23 14:17:14 +00:00
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writel(mask, pio + OFS_PIO_IDR);
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writel(mask, pio + (use_pullup ? OFS_PIO_PUER : OFS_PIO_PUDR));
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writel(mask, pio + OFS_PIO_ODR);
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writel(mask, pio + OFS_PIO_PER);
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_input);
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/*
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* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
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* and configure it for an output.
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*/
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int at91_set_gpio_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return -EINVAL;
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2009-06-23 14:17:14 +00:00
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writel(mask, pio + OFS_PIO_IDR);
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writel(mask, pio + OFS_PIO_PUDR);
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writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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writel(mask, pio + OFS_PIO_OER);
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writel(mask, pio + OFS_PIO_PER);
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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EXPORT_SYMBOL(at91_set_gpio_output);
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int gpio_direction_input(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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2009-06-23 14:17:14 +00:00
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if (!pio || !(readl(pio + OFS_PIO_PSR) & mask))
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2008-10-27 16:20:26 +00:00
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return -EINVAL;
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2009-06-23 14:17:14 +00:00
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writel(mask, pio + OFS_PIO_ODR);
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_input);
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int gpio_direction_output(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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2009-06-23 14:17:14 +00:00
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if (!pio || !(readl(pio + OFS_PIO_PSR) & mask))
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2008-10-27 16:20:26 +00:00
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return -EINVAL;
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2009-06-23 14:17:14 +00:00
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writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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writel(mask, pio + OFS_PIO_OER);
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2008-10-27 16:20:26 +00:00
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return 0;
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}
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EXPORT_SYMBOL(gpio_direction_output);
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/*--------------------------------------------------------------------------*/
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/*
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* assuming the pin is muxed as a gpio output, set its value.
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*/
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void gpio_set_value(unsigned pin, int value)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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if (!pio)
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return;
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2009-06-23 14:17:14 +00:00
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writel(mask, pio + (value ? OFS_PIO_SODR : OFS_PIO_CODR));
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2008-10-27 16:20:26 +00:00
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}
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EXPORT_SYMBOL(gpio_set_value);
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/*
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* read the pin's value (works even if it's not muxed as a gpio).
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*/
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int gpio_get_value(unsigned pin)
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{
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void __iomem *pio = pin_to_controller(pin);
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unsigned mask = pin_to_mask(pin);
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u32 pdsr;
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if (!pio)
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return -EINVAL;
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2009-06-23 14:17:14 +00:00
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pdsr = readl(pio + OFS_PIO_PDSR);
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2008-10-27 16:20:26 +00:00
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return (pdsr & mask) != 0;
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}
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EXPORT_SYMBOL(gpio_get_value);
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int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
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{
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unsigned i;
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struct at91_gpio_bank *last;
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gpio = data;
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gpio_banks = nr_banks;
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for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) {
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data->chipbase = i * 32;
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/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
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if (last && last->id == data->id)
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last->next = data;
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}
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return 0;
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}
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