219 lines
5.9 KiB
C
219 lines
5.9 KiB
C
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/generic.h>
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#include <mach/freeze-controller.h>
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#define SYSMGR_FRZCTRL_LOOP_PARAM (1000)
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#define SYSMGR_FRZCTRL_DELAY_LOOP_PARAM (10)
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/*
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* sys_mgr_frzctrl_freeze_req
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* Freeze HPS IOs
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*/
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int sys_mgr_frzctrl_freeze_req(enum frz_channel_id channel_id)
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{
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uint32_t reg, val;
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void *sm = (void *)CYCLONE5_SYSMGR_ADDRESS;
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/* select software FSM */
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writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,
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(sm + SYSMGR_FRZCTRL_SRC_ADDRESS));
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/* Freeze channel ID checking and base address */
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switch (channel_id) {
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case FREEZE_CHANNEL_0:
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case FREEZE_CHANNEL_1:
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case FREEZE_CHANNEL_2:
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reg = SYSMGR_FRZCTRL_VIOCTRL_ADDRESS + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT);
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/*
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* Assert active low enrnsl, plniotri
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* and niotri signals
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*/
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val = readl(sm + reg);
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val &= ~(SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
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| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
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| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK);
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writel(val, sm + reg);
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/*
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* Note: Delay for 20ns at min
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* Assert active low bhniotri signal and de-assert
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* active high csrdone
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*/
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val = readl(sm + reg);
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val &= ~(SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK);
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writel(val, sm + reg);
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break;
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case FREEZE_CHANNEL_3:
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/*
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* Assert active low enrnsl, plniotri and
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* niotri signals
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val &= ~(SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
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| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
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| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK);
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/*
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* Note: Delay for 40ns at min
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* assert active low bhniotri & nfrzdrv signals,
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* de-assert active high csrdone and assert
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* active high frzreg and nfrzdrv signals
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val &= ~(SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
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| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK);
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val |= SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
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| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/*
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* Note: Delay for 40ns at min
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* assert active high reinit signal and de-assert
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* active high pllbiasen signals
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val &= ~(SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
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val |= SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* sys_mgr_frzctrl_thaw_req
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* Unfreeze/Thaw HPS IOs
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*/
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int sys_mgr_frzctrl_thaw_req(enum frz_channel_id channel_id)
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{
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uint32_t reg, val;
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void *sm = (void *)CYCLONE5_SYSMGR_ADDRESS;
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/* select software FSM */
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writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, sm + SYSMGR_FRZCTRL_SRC_ADDRESS);
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/* Freeze channel ID checking and base address */
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switch (channel_id) {
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case FREEZE_CHANNEL_0:
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case FREEZE_CHANNEL_1:
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case FREEZE_CHANNEL_2:
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reg = SYSMGR_FRZCTRL_VIOCTRL_ADDRESS +
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(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT);
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/*
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* Assert active low bhniotri signal and
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* de-assert active high csrdone
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*/
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val = readl(sm + reg);
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val |= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK |
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SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
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writel(val, sm + reg);
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/*
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* Note: Delay for 20ns at min
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* de-assert active low plniotri and niotri signals
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*/
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val = readl(sm + reg);
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val |= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK |
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SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
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writel(val, sm + reg);
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/*
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* Note: Delay for 20ns at min
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* de-assert active low enrnsl signal
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*/
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val = readl(sm + reg);
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val |= SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK;
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writel(val, sm + reg);
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break;
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case FREEZE_CHANNEL_3:
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/* de-assert active high reinit signal */
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val &= ~SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/*
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* Note: Delay for 40ns at min
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* assert active high pllbiasen signals
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val |= SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/*
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* Delay 1000 intosc. intosc is based on eosc1
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* At 25MHz this would be 40us. Play safe, we have time...
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*/
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__udelay(1000);
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/*
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* de-assert active low bhniotri signals,
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* assert active high csrdone and nfrzdrv signal
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val |= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK |
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SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
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val &= ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/* Delay 33 intosc */
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__udelay(100);
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/* de-assert active low plniotri and niotri signals */
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val |= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK |
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SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/*
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* Note: Delay for 40ns at min
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* de-assert active high frzreg signal
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val &= ~SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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/*
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* Note: Delay for 40ns at min
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* de-assert active low enrnsl signal
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*/
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val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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val |= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK;
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writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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