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barebox/drivers/spi/imx_spi.c

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/*
* Copyright (C) 2008 Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
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#include <common.h>
#include <init.h>
#include <driver.h>
#include <spi/spi.h>
#include <xfuncs.h>
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#include <asm/io.h>
#include <gpio.h>
#include <mach/spi.h>
#include <mach/generic.h>
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#define CSPI_0_0_RXDATA 0x00
#define CSPI_0_0_TXDATA 0x04
#define CSPI_0_0_CTRL 0x08
#define CSPI_0_0_INT 0x0C
#define CSPI_0_0_DMA 0x18
#define CSPI_0_0_STAT 0x0C
#define CSPI_0_0_PERIOD 0x14
#define CSPI_0_0_TEST 0x10
#define CSPI_0_0_RESET 0x1C
#define CSPI_0_0_CTRL_ENABLE (1 << 10)
#define CSPI_0_0_CTRL_MASTER (1 << 11)
#define CSPI_0_0_CTRL_XCH (1 << 9)
#define CSPI_0_0_CTRL_LOWPOL (1 << 5)
#define CSPI_0_0_CTRL_PHA (1 << 6)
#define CSPI_0_0_CTRL_SSCTL (1 << 7)
#define CSPI_0_0_CTRL_HIGHSSPOL (1 << 8)
#define CSPI_0_0_CTRL_CS(x) (((x) & 0x3) << 19)
#define CSPI_0_0_CTRL_BITCOUNT(x) (((x) & 0x1f) << 0)
#define CSPI_0_0_CTRL_DATARATE(x) (((x) & 0x7) << 14)
#define CSPI_0_0_CTRL_MAXDATRATE 0x10
#define CSPI_0_0_CTRL_DATAMASK 0x1F
#define CSPI_0_0_CTRL_DATASHIFT 14
#define CSPI_0_0_STAT_TE (1 << 0)
#define CSPI_0_0_STAT_TH (1 << 1)
#define CSPI_0_0_STAT_TF (1 << 2)
#define CSPI_0_0_STAT_RR (1 << 4)
#define CSPI_0_0_STAT_RH (1 << 5)
#define CSPI_0_0_STAT_RF (1 << 6)
#define CSPI_0_0_STAT_RO (1 << 7)
#define CSPI_0_0_PERIOD_32KHZ (1 << 15)
#define CSPI_0_0_TEST_LBC (1 << 14)
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enum imx_spi_devtype {
#ifdef CONFIG_DRIVER_SPI_IMX1
SPI_IMX_VER_IMX1,
#endif
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
SPI_IMX_VER_0_0,
#endif
#ifdef CONFIG_DRIVER_SPI_IMX_0_4
SPI_IMX_VER_0_4,
#endif
#ifdef CONFIG_DRIVER_SPI_IMX_0_5
SPI_IMX_VER_0_5,
#endif
#ifdef CONFIG_DRIVER_SPI_IMX_0_7
SPI_IMX_VER_0_7,
#endif
#ifdef CONFIG_DRIVER_SPI_IMX_2_3
SPI_IMX_VER_2_3,
#endif
};
struct imx_spi {
struct spi_master master;
int *cs_array;
void __iomem *regs;
unsigned int (*xchg_single)(struct imx_spi *imx, u32 data);
void (*chipselect)(struct spi_device *spi, int active);
};
struct spi_imx_devtype_data {
unsigned int (*xchg_single)(struct imx_spi *imx, u32 data);
void (*chipselect)(struct spi_device *spi, int active);
};
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static int imx_spi_setup(struct spi_device *spi)
{
debug("%s mode 0x%08x bits_per_word: %d speed: %d\n",
__FUNCTION__, spi->mode, spi->bits_per_word,
spi->max_speed_hz);
return 0;
}
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
static unsigned int cspi_0_0_xchg_single(struct imx_spi *imx, unsigned int data)
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{
void __iomem *base = imx->regs;
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unsigned int cfg_reg = readl(base + CSPI_0_0_CTRL);
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writel(data, base + CSPI_0_0_TXDATA);
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cfg_reg |= CSPI_0_0_CTRL_XCH;
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writel(cfg_reg, base + CSPI_0_0_CTRL);
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while (!(readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR));
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return readl(base + CSPI_0_0_RXDATA);
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}
static void cspi_0_0_chipselect(struct spi_device *spi, int is_active)
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{
struct spi_master *master = spi->master;
struct imx_spi *imx = container_of(master, struct imx_spi, master);
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ulong base = master->dev->map_base;
unsigned int cs = 0;
int gpio = imx->cs_array[spi->chip_select];
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u32 ctrl_reg;
if (spi->mode & SPI_CS_HIGH)
cs = 1;
if (!is_active) {
if (gpio >= 0)
gpio_set_value(gpio, !cs);
return;
}
ctrl_reg = CSPI_0_0_CTRL_BITCOUNT(spi->bits_per_word - 1)
| CSPI_0_0_CTRL_DATARATE(7) /* FIXME: calculate data rate */
| CSPI_0_0_CTRL_ENABLE
| CSPI_0_0_CTRL_MASTER;
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if (gpio < 0) {
ctrl_reg |= CSPI_0_0_CTRL_CS(gpio + 32);
}
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if (spi->mode & SPI_CPHA)
ctrl_reg |= CSPI_0_0_CTRL_PHA;
if (spi->mode & SPI_CPOL)
ctrl_reg |= CSPI_0_0_CTRL_LOWPOL;
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if (spi->mode & SPI_CS_HIGH)
ctrl_reg |= CSPI_0_0_CTRL_HIGHSSPOL;
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writel(ctrl_reg, base + CSPI_0_0_CTRL);
if (gpio >= 0)
gpio_set_value(gpio, cs);
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}
#endif
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static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg)
{
struct spi_master *master = spi->master;
struct imx_spi *imx = container_of(master, struct imx_spi, master);
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struct spi_transfer *t = NULL;
imx->chipselect(spi, 1);
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list_for_each_entry (t, &mesg->transfers, transfer_list) {
const u32 *txbuf = t->tx_buf;
u32 *rxbuf = t->rx_buf;
int i = 0;
while(i < t->len >> 2) {
rxbuf[i] = imx->xchg_single(imx, txbuf[i]);
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i++;
}
}
imx->chipselect(spi, 0);
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return 0;
}
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static struct spi_imx_devtype_data spi_imx_devtype_data[] = {
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
[SPI_IMX_VER_0_0] = {
.chipselect = cspi_0_0_chipselect,
.xchg_single = cspi_0_0_xchg_single,
},
#endif
};
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static int imx_spi_probe(struct device_d *dev)
{
struct spi_master *master;
struct imx_spi *imx;
struct spi_imx_master *pdata = dev->platform_data;
enum imx_spi_devtype version;
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imx = xzalloc(sizeof(*imx));
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master = &imx->master;
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master->dev = dev;
master->setup = imx_spi_setup;
master->transfer = imx_spi_transfer;
master->num_chipselect = pdata->num_chipselect;
imx->cs_array = pdata->chipselect;
#ifdef CONFIG_DRIVER_SPI_IMX_0_0
if (cpu_is_mx27())
version = SPI_IMX_VER_0_0;
#endif
imx->chipselect = spi_imx_devtype_data[version].chipselect;
imx->xchg_single = spi_imx_devtype_data[version].xchg_single;
imx->regs = (void __iomem *)dev->map_base;
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writel(CSPI_0_0_CTRL_ENABLE | CSPI_0_0_CTRL_MASTER,
dev->map_base + CSPI_0_0_CTRL);
writel(CSPI_0_0_PERIOD_32KHZ,
dev->map_base + CSPI_0_0_PERIOD);
while (readl(dev->map_base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR)
readl(dev->map_base + CSPI_0_0_RXDATA);
writel(0, dev->map_base + CSPI_0_0_INT);
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spi_register_master(master);
return 0;
}
static struct driver_d imx_spi_driver = {
.name = "imx_spi",
.probe = imx_spi_probe,
};
static int imx_spi_init(void)
{
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register_driver(&imx_spi_driver);
return 0;
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}
device_initcall(imx_spi_init);