2008-02-19 14:59:37 +00:00
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/*
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* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
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* Applications Processor Reference Manual, Rev. 0.2".
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*
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
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.macro sdram_init_sha
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/*
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* DDR on CSD0
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*/
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writel(0x00000008, 0xD8001010)
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writel(0x55555555, 0x10027828)
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writel(0x55555555, 0x10027830)
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writel(0x55555555, 0x10027834)
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writel(0x00005005, 0x10027838)
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writel(0x15555555, 0x1002783C)
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writel(0x00000004, 0xD8001010)
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writel(0x006ac73a, 0xD8001004)
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writel(0x92100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2200000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xb2100000, 0xD8001000)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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ldr r0, =0xA1000000
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mov r1, #0xff
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strb r1, [r0]
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writel(0x82226080, 0xD8001000)
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.endm
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.macro sdram_init_mx27_manual
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/*
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* sdram init sequence, as defined in 18.5.4 of the i.MX27 reference manual
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*/
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1:
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ldr r2, =ESD_ESDCTL0 /* base address of registers */
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ldr r3, =PRE_ALL_CMD /* SMODE=001 */
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str r3,(r2,#0x0) /* put CSD0 in precharge command mode */
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ldr r4, =SDRAM_CSD0 /* CSD0 precharge address (A10=1) */
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str r1,(r4,#0x0) /* precharge CSD0 all banks */
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ldr r3, =AUTO_REF_CMD /* SMODE=010 */
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str r3,(r2,#0x0) /* put array 0 in auto-refresh mode */
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ldr r4, =SDRAM_CSD0_BASE /* CSD0 base address */
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ldr r6,=0x7 /* load loop counter */
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1: ldr r5,(r4,#0x0) /* run auto-refresh cycle to array 0 */
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subs r6,r6,#1 /* decrease counter value */
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bne 1b
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ldr r3, =SET_MODE_REG_CMD /* SMODE=011 */
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str r3,(r2,#0x0) /* setup CSD0 for mode register write */
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ldr r3, =MODE_REG_VAL0 /* array 0 mode register value */
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ldrb r5,(r3,#0x0) /* New mode register value on address bus */
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ldr r3, =NORMAL_MODE /* SMODE=000 */
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str r3,(r2,#0x0) /* setup CSD0 for normal operation */
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ESD_ESDCTL0 .long 0xD8001000 // system/external device dependent data
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SDRAM_CSD0 .long 0x00000000 // system/external device dependent data
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SDRAM_CSD0_BASE .long 0x00000000 // system/external device dependent data
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PRE_ALL_CMD .long 0x00000000 // system/external device dependent data (SMODE=001)
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AUTO_REF_CMD .long 0x00000000 // system/external device dependent data (SMODE=010)
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SET_MODE_REG_CMD .long 0x00000000 // system/external device dependent data (SMODE=011)
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MODE_REG_VAL0 .long 0x00000000 // system/external device dependent data
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NORMAL_MODE .long 0x00000000 // system/external device dependent data (SMODE=000)
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.endm
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.macro sdram_init_uboot
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/* configure 16 bit nor flash on cs0 */
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writel(0x0000CC03, 0xd8002000)
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writel(0xa0330D01, 0xd8002004)
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writel(0x00220800, 0xd8002008)
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/* ddr on csd0 - initial reset */
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writel(0x00000008, 0xD8001010)
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/* configure ddr on csd0 - wait 5000 cycles */
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writel(0x00000004, 0xD8001010)
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writel(0x006ac73a, 0xD8001004)
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writel(0x92100000, 0xD8001000)
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writel(0x12344321, 0xA0000f00)
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writel(0xa2100000, 0xD8001000)
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writel(0x12344321, 0xA0000000)
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writel(0x12344321, 0xA0000000)
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writel(0xb2100000, 0xD8001000)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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ldr r0, =0xA1000000
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mov r1, #0xff
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strb r1, [r0]
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writel(0x82226080, 0xD8001000)
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writel(0xDEADBEEF, 0xA0000000)
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writel(0x0000000c, 0xD8001010)
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.endm
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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/* ahb lite ip interface */
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writel(0x20040304, AIPI1_PSR0)
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writel(0xDFFBFCFB, AIPI1_PSR1)
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writel(0x00000000, AIPI2_PSR0)
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writel(0xFFFFFFFF, AIPI2_PSR1)
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/* disable mpll/spll */
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ldr r0, =CSCR
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ldr r1, [r0]
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bic r1, r1, #0x03
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str r1, [r0]
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/*
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* pll clock initialization - see section 3.4.3 of the i.MX27 manual
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*
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* FIXME: Using the 399*2 MHz values from table 3-8 doens't work
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* with 1.2 V core voltage! Find out if this is
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* documented somewhere.
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*/
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writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */
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writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */
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/*
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* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
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* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
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* System clock (HCLK) = 133 MHz
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*/
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writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
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/* add some delay here */
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mov r1, #0x1000
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1: subs r1, r1, #0x1
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bne 1b
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/* clock gating enable */
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writel(0x00050f08, GPCR)
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/* peripheral clock divider */
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writel(0x23C8F403, PCDR0) /* FIXME */
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writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */
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2008-02-22 15:13:23 +00:00
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/* PERDIV1=04 @266 MHz *
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* /
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2008-02-19 14:59:37 +00:00
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/* skip sdram initialization if we run from ram */
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cmp pc, #0xa0000000
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bls 1f
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cmp pc, #0xc0000000
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bhi 1f
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mov pc,r10
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1:
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sdram_init_sha
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mov pc,r10
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