2007-11-08 15:24:51 +00:00
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/*
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* (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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* (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <malloc.h>
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#include <net.h>
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#include <init.h>
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#include <miiphy.h>
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#include <driver.h>
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#include <miiphy.h>
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#include <fec.h>
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2009-02-20 17:13:26 +00:00
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#include <asm/mmu.h>
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2007-11-08 15:24:51 +00:00
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#include <asm/io.h>
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2009-10-22 12:21:25 +00:00
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#include <mach/imx-regs.h>
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2007-11-08 15:24:51 +00:00
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#include <clock.h>
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2009-10-22 12:21:25 +00:00
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#include <mach/clock.h>
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2007-11-08 15:24:51 +00:00
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#include <xfuncs.h>
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2009-02-20 17:13:26 +00:00
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#include "fec_imx.h"
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2009-08-19 10:04:11 +00:00
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struct fec_frame {
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uint8_t data[1500]; /* actual data */
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int length; /* actual length */
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int used; /* buffer in use or not */
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uint8_t head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
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};
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2007-11-08 15:24:51 +00:00
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/*
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* MII-interface related functions
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*/
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static int fec_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
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uint8_t regAddr, uint16_t * retVal)
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{
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struct eth_device *edev = mdev->edev;
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2009-04-01 13:56:19 +00:00
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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2007-11-08 15:24:51 +00:00
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint64_t start;
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2009-07-30 14:09:59 +00:00
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writel(((imx_get_fecclk() >> 20) / 5) << 1,
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fec->regs + FEC_MII_SPEED);
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2007-11-08 15:24:51 +00:00
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/*
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* reading from any PHY's register is done by properly
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* programming the FEC's MII data register.
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*/
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2009-04-01 13:53:50 +00:00
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writel(FEC_IEVENT_MII, fec->regs + FEC_IEVENT);
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2007-11-08 15:24:51 +00:00
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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2009-04-01 13:53:50 +00:00
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg, fec->regs + FEC_MII_DATA);
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2007-11-08 15:24:51 +00:00
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/*
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* wait for the related interrupt
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*/
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start = get_time_ns();
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2009-04-01 13:53:50 +00:00
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while (!(readl(fec->regs + FEC_IEVENT) & FEC_IEVENT_MII)) {
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2007-11-08 15:24:51 +00:00
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if (is_timeout(start, MSECOND)) {
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printf("Read MDIO failed...\n");
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return -1;
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}
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}
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/*
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* clear mii interrupt bit
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*/
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2009-04-01 13:53:50 +00:00
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writel(FEC_IEVENT_MII, fec->regs + FEC_IEVENT);
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2007-11-08 15:24:51 +00:00
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/*
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* it's now safe to read the PHY's register
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*/
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2009-04-01 13:53:50 +00:00
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*retVal = readl(fec->regs + FEC_MII_DATA);
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2007-11-08 15:24:51 +00:00
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return 0;
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}
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static int fec_miiphy_write(struct miiphy_device *mdev, uint8_t phyAddr,
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uint8_t regAddr, uint16_t data)
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{
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struct eth_device *edev = mdev->edev;
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2009-04-01 13:56:19 +00:00
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struct fec_priv *fec = (struct fec_priv *)edev->priv;
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2007-11-08 15:24:51 +00:00
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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uint64_t start;
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2009-07-30 14:09:59 +00:00
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writel(((imx_get_fecclk() >> 20) / 5) << 1,
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fec->regs + FEC_MII_SPEED);
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2007-11-08 15:24:51 +00:00
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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2009-04-01 13:53:50 +00:00
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FEC_MII_DATA_TA | phy | reg | data, fec->regs + FEC_MII_DATA);
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2007-11-08 15:24:51 +00:00
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/*
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* wait for the MII interrupt
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*/
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start = get_time_ns();
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2009-04-01 13:53:50 +00:00
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while (!(readl(fec->regs + FEC_IEVENT) & FEC_IEVENT_MII)) {
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2007-11-08 15:24:51 +00:00
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if (is_timeout(start, MSECOND)) {
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printf("Write MDIO failed...\n");
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return -1;
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}
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}
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/*
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* clear MII interrupt bit
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*/
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2009-04-01 13:53:50 +00:00
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writel(FEC_IEVENT_MII, fec->regs + FEC_IEVENT);
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2007-11-08 15:24:51 +00:00
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return 0;
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}
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2009-04-01 13:56:19 +00:00
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static int fec_rx_task_enable(struct fec_priv *fec)
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2007-11-08 15:24:51 +00:00
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{
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2009-04-01 13:53:50 +00:00
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writel(1 << 24, fec->regs + FEC_R_DES_ACTIVE);
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2007-11-08 15:24:51 +00:00
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return 0;
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}
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2009-04-01 13:56:19 +00:00
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static int fec_rx_task_disable(struct fec_priv *fec)
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2007-11-08 15:24:51 +00:00
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{
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return 0;
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}
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2009-04-01 13:56:19 +00:00
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static int fec_tx_task_enable(struct fec_priv *fec)
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2007-11-08 15:24:51 +00:00
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{
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2009-04-01 13:53:50 +00:00
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writel(1 << 24, fec->regs + FEC_X_DES_ACTIVE);
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2007-11-08 15:24:51 +00:00
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return 0;
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}
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2009-04-01 13:56:19 +00:00
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static int fec_tx_task_disable(struct fec_priv *fec)
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2007-11-08 15:24:51 +00:00
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{
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return 0;
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}
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/**
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* Initialize receive task's buffer descriptors
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* @param[in] fec all we know about the device yet
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* @param[in] count receive buffer count to be allocated
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* @param[in] size size of each receive buffer
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* @return 0 on success
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*
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* For this task we need additional memory for the data buffers. And each
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* data buffer requires some alignment. Thy must be aligned to a specific
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2007-11-09 11:01:18 +00:00
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* boundary each (DB_DATA_ALIGNMENT).
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2007-11-08 15:24:51 +00:00
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*/
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2009-04-01 13:56:19 +00:00
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static int fec_rbd_init(struct fec_priv *fec, int count, int size)
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2007-11-08 15:24:51 +00:00
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{
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int ix;
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static int once = 0;
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2009-02-20 17:13:26 +00:00
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unsigned long p = 0;
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2007-11-08 15:24:51 +00:00
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if (!once) {
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/* reserve data memory and consider alignment */
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2009-02-20 17:13:26 +00:00
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p = (unsigned long)dma_alloc_coherent(size * count + DB_DATA_ALIGNMENT);
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p += DB_DATA_ALIGNMENT - 1;
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p &= ~(DB_DATA_ALIGNMENT - 1);
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2007-11-08 15:24:51 +00:00
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}
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for (ix = 0; ix < count; ix++) {
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if (!once) {
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2009-09-16 14:27:56 +00:00
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writel(virt_to_phys((void *)p), &fec->rbd_base[ix].data_pointer);
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2007-11-08 15:24:51 +00:00
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p += size;
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}
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writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
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writew(0, &fec->rbd_base[ix].data_length);
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}
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once = 1; /* malloc done now (and once) */
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/*
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* mark the last RBD to close the ring
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*/
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
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fec->rbd_index = 0;
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return 0;
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}
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/**
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* Initialize transmit task's buffer descriptors
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* @param[in] fec all we know about the device yet
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*
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2007-11-09 11:01:18 +00:00
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* Transmit buffers are created externally. We only have to init the BDs here.\n
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2007-11-08 15:24:51 +00:00
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* Note: There is a race condition in the hardware. When only one BD is in
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2008-08-11 07:38:48 +00:00
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* use it must be marked with the WRAP bit to use it for every transmit.
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2007-11-08 15:24:51 +00:00
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* This bit in combination with the READY bit results into double transmit
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* of each data buffer. It seems the state machine checks READY earlier then
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* resetting it after the first transfer.
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* Using two BDs solves this issue.
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*/
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2009-04-01 13:56:19 +00:00
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static void fec_tbd_init(struct fec_priv *fec)
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2007-11-08 15:24:51 +00:00
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{
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writew(0x0000, &fec->tbd_base[0].status);
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writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
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fec->tbd_index = 0;
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}
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/**
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* Mark the given read buffer descriptor as free
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* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
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* @param[in] pRbd buffer descriptor to mark free again
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*/
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2009-04-01 13:59:09 +00:00
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static void fec_rbd_clean(int last, struct buffer_descriptor *pRbd)
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2007-11-08 15:24:51 +00:00
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{
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/*
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* Reset buffer descriptor as empty
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*/
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if (last)
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
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else
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writew(FEC_RBD_EMPTY, &pRbd->status);
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/*
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* no data in it
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*/
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writew(0, &pRbd->data_length);
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}
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static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
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{
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/* no eeprom */
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return -1;
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}
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static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
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{
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2009-04-01 13:56:19 +00:00
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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2007-11-08 15:24:51 +00:00
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/*
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* Set physical address
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*/
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2009-04-01 13:53:50 +00:00
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writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], fec->regs + FEC_PADDR1);
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writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, fec->regs + FEC_PADDR2);
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2007-11-08 15:24:51 +00:00
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return 0;
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}
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static int fec_init(struct eth_device *dev)
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{
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2009-04-01 13:56:19 +00:00
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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2007-11-08 15:24:51 +00:00
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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2009-04-01 13:53:50 +00:00
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writel(0xffffffff, fec->regs + FEC_IEVENT);
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2007-11-08 15:24:51 +00:00
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/*
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* Set interrupt mask register
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*/
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2009-04-01 13:53:50 +00:00
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writel(0x00000000, fec->regs + FEC_IMASK);
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2007-11-08 15:24:51 +00:00
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/*
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* Set FEC-Lite receive control register(R_CNTRL):
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*/
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if (fec->xcv_type == SEVENWIRE) {
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/*
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* Frame length=1518; 7-wire mode
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*/
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2009-04-01 13:53:50 +00:00
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writel((1518 << 16), fec->regs + FEC_R_CNTRL);
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2007-11-08 15:24:51 +00:00
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} else {
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/*
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* Frame length=1518; MII mode;
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*/
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2009-04-01 13:53:50 +00:00
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writel((1518 << 16) | (1 << 2), fec->regs + FEC_R_CNTRL);
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2007-11-08 15:24:51 +00:00
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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*/
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2009-04-01 14:02:35 +00:00
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writel(((imx_get_fecclk() >> 20) / 5) << 1,
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2009-11-20 09:25:34 +00:00
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fec->regs + FEC_MII_SPEED);
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2007-11-08 15:24:51 +00:00
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}
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2009-04-01 13:53:50 +00:00
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if (fec->xcv_type == RMII) {
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/* disable the gasket and wait */
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writel(0, fec->regs + FEC_MIIGSK_ENR);
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while (readl(fec->regs + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
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udelay(1);
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/* configure the gasket for RMII, 50 MHz, no loopback, no echo */
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writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fec->regs + FEC_MIIGSK_CFGR);
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/* re-enable the gasket */
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writel(FEC_MIIGSK_ENR_EN, fec->regs + FEC_MIIGSK_ENR);
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}
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2007-11-08 15:24:51 +00:00
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/*
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|
* Set Opcode/Pause Duration Register
|
|
|
|
*/
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(0x00010020, fec->regs + FEC_OP_PAUSE);
|
|
|
|
writel(0x2, fec->regs + FEC_X_WMRK);
|
2007-11-08 15:24:51 +00:00
|
|
|
/*
|
|
|
|
* Set multicast address filter
|
|
|
|
*/
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(0, fec->regs + FEC_IADDR1);
|
|
|
|
writel(0, fec->regs + FEC_IADDR2);
|
|
|
|
writel(0, fec->regs + FEC_GADDR1);
|
|
|
|
writel(0, fec->regs + FEC_GADDR2);
|
2007-11-08 15:24:51 +00:00
|
|
|
|
|
|
|
/* size of each buffer */
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(FEC_MAX_PKT_SIZE, fec->regs + FEC_EMRBR);
|
2007-11-08 15:24:51 +00:00
|
|
|
|
|
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
|
|
miiphy_restart_aneg(&fec->miiphy);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Start the FEC engine
|
2008-04-04 10:04:15 +00:00
|
|
|
* @param[in] edev Our device to handle
|
2007-11-08 15:24:51 +00:00
|
|
|
*/
|
|
|
|
static int fec_open(struct eth_device *edev)
|
|
|
|
{
|
2009-04-01 13:56:19 +00:00
|
|
|
struct fec_priv *fec = (struct fec_priv *)edev->priv;
|
2009-02-27 15:35:05 +00:00
|
|
|
int ret;
|
2007-11-08 15:24:51 +00:00
|
|
|
|
2009-10-09 09:57:07 +00:00
|
|
|
/*
|
|
|
|
* Initialize RxBD/TxBD rings
|
|
|
|
*/
|
|
|
|
fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
|
|
|
|
fec_tbd_init(fec);
|
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
/* full-duplex, heartbeat disabled */
|
|
|
|
writel(1 << 2, fec->regs + FEC_X_CNTRL);
|
2007-11-08 15:24:51 +00:00
|
|
|
fec->rbd_index = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable FEC-Lite controller
|
|
|
|
*/
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(FEC_ECNTRL_ETHER_EN, fec->regs + FEC_ECNTRL);
|
2007-11-08 15:24:51 +00:00
|
|
|
/*
|
|
|
|
* Enable SmartDMA receive task
|
|
|
|
*/
|
|
|
|
fec_rx_task_enable(fec);
|
|
|
|
|
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
2009-02-27 15:35:05 +00:00
|
|
|
ret = miiphy_wait_aneg(&fec->miiphy);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2007-11-08 15:24:51 +00:00
|
|
|
miiphy_print_status(&fec->miiphy);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Halt the FEC engine
|
|
|
|
* @param[in] dev Our device to handle
|
|
|
|
*/
|
|
|
|
static void fec_halt(struct eth_device *dev)
|
|
|
|
{
|
2009-04-01 13:56:19 +00:00
|
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
2007-11-08 15:24:51 +00:00
|
|
|
int counter = 0xffff;
|
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
/* issue graceful stop command to the FEC transmitter if necessary */
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(readl(fec->regs + FEC_X_CNTRL) | FEC_ECNTRL_RESET,
|
|
|
|
fec->regs + FEC_X_CNTRL);
|
2007-11-08 15:24:51 +00:00
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
/* wait for graceful stop to register */
|
2009-04-01 13:53:50 +00:00
|
|
|
while ((counter--) && (!(readl(fec->regs + FEC_IEVENT) & FEC_IEVENT_GRA)))
|
2007-11-08 15:24:51 +00:00
|
|
|
; /* FIXME ensure time */
|
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
/* Disable SmartDMA tasks */
|
2007-11-08 15:24:51 +00:00
|
|
|
fec_tx_task_disable(fec);
|
|
|
|
fec_rx_task_disable(fec);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable the Ethernet Controller
|
|
|
|
* Note: this will also reset the BD index counter!
|
|
|
|
*/
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(0, fec->regs + FEC_ECNTRL);
|
2007-11-08 15:24:51 +00:00
|
|
|
fec->rbd_index = 0;
|
|
|
|
fec->tbd_index = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Transmit one frame
|
|
|
|
* @param[in] dev Our ethernet device to handle
|
|
|
|
* @param[in] eth_data Pointer to the data to be transmitted
|
|
|
|
* @param[in] data_length Data count in bytes
|
|
|
|
* @return 0 on success
|
|
|
|
*/
|
|
|
|
static int fec_send(struct eth_device *dev, void *eth_data, int data_length)
|
|
|
|
{
|
|
|
|
unsigned int status;
|
2009-02-20 17:05:11 +00:00
|
|
|
uint64_t tmo;
|
2007-11-08 15:24:51 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* This routine transmits one frame. This routine only accepts
|
|
|
|
* 6-byte Ethernet addresses.
|
|
|
|
*/
|
2009-04-01 13:56:19 +00:00
|
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
2007-11-08 15:24:51 +00:00
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
/* Check for valid length of data. */
|
2007-11-08 15:24:51 +00:00
|
|
|
if ((data_length > 1500) || (data_length <= 0)) {
|
|
|
|
printf("Payload (%d) to large!\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
if ((uint32_t)eth_data & (DB_DATA_ALIGNMENT-1))
|
2008-08-11 07:38:48 +00:00
|
|
|
printf("%s: Warning: Transmit data not aligned: %p!\n", __FUNCTION__, eth_data);
|
2007-11-09 08:57:16 +00:00
|
|
|
|
2007-11-08 15:24:51 +00:00
|
|
|
/*
|
2009-02-20 16:42:49 +00:00
|
|
|
* Setup the transmit buffer
|
2007-11-08 15:24:51 +00:00
|
|
|
* Note: We are always using the first buffer for transmission,
|
|
|
|
* the second will be empty and only used to stop the DMA engine
|
|
|
|
*/
|
|
|
|
writew(data_length, &fec->tbd_base[fec->tbd_index].data_length);
|
2009-02-20 17:13:26 +00:00
|
|
|
|
|
|
|
writel((uint32_t)(eth_data), &fec->tbd_base[fec->tbd_index].data_pointer);
|
2010-03-30 08:53:23 +00:00
|
|
|
dma_flush_range((unsigned long)eth_data,
|
|
|
|
(unsigned long)(eth_data + data_length));
|
2007-11-08 15:24:51 +00:00
|
|
|
/*
|
|
|
|
* update BD's status now
|
|
|
|
* This block:
|
|
|
|
* - is always the last in a chain (means no chain)
|
|
|
|
* - should transmitt the CRC
|
|
|
|
* - might be the last BD in the list, so the address counter should
|
|
|
|
* wrap (-> keep the WRAP flag)
|
|
|
|
*/
|
|
|
|
status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
|
|
|
|
status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
|
|
|
|
writew(status, &fec->tbd_base[fec->tbd_index].status);
|
2009-04-01 14:02:35 +00:00
|
|
|
/* Enable SmartDMA transmit task */
|
2007-11-08 15:24:51 +00:00
|
|
|
fec_tx_task_enable(fec);
|
|
|
|
|
2009-04-01 14:02:35 +00:00
|
|
|
/* wait until frame is sent */
|
2009-02-20 17:05:11 +00:00
|
|
|
tmo = get_time_ns();
|
2007-11-08 15:24:51 +00:00
|
|
|
while (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) {
|
2009-02-20 17:05:11 +00:00
|
|
|
if (is_timeout(tmo, 1 * SECOND)) {
|
|
|
|
printf("transmission timeout\n");
|
|
|
|
break;
|
|
|
|
}
|
2007-11-08 15:24:51 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* for next transmission use the other buffer */
|
|
|
|
if (fec->tbd_index)
|
|
|
|
fec->tbd_index = 0;
|
|
|
|
else
|
|
|
|
fec->tbd_index = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Pull one frame from the card
|
|
|
|
* @param[in] dev Our ethernet device to handle
|
|
|
|
* @return Length of packet read
|
|
|
|
*/
|
|
|
|
static int fec_recv(struct eth_device *dev)
|
|
|
|
{
|
2009-04-01 13:56:19 +00:00
|
|
|
struct fec_priv *fec = (struct fec_priv *)dev->priv;
|
2009-04-01 13:59:09 +00:00
|
|
|
struct buffer_descriptor *rbd = &fec->rbd_base[fec->rbd_index];
|
2007-11-08 15:24:51 +00:00
|
|
|
unsigned long ievent;
|
|
|
|
int frame_length, len = 0;
|
2009-08-19 10:04:11 +00:00
|
|
|
struct fec_frame *frame;
|
2007-11-08 15:24:51 +00:00
|
|
|
uint16_t bd_status;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if any critical events have happened
|
|
|
|
*/
|
2009-04-01 13:53:50 +00:00
|
|
|
ievent = readl(fec->regs + FEC_IEVENT);
|
|
|
|
writel(ievent, fec->regs + FEC_IEVENT);
|
2009-02-20 17:05:11 +00:00
|
|
|
|
2007-11-08 15:24:51 +00:00
|
|
|
if (ievent & (FEC_IEVENT_BABT | FEC_IEVENT_XFIFO_ERROR |
|
|
|
|
FEC_IEVENT_RFIFO_ERROR)) {
|
|
|
|
/* BABT, Rx/Tx FIFO errors */
|
|
|
|
fec_halt(dev);
|
|
|
|
fec_init(dev);
|
|
|
|
printf("some error: 0x%08x\n", ievent);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (ievent & FEC_IEVENT_HBERR) {
|
|
|
|
/* Heartbeat error */
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(readl(fec->regs + FEC_X_CNTRL) | 0x1,
|
|
|
|
fec->regs + FEC_X_CNTRL);
|
2007-11-08 15:24:51 +00:00
|
|
|
}
|
|
|
|
if (ievent & FEC_IEVENT_GRA) {
|
|
|
|
/* Graceful stop complete */
|
2009-04-01 13:53:50 +00:00
|
|
|
if (readl(fec->regs + FEC_X_CNTRL) & 0x00000001) {
|
2007-11-08 15:24:51 +00:00
|
|
|
fec_halt(dev);
|
2009-11-20 09:25:34 +00:00
|
|
|
writel(readl(fec->regs + FEC_X_CNTRL) & ~0x00000001,
|
2009-04-01 13:53:50 +00:00
|
|
|
fec->regs + FEC_X_CNTRL);
|
2007-11-08 15:24:51 +00:00
|
|
|
fec_init(dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* ensure reading the right buffer status
|
|
|
|
*/
|
|
|
|
bd_status = readw(&rbd->status);
|
|
|
|
|
|
|
|
if (!(bd_status & FEC_RBD_EMPTY)) {
|
|
|
|
if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
|
|
|
|
((readw(&rbd->data_length) - 4) > 14)) {
|
|
|
|
/*
|
|
|
|
* Get buffer address and size
|
|
|
|
*/
|
2009-09-16 14:27:56 +00:00
|
|
|
frame = phys_to_virt(readl(&rbd->data_pointer));
|
2007-11-08 15:24:51 +00:00
|
|
|
frame_length = readw(&rbd->data_length) - 4;
|
2010-06-02 13:59:16 +00:00
|
|
|
net_receive(frame->data, frame_length);
|
2007-11-08 15:24:51 +00:00
|
|
|
len = frame_length;
|
|
|
|
} else {
|
|
|
|
if (bd_status & FEC_RBD_ERR) {
|
|
|
|
printf("error frame: 0x%08x 0x%08x\n", rbd, bd_status);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* free the current buffer, restart the engine
|
|
|
|
* and move forward to the next buffer
|
|
|
|
*/
|
|
|
|
fec_rbd_clean(fec->rbd_index == (FEC_RBD_NUM - 1) ? 1 : 0, rbd);
|
|
|
|
fec_rx_task_enable(fec);
|
|
|
|
fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
|
|
|
|
}
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
2009-02-21 00:26:16 +00:00
|
|
|
static int fec_probe(struct device_d *dev)
|
2007-11-08 15:24:51 +00:00
|
|
|
{
|
|
|
|
struct fec_platform_data *pdata = (struct fec_platform_data *)dev->platform_data;
|
|
|
|
struct eth_device *edev;
|
2009-04-01 13:56:19 +00:00
|
|
|
struct fec_priv *fec;
|
2007-11-08 15:24:51 +00:00
|
|
|
uint32_t base;
|
2009-01-30 11:54:28 +00:00
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
2007-11-08 15:24:51 +00:00
|
|
|
PCCR0 |= PCCR0_FEC_EN;
|
2009-01-30 11:54:28 +00:00
|
|
|
#endif
|
2010-04-14 08:05:07 +00:00
|
|
|
edev = (struct eth_device *)xzalloc(sizeof(struct eth_device));
|
|
|
|
dev->type_data = edev;
|
|
|
|
fec = (struct fec_priv *)xzalloc(sizeof(*fec));
|
|
|
|
edev->priv = fec;
|
2007-11-08 15:24:51 +00:00
|
|
|
edev->open = fec_open,
|
|
|
|
edev->init = fec_init,
|
|
|
|
edev->send = fec_send,
|
|
|
|
edev->recv = fec_recv,
|
|
|
|
edev->halt = fec_halt,
|
|
|
|
edev->get_ethaddr = fec_get_hwaddr,
|
|
|
|
edev->set_ethaddr = fec_set_hwaddr,
|
|
|
|
|
2009-04-01 13:53:50 +00:00
|
|
|
fec->regs = (void *)dev->map_base;
|
2007-11-08 15:24:51 +00:00
|
|
|
|
|
|
|
/* Reset chip. */
|
2009-04-01 13:53:50 +00:00
|
|
|
writel(FEC_ECNTRL_RESET, fec->regs + FEC_ECNTRL);
|
|
|
|
while(readl(fec->regs + FEC_ECNTRL) & 1) {
|
2007-11-08 15:24:51 +00:00
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* reserve memory for both buffer descriptor chains at once
|
|
|
|
* Datasheet forces the startaddress of each chain is 16 byte aligned
|
|
|
|
*/
|
2009-02-20 17:13:26 +00:00
|
|
|
base = (uint32_t)dma_alloc_coherent((2 + FEC_RBD_NUM) *
|
|
|
|
sizeof(struct buffer_descriptor) + 2 * DB_ALIGNMENT);
|
2009-04-01 14:02:35 +00:00
|
|
|
base += (DB_ALIGNMENT - 1);
|
|
|
|
base &= ~(DB_ALIGNMENT - 1);
|
2009-04-01 13:59:09 +00:00
|
|
|
fec->rbd_base = (struct buffer_descriptor *)base;
|
|
|
|
base += FEC_RBD_NUM * sizeof (struct buffer_descriptor) +
|
|
|
|
(DB_ALIGNMENT - 1);
|
2009-04-01 14:02:35 +00:00
|
|
|
base &= ~(DB_ALIGNMENT - 1);
|
2009-04-01 13:59:09 +00:00
|
|
|
fec->tbd_base = (struct buffer_descriptor *)base;
|
2007-11-08 15:24:51 +00:00
|
|
|
|
2009-09-16 14:27:56 +00:00
|
|
|
writel((uint32_t)virt_to_phys(fec->tbd_base), fec->regs + FEC_ETDSR);
|
|
|
|
writel((uint32_t)virt_to_phys(fec->rbd_base), fec->regs + FEC_ERDSR);
|
2007-11-08 15:24:51 +00:00
|
|
|
|
|
|
|
fec->xcv_type = pdata->xcv_type;
|
|
|
|
|
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
|
|
|
fec->miiphy.read = fec_miiphy_read;
|
|
|
|
fec->miiphy.write = fec_miiphy_write;
|
2009-02-20 17:08:05 +00:00
|
|
|
fec->miiphy.address = pdata->phy_addr;
|
2007-11-08 15:24:51 +00:00
|
|
|
fec->miiphy.flags = pdata->xcv_type == MII10 ? MIIPHY_FORCE_10 : 0;
|
|
|
|
fec->miiphy.edev = edev;
|
|
|
|
|
|
|
|
miiphy_register(&fec->miiphy);
|
|
|
|
}
|
|
|
|
|
|
|
|
eth_register(edev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-02-21 00:26:16 +00:00
|
|
|
static void fec_remove(struct device_d *dev)
|
|
|
|
{
|
|
|
|
struct eth_device *edev = dev->type_data;
|
|
|
|
|
|
|
|
fec_halt(edev);
|
|
|
|
}
|
|
|
|
|
2007-11-09 11:01:18 +00:00
|
|
|
/**
|
|
|
|
* Driver description for registering
|
|
|
|
*/
|
2007-11-08 15:24:51 +00:00
|
|
|
static struct driver_d imx27_driver = {
|
2009-02-21 00:31:59 +00:00
|
|
|
.name = "fec_imx",
|
2009-02-21 00:26:16 +00:00
|
|
|
.probe = fec_probe,
|
|
|
|
.remove = fec_remove,
|
2007-11-08 15:24:51 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int fec_register(void)
|
|
|
|
{
|
|
|
|
register_driver(&imx27_driver);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
device_initcall(fec_register);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @file
|
|
|
|
* @brief Network driver for FreeScale's FEC implementation.
|
|
|
|
* This type of hardware can be found on i.MX27 CPUs
|
|
|
|
*/
|