2009-06-29 10:35:55 +00:00
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/*
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* Copyright (C) 2009 Juergen Beisert, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/**
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* @file
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* @brief a9m2440 Specific Board Initialization routines
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*
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*/
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#include <common.h>
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#include <driver.h>
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#include <init.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <partition.h>
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#include <nand.h>
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#include <asm/io.h>
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#include <asm/arch/s3c24x0-iomap.h>
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#include <asm/arch/s3c24x0-nand.h>
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2009-08-11 14:46:45 +00:00
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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2009-06-29 10:35:55 +00:00
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static struct device_d sdram_dev = {
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2009-08-11 14:46:45 +00:00
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.name = "mem",
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.map_base = CS6_BASE,
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.platform_data = &ram_pdata,
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2009-06-29 10:35:55 +00:00
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};
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static struct s3c24x0_nand_platform_data nand_info = {
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.nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1)
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};
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static struct device_d nand_dev = {
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.name = "s3c24x0_nand",
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.map_base = S3C24X0_NAND_BASE,
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.platform_data = &nand_info,
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};
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/*
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* SMSC 91C111 network controller on the baseboard
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* connected to CS line 1 and interrupt line
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* GPIO3, data width is 32 bit
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*/
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static struct device_d network_dev = {
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.name = "smc91c111",
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.map_base = CS1_BASE + 0x300,
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.size = 16,
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};
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static int a9m2440_devices_init(void)
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{
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uint32_t reg;
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/*
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* detect the current memory size
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*/
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reg = readl(BANKSIZE);
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switch (reg &= 0x7) {
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case 0:
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sdram_dev.size = 32 * 1024 * 1024;
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break;
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case 1:
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sdram_dev.size = 64 * 1024 * 1024;
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break;
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case 2:
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sdram_dev.size = 128 * 1024 * 1024;
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break;
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case 4:
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sdram_dev.size = 2 * 1024 * 1024;
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break;
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case 5:
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sdram_dev.size = 4 * 1024 * 1024;
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break;
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case 6:
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sdram_dev.size = 8 * 1024 * 1024;
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break;
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case 7:
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sdram_dev.size = 16 * 1024 * 1024;
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break;
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}
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/* both banks are present */
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sdram_dev.size <<= 1;
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/* ---------- configure the GPIOs ------------- */
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writel(0x007FFFFF, GPACON);
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writel(0x00000000, GPCCON);
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writel(0x00000000, GPCUP);
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writel(0x00000000, GPDCON);
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writel(0x00000000, GPDUP);
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writel(0xAAAAAAAA, GPECON);
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writel(0x0000E03F, GPEUP);
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writel(0x00000000, GPBCON); /* all inputs */
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writel(0x00000007, GPBUP); /* pullup disabled for GPB0..3 */
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writel(0x00009000, GPFCON); /* GPF7 CLK_INT#, GPF6 Debug-LED */
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writel(0x000000FF, GPFUP);
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writel(readl(GPGDAT) | 0x1010, GPGDAT); /* switch off IDLE_SW#, switch off LCD backlight */
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writel(0x0100A93A, GPGCON); /* switch on USB device */
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writel(0x0000F000, GPGUP);
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writel(0x0029FAAA, GPHCON);
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writel((1 << 12) | (0 << 11), GPJDAT);
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writel(0x0016aaaa, GPJCON);
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writel(~((0<<12)| (1<<11)), GPJUP);
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writel((0 << 12) | (0 << 11), GPJDAT);
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writel(0x0016aaaa, GPJCON);
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writel(0x00001fff, GPJUP);
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writel(0x00000000, DSC0);
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writel(0x00000000, DSC1);
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/*
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* USB port1 normal, USB port0 normal, USB1 pads for device
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* PCLK output on CLKOUT0, UPLL CLK output on CLKOUT1,
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*/
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writel(0x00140, MISCCR);
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/* ----------- configure the access to the outer space ---------- */
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reg = readl(BWSCON);
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/* CS#1 to access the network controller */
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reg &= ~0xf0;
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reg |= 0xe0;
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writel(0x1350, BANKCON1);
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/* CS#2 to the dual 16550 UART */
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reg &= ~0xf00;
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reg |= 0x400;
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writel(0x0d50, BANKCON2);
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writel(reg, BWSCON);
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/* release the reset signal to the network and UART device */
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2009-10-27 18:57:34 +00:00
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reg = readl(MISCCR);
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2009-06-29 10:35:55 +00:00
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reg |= 0x10000;
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writel(reg, MISCCR);
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/* ----------- the devices the boot loader should work with -------- */
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register_device(&nand_dev);
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register_device(&sdram_dev);
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register_device(&network_dev);
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#ifdef CONFIG_NAND
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/* ----------- add some vital partitions -------- */
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2009-07-21 14:55:49 +00:00
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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2009-10-27 18:57:34 +00:00
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dev_add_bb_dev("self_raw", "self0");
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2009-07-21 14:55:49 +00:00
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2009-10-27 18:57:34 +00:00
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devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
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2009-08-11 14:46:45 +00:00
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dev_add_bb_dev("env_raw", "env0");
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2009-06-29 10:35:55 +00:00
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#endif
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2009-08-11 14:46:45 +00:00
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armlinux_add_dram(&sdram_dev);
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2009-06-29 10:35:55 +00:00
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armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
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2009-07-31 10:07:25 +00:00
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armlinux_set_architecture(MACH_TYPE_A9M2440);
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2009-06-29 10:35:55 +00:00
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return 0;
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}
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device_initcall(a9m2440_devices_init);
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#ifdef CONFIG_S3C24XX_NAND_BOOT
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void __bare_init nand_boot(void)
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{
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s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512);
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}
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#endif
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static struct device_d a9m2440_serial_device = {
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.name = "s3c24x0_serial",
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.map_base = UART1_BASE,
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.size = UART1_SIZE,
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};
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static int a9m2440_console_init(void)
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{
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register_device(&a9m2440_serial_device);
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return 0;
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}
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console_initcall(a9m2440_console_init);
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/** @page a9m2440 DIGI's a9m2440
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This CPU card is based on a Samsung S3C2440 CPU. The card is shipped with:
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- S3C2440\@400 MHz or 533 MHz (ARM920T/ARMv4T)
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- 16.9344 MHz crystal reference
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2009-10-27 18:57:36 +00:00
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- SDRAM 32/64/128 MiB
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- Samsung K4M563233E-EE1H (one or two devices for 32 MiB or 64 MiB)
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- 2M x 32bit x 4 Banks Mobile SDRAM
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- CL2\@100 MHz (CAS/RAS delay 19ns)
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- 105 MHz max
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- collumn address size is 9 bits
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- Row cycle time: 69ns
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- Samsung K4M513233C-DG75 (one or two devices for 64 MiB or 128 MiB)
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- 4M x 32bit x 4 Banks Mobile SDRAM
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- CL2\@100MHz (CAS/RAS delay 18ns)
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- 111 MHz max
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- collumn address size is 9 bits
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- Row cycle time: 63ns
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- 64ms refresh period (4k)
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2009-06-29 10:35:55 +00:00
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- 90 pin FBGA
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- 32 bit data bits
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- Extended temperature range (-25<EFBFBD>C...85<EFBFBD>C)
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2009-10-27 18:57:36 +00:00
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- NAND Flash 32/64/128 MiB
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- Samsung KM29U512T (NAND01GW3A0AN6)
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- 64 MiB 3,3V 8-bit
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- ID: 0xEC, 0x76, 0x??, 0xBD
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- Samsung KM29U256T
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- 32 MiB 3,3V 8-bit
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- ID: 0xEC, 0x75, 0x??, 0xBD
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- ST Micro
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- 128 MiB 3,3V 8-bit
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- ID: 0x20, 0x79
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2009-06-29 10:35:55 +00:00
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- 30ns/40ns/20ns
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2009-10-27 18:57:36 +00:00
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- I2C interface, 100 KHz and 400 KHz
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2009-06-29 10:35:55 +00:00
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- Real Time Clock
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- Dallas DS1337
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2009-07-31 10:04:13 +00:00
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- address 0x68
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2009-10-27 18:57:36 +00:00
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- EEPROM
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- ST M24LC64
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- address 0x50
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- 16bit addressing
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2009-06-29 10:35:55 +00:00
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- LCD interface
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- Touch Screen interface
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- Camera interface
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- I2S interface
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- AC97 Audio-CODEC interface
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- SD card interface
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- 3 serial RS232 interfaces
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- Host and device USB interface, USB1.1 compliant
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- Ethernet interface
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2009-10-27 18:57:36 +00:00
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- 10Mbps, Cirrus Logic, CS8900A (on the CPU card)
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2009-06-29 10:35:55 +00:00
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- SPI interface
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- JTAG interface
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2009-07-31 11:03:33 +00:00
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How to get the binary image:
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Using the default configuration:
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@code
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make ARCH=arm a9m2440_defconfig
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@endcode
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Build the binary image:
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@code
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make ARCH=arm CROSS_COMPILE=armv4compiler
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@endcode
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@note replace the armv4compiler with your ARM v4 cross compiler.
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2009-06-29 10:35:55 +00:00
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*/
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