2010-10-11 11:01:44 +00:00
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <common.h>
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#include <init.h>
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#include <environment.h>
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2012-10-11 07:09:29 +00:00
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#include <mach/imx51-regs.h>
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2010-10-11 11:01:44 +00:00
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#include <fec.h>
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2013-08-16 10:26:17 +00:00
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#include <gpio.h>
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2010-10-11 11:01:44 +00:00
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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2013-07-10 07:27:06 +00:00
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#include <of.h>
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2010-10-11 11:01:44 +00:00
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#include <fcntl.h>
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2012-10-15 10:44:00 +00:00
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#include <mach/bbu.h>
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2010-10-11 11:01:44 +00:00
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#include <nand.h>
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2012-03-23 10:21:16 +00:00
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#include <notifier.h>
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2010-10-11 11:01:44 +00:00
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#include <spi/spi.h>
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2012-04-10 19:44:02 +00:00
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#include <mfd/mc13xxx.h>
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2011-09-22 17:02:57 +00:00
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#include <io.h>
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2010-10-11 11:01:44 +00:00
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#include <asm/mmu.h>
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2011-12-16 14:16:54 +00:00
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#include <mach/imx5.h>
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2010-10-11 11:01:44 +00:00
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#include <mach/imx-nand.h>
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#include <mach/spi.h>
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#include <mach/generic.h>
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#include <mach/iomux-mx51.h>
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2010-10-24 18:54:27 +00:00
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#include <mach/devices-imx51.h>
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2012-09-30 16:14:08 +00:00
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#include <mach/revision.h>
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2012-10-15 10:44:00 +00:00
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#include <mach/imx-flash-header.h>
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2010-10-11 11:01:44 +00:00
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#define MX51_CCM_CACRR 0x10
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static void babbage_power_init(void)
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{
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2012-04-10 19:44:09 +00:00
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struct mc13xxx *mc13xxx;
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2010-10-11 11:01:44 +00:00
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u32 val;
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2012-04-10 19:44:09 +00:00
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mc13xxx = mc13xxx_get();
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if (!mc13xxx) {
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printf("could not get PMIC\n");
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2010-10-11 11:01:44 +00:00
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return;
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}
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/* Write needed to Power Gate 2 register */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_POWER_MISC, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x10000;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, val);
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2010-10-11 11:01:44 +00:00
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/* Write needed to update Charger 0 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_CHARGE, 0x0023807F);
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2010-10-11 11:01:44 +00:00
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/* power up the system first */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_POWER_MISC, 0x00200000);
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2010-10-11 11:01:44 +00:00
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2012-04-18 20:02:44 +00:00
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if (imx_silicon_revision() < IMX_CHIP_REV_3_0) {
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2010-10-11 11:01:44 +00:00
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/* Set core voltage to 1.1V */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_0, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x1f;
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val |= 0x14;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_0, val);
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2010-10-11 11:01:44 +00:00
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/* Setup VCC (SW2) to 1.25 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x1f;
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val |= 0x1a;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
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2010-10-11 11:01:44 +00:00
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/* Setup 1V2_DIG1 (SW3) to 1.25 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x1f;
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val |= 0x1a;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
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2010-10-11 11:01:44 +00:00
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} else {
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/* Setup VCC (SW2) to 1.225 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_1, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x1f;
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val |= 0x19;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_1, val);
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2010-10-11 11:01:44 +00:00
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/* Setup 1V2_DIG1 (SW3) to 1.2 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_2, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x1f;
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val |= 0x18;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_2, val);
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2010-10-11 11:01:44 +00:00
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}
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2012-08-04 09:15:53 +00:00
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if (mc13xxx_revision(mc13xxx) < MC13892_REVISION_2_0) {
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2010-10-11 11:01:44 +00:00
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/* Set switchers in PWM mode for Atlas 2.0 and lower */
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/* Setup the switcher mode for SW1 & SW2*/
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x3c0f;
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val |= 0x1405;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
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2010-10-11 11:01:44 +00:00
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/* Setup the switcher mode for SW3 & SW4 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0xf0f;
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val |= 0x505;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
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2010-10-11 11:01:44 +00:00
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} else {
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/* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
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/* Setup the switcher mode for SW1 & SW2*/
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_4, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x3c0f;
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val |= 0x2008;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_4, val);
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2010-10-11 11:01:44 +00:00
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/* Setup the switcher mode for SW3 & SW4 */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SW_5, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0xf0f;
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val |= 0x808;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SW_5, val);
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2010-10-11 11:01:44 +00:00
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}
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/* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_0, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x34030;
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val |= 0x10020;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_0, val);
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2010-10-11 11:01:44 +00:00
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/* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_read(mc13xxx, MC13892_REG_SETTING_1, &val);
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2010-10-11 11:01:44 +00:00
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val &= ~0x1FC;
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val |= 0x1F4;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_SETTING_1, val);
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2010-10-11 11:01:44 +00:00
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/* Configure VGEN3 and VCAM regulators to use external PNP */
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val = 0x208;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
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2010-10-11 11:01:44 +00:00
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udelay(200);
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#define GPIO_LAN8700_RESET (1 * 32 + 14)
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/* Reset the ethernet controller over GPIO */
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gpio_direction_output(GPIO_LAN8700_RESET, 0);
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/* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
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val = 0x49249;
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2012-04-10 19:44:09 +00:00
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mc13xxx_reg_write(mc13xxx, MC13892_REG_MODE_1, val);
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2010-10-11 11:01:44 +00:00
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2012-09-27 07:16:23 +00:00
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udelay(200);
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2010-10-11 11:01:44 +00:00
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gpio_set_value(GPIO_LAN8700_RESET, 1);
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2012-09-27 07:16:23 +00:00
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mdelay(50);
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2010-10-11 11:01:44 +00:00
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}
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2013-06-23 13:49:51 +00:00
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extern char flash_header_imx51_babbage_start[];
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extern char flash_header_imx51_babbage_end[];
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2012-10-15 10:44:00 +00:00
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2013-06-23 14:29:14 +00:00
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static int imx51_babbage_late_init(void)
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2010-10-11 11:01:44 +00:00
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{
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2013-06-23 14:29:14 +00:00
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if (!of_machine_is_compatible("fsl,imx51-babbage"))
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return 0;
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2010-10-11 11:01:44 +00:00
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babbage_power_init();
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2012-03-23 10:21:16 +00:00
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console_flush();
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2012-04-12 16:20:18 +00:00
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imx51_init_lowlevel(800);
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2012-03-23 10:21:16 +00:00
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clock_notifier_call_chain();
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2010-10-11 11:01:44 +00:00
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armlinux_set_bootparams((void *)0x90000100);
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armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);
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2013-05-26 13:31:32 +00:00
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imx51_bbu_internal_mmc_register_handler("mmc", "/dev/mmc0",
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2013-06-23 13:49:51 +00:00
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BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx51_babbage_start,
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flash_header_imx51_babbage_end - flash_header_imx51_babbage_start, 0);
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2012-10-15 10:44:00 +00:00
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2010-10-11 11:01:44 +00:00
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return 0;
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}
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2013-06-23 14:29:14 +00:00
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late_initcall(imx51_babbage_late_init);
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