2003-07-16 21:53:01 +00:00
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/*
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2005-04-13 23:15:10 +00:00
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* (C) Copyright 2003-2005
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2003-07-16 21:53:01 +00:00
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This file is based on mpc4200fec.c,
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* (C) Copyright Motorola, Inc., 2000
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2007-11-05 17:19:31 +00:00
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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2003-07-16 21:53:01 +00:00
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*/
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2007-11-05 11:26:29 +00:00
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#define DEBUG
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2003-07-16 21:53:01 +00:00
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#include <common.h>
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2007-11-05 11:26:29 +00:00
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//#include <asm/arch/mpc5xxx.h>
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2003-07-16 21:53:01 +00:00
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#include <malloc.h>
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#include <net.h>
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2007-07-05 16:01:31 +00:00
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#include <init.h>
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2003-07-16 21:53:01 +00:00
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#include <miiphy.h>
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2007-07-05 16:01:31 +00:00
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#include <driver.h>
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2007-11-05 11:26:29 +00:00
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//#include <asm/arch/sdma.h>
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//#include <asm/arch/fec.h>
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#include <asm-ppc/arch-mpc5200/fec.h>
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//#include <asm/arch/clocks.h>
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2007-07-05 16:02:06 +00:00
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#include <miiphy.h>
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2007-07-05 16:01:31 +00:00
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#include "fec_mpc5200.h"
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2007-11-05 17:19:31 +00:00
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#include <asm/io.h>
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2007-11-05 11:26:29 +00:00
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#ifdef CONFIG_ARCH_IMX27
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#include <asm/arch/imx-regs.h>
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#include <clock.h>
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#include <asm/arch/clock.h>
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#include <xfuncs.h>
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#endif
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2003-07-16 21:53:01 +00:00
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2007-11-05 17:19:31 +00:00
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extern int memory_display(char *addr, ulong offs, ulong nbytes, int size);
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2007-07-05 16:01:31 +00:00
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#define CONFIG_PHY_ADDR 1 /* FIXME */
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2003-07-16 21:53:01 +00:00
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2003-07-26 08:08:08 +00:00
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typedef struct {
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2007-10-09 16:17:41 +00:00
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uint8 data[1500]; /* actual data */
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int length; /* actual length */
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int used; /* buffer in use or not */
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uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
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2003-07-26 08:08:08 +00:00
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} NBUF;
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2007-10-09 16:17:41 +00:00
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/*
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* MII-interface related functions
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*/
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2007-10-09 16:13:06 +00:00
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static int fec5xxx_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
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uint8_t regAddr, uint16_t * retVal)
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{
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2007-10-09 16:59:18 +00:00
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struct eth_device *edev = mdev->edev;
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
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2007-10-09 16:13:06 +00:00
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uint32 reg; /* convenient holder for the PHY register */
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uint32 phy; /* convenient holder for the PHY */
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2007-11-05 11:26:29 +00:00
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uint64_t start;
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2007-10-09 16:13:06 +00:00
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/*
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* reading from any PHY's register is done by properly
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* programming the FEC's MII data register.
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*/
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2007-11-05 17:19:31 +00:00
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writel(FEC_IEVENT_MII, &fec->eth->ievent);
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2007-10-09 16:13:06 +00:00
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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2007-11-05 17:19:31 +00:00
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg, &fec->eth->mii_data);
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2007-10-09 16:13:06 +00:00
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/*
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* wait for the related interrupt
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*/
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2007-11-05 11:26:29 +00:00
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start = get_time_ns();
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2007-11-05 17:19:31 +00:00
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while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
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2007-11-05 11:26:29 +00:00
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if (is_timeout(start, MSECOND)) {
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printf("Read MDIO failed...\n");
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return -1;
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}
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2007-10-09 16:13:06 +00:00
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}
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/*
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* clear mii interrupt bit
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*/
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2007-11-05 17:19:31 +00:00
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writel(FEC_IEVENT_MII, &fec->eth->ievent);
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2007-10-09 16:13:06 +00:00
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/*
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* it's now safe to read the PHY's register
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*/
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2007-11-05 17:19:31 +00:00
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*retVal = readl(&fec->eth->mii_data);
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2007-10-09 16:13:06 +00:00
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return 0;
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}
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static int fec5xxx_miiphy_write(struct miiphy_device *mdev, uint8_t phyAddr,
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uint8_t regAddr, uint16_t data)
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{
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2007-10-09 16:59:18 +00:00
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struct eth_device *edev = mdev->edev;
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
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2007-10-09 16:13:06 +00:00
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uint32 reg; /* convenient holder for the PHY register */
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uint32 phy; /* convenient holder for the PHY */
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2007-11-05 11:26:29 +00:00
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uint64_t start;
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2007-10-09 16:13:06 +00:00
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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2007-11-05 17:19:31 +00:00
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writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
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2007-10-09 16:13:06 +00:00
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/*
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* wait for the MII interrupt
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*/
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2007-11-05 11:26:29 +00:00
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start = get_time_ns();
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2007-11-05 17:19:31 +00:00
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while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
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2007-11-05 11:26:29 +00:00
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if (is_timeout(start, MSECOND)) {
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printf("Write MDIO failed...\n");
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return -1;
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}
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2007-10-09 16:13:06 +00:00
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}
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/*
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* clear MII interrupt bit
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*/
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2007-11-05 17:19:31 +00:00
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writel(FEC_IEVENT_MII, &fec->eth->ievent);
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2007-10-09 16:13:06 +00:00
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return 0;
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}
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2005-10-28 20:30:33 +00:00
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2007-11-05 11:26:29 +00:00
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#ifdef CONFIG_MPC5200
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static int mpc5xxx_fec_rx_task_enable(mpc5xxx_fec_priv *fec)
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{
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SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
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return 0;
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}
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static int mpc5xxx_fec_rx_task_disable(mpc5xxx_fec_priv *fec)
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{
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SDMA_TASK_DISABLE(FEC_RECV_TASK_NO);
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return 0;
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}
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static int mpc5xxx_fec_tx_task_enable(mpc5xxx_fec_priv *fec)
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{
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SDMA_TASK_ENABLE(FEC_XMIT_TASK_NO);
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return 0;
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}
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static int mpc5xxx_fec_tx_task_disable(mpc5xxx_fec_priv *fec)
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{
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SDMA_TASK_DISABLE(FEC_XMIT_TASK_NO);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_IMX27
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static int mpc5xxx_fec_rx_task_enable(mpc5xxx_fec_priv *fec)
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{
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2007-11-05 17:19:31 +00:00
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writel(1 << 24, &fec->eth->r_des_active);
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2007-11-05 11:26:29 +00:00
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return 0;
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}
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static int mpc5xxx_fec_rx_task_disable(mpc5xxx_fec_priv *fec)
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{
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return 0;
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}
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static int mpc5xxx_fec_tx_task_enable(mpc5xxx_fec_priv *fec)
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{
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2007-11-05 17:19:31 +00:00
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writel(1 << 24, &fec->eth->x_des_active);
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2007-11-05 11:26:29 +00:00
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return 0;
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}
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static int mpc5xxx_fec_tx_task_disable(mpc5xxx_fec_priv *fec)
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{
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return 0;
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}
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#endif
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2007-11-05 17:19:31 +00:00
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/**
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* allocate and link buffers for the receive task
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* @param[in] fec all we know about the device yet
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* @param[in] count receive buffer count to be allocated
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* @param[in] size size of each receive buffer
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* @return 0 on success
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*
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* We need some alignment for the buffers. Thy must be
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* aligned to a specific boundary each. See RDB_ALIGNMENT
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*/
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static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec, int count, int size)
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2003-07-16 21:53:01 +00:00
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{
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int ix;
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2003-07-26 08:08:08 +00:00
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static int once = 0;
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2007-11-05 17:19:31 +00:00
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uint32 p;
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2003-07-16 21:53:01 +00:00
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2007-11-05 11:26:29 +00:00
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printf("%s\n", __FUNCTION__);
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2007-11-05 17:19:31 +00:00
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size += RDB_ALIGNMENT; /* enlarge the size for alignment */
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for (ix = 0; ix < count; ix++) {
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2003-07-26 08:08:08 +00:00
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if (!once) {
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2007-11-05 17:19:31 +00:00
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p = (uint32)xzalloc(size);
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p += RDB_ALIGNMENT - 1;
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p &= ~(RDB_ALIGNMENT - 1);
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writel(p, &fec->rbdBase[ix].dataPointer);
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2003-07-16 21:53:01 +00:00
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}
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2007-11-05 17:19:31 +00:00
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writew(FEC_RBD_EMPTY, &fec->rbdBase[ix].status);
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writew(0, &fec->rbdBase[ix].dataLength);
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2003-07-16 21:53:01 +00:00
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}
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2003-07-26 08:08:08 +00:00
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once ++;
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2003-07-16 21:53:01 +00:00
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/*
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* have the last RBD to close the ring
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*/
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2007-11-05 17:19:31 +00:00
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writew(FEC_RBD_WRAP | readl(&fec->rbdBase[ix - 1].status), &fec->rbdBase[ix - 1].status);
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2003-07-16 21:53:01 +00:00
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fec->rbdIndex = 0;
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return 0;
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}
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2007-11-05 17:19:31 +00:00
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/**
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* initialize buffers for the transmit task
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* @param[in] fec all we know about the device yet
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*
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* Nothing special here to do. We ony using one bufffer
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* for all transmit operations.
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*/
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2003-07-16 21:53:01 +00:00
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static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
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{
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2007-11-05 17:19:31 +00:00
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writew(FEC_TBD_WRAP, &fec->tbdBase[0].status);
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2003-07-16 21:53:01 +00:00
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}
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2007-11-05 17:19:31 +00:00
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/**
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* Mark the given read buffer descriptor as free
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* @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
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* @param[in] pRbd buffer descriptor to mark free again
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*/
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static void mpc5xxx_fec_rbd_clean(int last, FEC_RBD *pRbd)
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2003-07-16 21:53:01 +00:00
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{
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/*
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* Reset buffer descriptor as empty
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*/
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2007-11-05 17:19:31 +00:00
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if (last)
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writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
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2003-07-16 21:53:01 +00:00
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else
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2007-11-05 17:19:31 +00:00
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writew(FEC_RBD_EMPTY, &pRbd->status);
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2003-07-16 21:53:01 +00:00
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/*
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2007-11-05 17:19:31 +00:00
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* no data in it
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2003-07-16 21:53:01 +00:00
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*/
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2007-11-05 17:19:31 +00:00
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writew(0, &pRbd->dataLength);
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2003-07-16 21:53:01 +00:00
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}
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2007-11-05 11:26:29 +00:00
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static int mpc5xxx_fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
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2003-07-16 21:53:01 +00:00
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{
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2007-07-05 16:02:00 +00:00
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/* no eeprom */
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return -1;
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2007-07-05 16:01:31 +00:00
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}
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2007-11-05 11:26:29 +00:00
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static int mpc5xxx_fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
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2007-07-05 16:01:31 +00:00
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{
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
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2007-11-05 17:19:31 +00:00
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//#define WTF_IS_THIS
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#ifdef WTF_IS_THIS
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uint32 crc = 0xffffffff; /* initial value */
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2003-07-16 21:53:01 +00:00
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uint8 currByte; /* byte for which to compute the CRC */
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int byte; /* loop - counter */
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int bit; /* loop - counter */
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2007-11-05 17:19:31 +00:00
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2003-07-16 21:53:01 +00:00
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/*
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* The algorithm used is the following:
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* we loop on each of the six bytes of the provided address,
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* and we compute the CRC by left-shifting the previous
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* value by one position, so that each bit in the current
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* byte of the address may contribute the calculation. If
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* the latter and the MSB in the CRC are different, then
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* the CRC value so computed is also ex-ored with the
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* "polynomium generator". The current byte of the address
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* is also shifted right by one bit at each iteration.
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* This is because the CRC generatore in hardware is implemented
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* as a shift-register with as many ex-ores as the radixes
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|
|
* in the polynomium. This suggests that we represent the
|
|
|
|
* polynomiumm itself as a 32-bit constant.
|
|
|
|
*/
|
|
|
|
for (byte = 0; byte < 6; byte++) {
|
|
|
|
currByte = mac[byte];
|
|
|
|
for (bit = 0; bit < 8; bit++) {
|
|
|
|
if ((currByte & 0x01) ^ (crc & 0x01)) {
|
|
|
|
crc >>= 1;
|
|
|
|
crc = crc ^ 0xedb88320;
|
|
|
|
} else {
|
|
|
|
crc >>= 1;
|
|
|
|
}
|
|
|
|
currByte >>= 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
crc = crc >> 26;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set individual hash table register
|
|
|
|
*/
|
|
|
|
if (crc >= 32) {
|
|
|
|
fec->eth->iaddr1 = (1 << (crc - 32));
|
|
|
|
fec->eth->iaddr2 = 0;
|
|
|
|
} else {
|
|
|
|
fec->eth->iaddr1 = 0;
|
|
|
|
fec->eth->iaddr2 = (1 << crc);
|
|
|
|
}
|
2007-11-05 11:26:29 +00:00
|
|
|
#else
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0, &fec->eth->iaddr1);
|
|
|
|
writel(0, &fec->eth->iaddr2);
|
|
|
|
writel(0, &fec->eth->gaddr1);
|
|
|
|
writel(0, &fec->eth->gaddr2);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Set physical address
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], &fec->eth->paddr1);
|
|
|
|
writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
|
2007-07-05 16:01:31 +00:00
|
|
|
|
|
|
|
return 0;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
static int mpc5xxx_fec_init(struct eth_device *dev)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-16 21:53:01 +00:00
|
|
|
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("mpc5xxx_fec_init... Begin\n");
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-07-05 16:02:00 +00:00
|
|
|
/*
|
2003-07-16 21:53:01 +00:00
|
|
|
* Initialize RxBD/TxBD rings
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
mpc5xxx_fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
|
2003-07-16 21:53:01 +00:00
|
|
|
mpc5xxx_fec_tbd_init(fec);
|
|
|
|
|
2007-07-05 16:02:00 +00:00
|
|
|
/*
|
2003-07-16 21:53:01 +00:00
|
|
|
* Clear FEC-Lite interrupt event register(IEVENT)
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0xffffffff, &fec->eth->ievent);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set interrupt mask register
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000000, &fec->eth->imask);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set FEC-Lite receive control register(R_CNTRL):
|
|
|
|
*/
|
|
|
|
if (fec->xcv_type == SEVENWIRE) {
|
|
|
|
/*
|
|
|
|
* Frame length=1518; 7-wire mode
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x05ee0020, &fec->eth->r_cntrl); /* FIXME 0x05ee0000 */
|
2003-07-16 21:53:01 +00:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Frame length=1518; MII mode;
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x05ee0024, &fec->eth->r_cntrl); /* FIXME 0x05ee0004 */
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
2003-09-05 23:19:14 +00:00
|
|
|
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
|
2003-07-16 21:53:01 +00:00
|
|
|
* and do not drop the Preamble.
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(((get_ipb_clock() >> 20) / 5) << 1, &fec->eth->mii_speed); /* No MII for 7-wire mode */
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(((imx_get_ahbclk() >> 20) / 5) << 1, &fec->eth->mii_speed); /* No MII for 7-wire mode */
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set Opcode/Pause Duration Register
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Set Rx FIFO alarm and granularity value
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x0c000000 | (readl(&fec->eth->rfifo_cntrl) & ~0x0f000000)), &fec->eth->rfifo_cntrl);
|
|
|
|
writel(0x0000030c, &fec->eth->rfifo_alarm);
|
2007-10-09 16:34:26 +00:00
|
|
|
|
2007-11-05 17:19:31 +00:00
|
|
|
if (readl(&fec->eth->rfifo_status) & 0x00700000 ) {
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("mpc5xxx_fec_init() RFIFO error\n");
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set Tx FIFO granularity value
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x0c000000 | (readl(&fec->eth->tfifo_cntrl)& ~0x0f000000), &fec->eth->tfifo_cntrl);
|
2007-10-09 16:34:26 +00:00
|
|
|
|
2007-11-05 17:19:31 +00:00
|
|
|
debug("tfifo_status: 0x%08x\n", readl(&fec->eth->tfifo_status));
|
|
|
|
debug("tfifo_alarm: 0x%08x\n", readl(&fec->eth->tfifo_alarm));
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set transmit fifo watermark register(X_WMRK), default = 64
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000080, &fec->eth->tfifo_alarm);
|
2007-11-05 11:26:29 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Turn ON cheater FSM: ????
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x03000000, &fec->eth->xmit_fsm);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
|
|
|
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x2, &fec->eth->x_wmrk);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set multicast address filter
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000000, &fec->eth->gaddr1);
|
|
|
|
writel(0x00000000, &fec->eth->gaddr2);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Set priority of different initiators
|
|
|
|
*/
|
|
|
|
sdma->IPR0 = 7; /* always */
|
|
|
|
sdma->IPR3 = 6; /* Eth RX */
|
|
|
|
sdma->IPR4 = 5; /* Eth Tx */
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(2048-16, &fec->eth->emrbr);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Clear SmartDMA task interrupt pending bits
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
// SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize SmartDMA parameters stored in SRAM
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2005-02-24 22:44:16 +00:00
|
|
|
*(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
|
|
|
|
*(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
|
|
|
|
*(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
|
|
|
|
*(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("mpc5xxx_fec_init... Done \n");
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
if (fec->xcv_type != SEVENWIRE)
|
|
|
|
miiphy_restart_aneg(&fec->miiphy);
|
2004-05-12 22:18:31 +00:00
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
return 0;
|
2004-05-12 22:18:31 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
static int mpc5xxx_fec_open(struct eth_device *edev)
|
2004-05-12 22:18:31 +00:00
|
|
|
{
|
2007-07-05 16:02:06 +00:00
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
|
2004-05-12 22:18:31 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
printf("%s\n", __FUNCTION__);
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
#if defined(CONFIG_MPC5200)
|
|
|
|
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
|
|
|
|
/*
|
|
|
|
* Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
|
|
|
|
* work w/ the current receive task.
|
|
|
|
*/
|
|
|
|
sdma->PtdCntrl |= 0x00000001;
|
2004-05-12 22:18:31 +00:00
|
|
|
#endif
|
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
#if 0
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000000, &fec->eth->x_cntrl); /* half-duplex, heartbeat disabled */
|
2007-11-05 11:26:29 +00:00
|
|
|
#else
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(1 << 2, &fec->eth->x_cntrl); /* full-duplex, heartbeat disabled */
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
fec->rbdIndex = 0;
|
2007-07-05 16:02:06 +00:00
|
|
|
|
2004-05-12 22:18:31 +00:00
|
|
|
/*
|
2007-07-05 16:02:06 +00:00
|
|
|
* Enable FEC-Lite controller
|
2004-05-12 22:18:31 +00:00
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
#if defined(CONFIG_MPC5200)
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000006 | readl(&fec->eth->ecntrl), &fec->eth->ecntrl);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_IMX27)
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000002 | readl(&fec->eth->ecntrl), &fec->eth->ecntrl);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2004-05-12 22:18:31 +00:00
|
|
|
/*
|
2007-07-05 16:02:06 +00:00
|
|
|
* Enable SmartDMA receive task
|
2004-05-12 22:18:31 +00:00
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
mpc5xxx_fec_rx_task_enable(fec);
|
2004-05-12 22:18:31 +00:00
|
|
|
|
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
2007-07-05 16:02:06 +00:00
|
|
|
miiphy_wait_aneg(&fec->miiphy);
|
|
|
|
miiphy_print_status(&fec->miiphy);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
return 0;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mpc5xxx_fec_halt(struct eth_device *dev)
|
|
|
|
{
|
2003-07-26 08:08:08 +00:00
|
|
|
#if defined(CONFIG_MPC5200)
|
2003-07-16 21:53:01 +00:00
|
|
|
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
|
2003-07-26 08:08:08 +00:00
|
|
|
#endif
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2003-07-16 21:53:01 +00:00
|
|
|
int counter = 0xffff;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* issue graceful stop command to the FEC transmitter if necessary
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000001 | readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* wait for graceful stop to register
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
|
|
|
|
;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable SmartDMA tasks
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
mpc5xxx_fec_tx_task_disable(fec);
|
|
|
|
mpc5xxx_fec_rx_task_disable(fec);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Turn on COMM bus prefetch in the MGT5200 BestComm after we're
|
|
|
|
* done. It doesn't work w/ the current receive task.
|
|
|
|
*/
|
|
|
|
sdma->PtdCntrl &= ~0x00000001;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable the Ethernet Controller
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0, &fec->eth->ecntrl);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Clear FIFO status registers
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00700000 & readl(&fec->eth->rfifo_status), &fec->eth->rfifo_status);
|
|
|
|
writel(0x00700000 & readl(&fec->eth->tfifo_status), &fec->eth->tfifo_status);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 17:19:31 +00:00
|
|
|
// writel(0x01000000, &fec->eth->reset_cntrl);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("Ethernet task stopped\n");
|
|
|
|
}
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
#ifdef DEBUG_FIFO
|
2005-10-28 20:30:33 +00:00
|
|
|
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
2007-11-05 17:19:31 +00:00
|
|
|
if ((readl(&fec->eth->tfifo_lrf_ptr) != readl(&fec->eth->tfifo_lwf_ptr))
|
|
|
|
|| (readl(&fec->eth->tfifo_rdptr) != readl(&fec->eth->tfifo_wrptr))) {
|
|
|
|
|
|
|
|
printf("ecntrl: 0x%08x\n", readl(&fec->eth->ecntrl));
|
|
|
|
printf("ievent: 0x%08x\n", readl(&fec->eth->ievent));
|
|
|
|
printf("x_status: 0x%08x\n", readl(&fec->eth->x_status));
|
|
|
|
printf("tfifo: status 0x%08x\n", readl(&fec->eth->tfifo_status));
|
|
|
|
|
|
|
|
printf(" control 0x%08x\n", readl(&fec->eth->tfifo_cntrl));
|
|
|
|
printf(" lrfp 0x%08x\n", readl(&fec->eth->tfifo_lrf_ptr));
|
|
|
|
printf(" lwfp 0x%08x\n", readl(&fec->eth->tfifo_lwf_ptr));
|
|
|
|
printf(" alarm 0x%08x\n", readl(&fec->eth->tfifo_alarm));
|
|
|
|
printf(" readptr 0x%08x\n", readl(&fec->eth->tfifo_rdptr));
|
|
|
|
printf(" writptr 0x%08x\n", readl(&fec->eth->tfifo_wrptr));
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-10-28 20:30:33 +00:00
|
|
|
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
2007-11-05 17:19:31 +00:00
|
|
|
if ((readl(&fec->eth->rfifo_lrf_ptr) != readl(&fec->eth->rfifo_lwf_ptr))
|
|
|
|
|| (readl(&fec->eth->rfifo_rdptr) != readl(&fec->eth->rfifo_wrptr))) {
|
|
|
|
|
|
|
|
printf("ecntrl: 0x%08x\n", readl(&fec->eth->ecntrl));
|
|
|
|
printf("ievent: 0x%08x\n", readl(&fec->eth->ievent));
|
|
|
|
printf("x_status: 0x%08x\n", readl(&fec->eth->x_status));
|
|
|
|
printf("rfifo: status 0x%08x\n", readl(&fec->eth->rfifo_status));
|
|
|
|
|
|
|
|
printf(" control 0x%08x\n", readl(&fec->eth->rfifo_cntrl));
|
|
|
|
printf(" lrfp 0x%08x\n", readl(&fec->eth->rfifo_lrf_ptr));
|
|
|
|
printf(" lwfp 0x%08x\n", readl(&fec->eth->rfifo_lwf_ptr));
|
|
|
|
printf(" alarm 0x%08x\n", readl(&fec->eth->rfifo_alarm));
|
|
|
|
printf(" readptr 0x%08x\n", readl(&fec->eth->rfifo_rdptr));
|
|
|
|
printf(" writptr 0x%08x\n", readl(&fec->eth->rfifo_wrptr));
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
}
|
2007-10-09 16:34:26 +00:00
|
|
|
#else
|
|
|
|
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
static void __maybe_unused rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
2007-10-09 16:34:26 +00:00
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif /* DEBUG_FIFO */
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-07-05 16:02:00 +00:00
|
|
|
static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
|
2003-07-16 21:53:01 +00:00
|
|
|
int data_length)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* This routine transmits one frame. This routine only accepts
|
|
|
|
* 6-byte Ethernet addresses.
|
|
|
|
*/
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2005-02-24 22:44:16 +00:00
|
|
|
volatile FEC_TBD *pTbd;
|
2007-07-05 16:02:00 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
// printf("%s length=%d data=0x%08x\n", __FUNCTION__, data_length, eth_data);
|
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
#ifdef DEBUG_FIFO
|
|
|
|
debug_fifo("tbd status: 0x%04x\n", fec->tbdBase[0].status);
|
2005-10-28 20:30:33 +00:00
|
|
|
tfifo_print(dev->name, fec);
|
2003-07-16 21:53:01 +00:00
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* Check for valid length of data.
|
|
|
|
*/
|
|
|
|
if ((data_length > 1500) || (data_length <= 0)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the first TxBD to send the mac header
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
pTbd = &fec->tbdBase[0];
|
2003-07-16 21:53:01 +00:00
|
|
|
pTbd->dataLength = data_length;
|
|
|
|
pTbd->dataPointer = (uint32)eth_data;
|
2007-11-05 11:26:29 +00:00
|
|
|
pTbd->status = FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY | FEC_TBD_WRAP;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable SmartDMA transmit task
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
mpc5xxx_fec_tx_task_enable(fec);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* wait until frame is sent .
|
|
|
|
*/
|
|
|
|
while (pTbd->status & FEC_TBD_READY) {
|
2007-10-09 16:34:26 +00:00
|
|
|
/* FIXME: Timeout */
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mpc5xxx_fec_recv(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* This command pulls one frame from the card
|
|
|
|
*/
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2007-11-05 17:19:31 +00:00
|
|
|
FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
|
2003-07-16 21:53:01 +00:00
|
|
|
unsigned long ievent;
|
2003-07-26 08:08:08 +00:00
|
|
|
int frame_length, len = 0;
|
|
|
|
NBUF *frame;
|
2005-10-13 14:45:02 +00:00
|
|
|
uchar buff[FEC_MAX_PKT_SIZE];
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
// printf("%s\n", __FUNCTION__);
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Check if any critical events have happened
|
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
ievent = readl(&fec->eth->ievent);
|
|
|
|
writel(ievent, &fec->eth->ievent);
|
2007-10-09 16:09:17 +00:00
|
|
|
if (ievent & (FEC_IEVENT_BABT | FEC_IEVENT_XFIFO_ERROR |
|
|
|
|
FEC_IEVENT_RFIFO_ERROR)) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/* BABT, Rx/Tx FIFO errors */
|
|
|
|
mpc5xxx_fec_halt(dev);
|
2007-07-05 16:01:31 +00:00
|
|
|
mpc5xxx_fec_init(dev);
|
2007-11-05 11:26:29 +00:00
|
|
|
printf("some error: 0x%08x\n", ievent);
|
2003-07-16 21:53:01 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2007-10-09 16:09:17 +00:00
|
|
|
if (ievent & FEC_IEVENT_HBERR) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/* Heartbeat error */
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(0x00000001 | readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
2007-10-09 16:09:17 +00:00
|
|
|
if (ievent & FEC_IEVENT_GRA) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/* Graceful stop complete */
|
2007-11-05 17:19:31 +00:00
|
|
|
if (readl(&fec->eth->x_cntrl) & 0x00000001) {
|
2003-07-16 21:53:01 +00:00
|
|
|
mpc5xxx_fec_halt(dev);
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(~0x00000001 & readl(&fec->eth->x_cntrl), &fec->eth->x_cntrl);
|
2007-07-05 16:01:31 +00:00
|
|
|
mpc5xxx_fec_init(dev);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-07-26 08:08:08 +00:00
|
|
|
if (!(pRbd->status & FEC_RBD_EMPTY)) {
|
|
|
|
if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
|
|
|
|
((pRbd->dataLength - 4) > 14)) {
|
2007-11-05 11:26:29 +00:00
|
|
|
printf("read from %d (0x%08x) rbd=0x%08x", fec->rbdIndex, pRbd->dataPointer, pRbd);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2003-07-26 08:08:08 +00:00
|
|
|
/*
|
|
|
|
* Get buffer address and size
|
|
|
|
*/
|
|
|
|
frame = (NBUF *)pRbd->dataPointer;
|
|
|
|
frame_length = pRbd->dataLength - 4;
|
2007-11-05 11:26:29 +00:00
|
|
|
printf(" len=%d\n", frame_length);
|
|
|
|
#define DEBUG_RX_HEADER
|
2007-10-09 16:34:26 +00:00
|
|
|
#ifdef DEBUG_RX_HEADER
|
2003-07-26 08:08:08 +00:00
|
|
|
{
|
2007-11-05 11:26:29 +00:00
|
|
|
printf("recv data hdr:\n");
|
|
|
|
memory_display(frame->data, 0, frame_length, 1);
|
2003-07-26 08:08:08 +00:00
|
|
|
}
|
2007-07-05 16:02:00 +00:00
|
|
|
#endif
|
2003-07-26 08:08:08 +00:00
|
|
|
/*
|
|
|
|
* Fill the buffer and pass it to upper layers
|
|
|
|
*/
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-26 08:08:08 +00:00
|
|
|
memcpy(buff, frame->head, 14);
|
|
|
|
memcpy(buff + 14, frame->data, frame_length);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
|
|
|
memcpy(buff, frame->data, frame_length);
|
|
|
|
#endif
|
2003-07-26 08:08:08 +00:00
|
|
|
NetReceive(buff, frame_length);
|
|
|
|
len = frame_length;
|
2007-11-05 11:26:29 +00:00
|
|
|
} else {
|
|
|
|
if (pRbd->status & FEC_RBD_ERR) {
|
|
|
|
printf("error frame: 0x%08x 0x%08x\n", pRbd, pRbd->status);
|
|
|
|
}
|
2003-07-26 08:08:08 +00:00
|
|
|
}
|
|
|
|
/*
|
2007-11-05 17:19:31 +00:00
|
|
|
* free the current buffer, restart the engine and move
|
|
|
|
* forward to the next buffer
|
2003-07-26 08:08:08 +00:00
|
|
|
*/
|
2007-11-05 17:19:31 +00:00
|
|
|
mpc5xxx_fec_rbd_clean(fec->rbdIndex == (FEC_RBD_NUM - 1) ? 1 : 0, pRbd);
|
|
|
|
mpc5xxx_fec_rx_task_enable(fec);
|
|
|
|
fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
|
|
|
|
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
2007-07-05 16:02:00 +00:00
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
// SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
|
2003-07-26 08:08:08 +00:00
|
|
|
return len;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
int mpc5xxx_fec_probe(struct device_d *dev)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
2007-07-05 16:01:31 +00:00
|
|
|
struct mpc5xxx_fec_platform_data *pdata = (struct mpc5xxx_fec_platform_data *)dev->platform_data;
|
|
|
|
struct eth_device *edev;
|
2003-07-16 21:53:01 +00:00
|
|
|
mpc5xxx_fec_priv *fec;
|
|
|
|
|
2007-11-05 11:26:29 +00:00
|
|
|
printf("%s\n", __FUNCTION__);
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
|
|
|
PCCR0 |= PCCR0_FEC_EN;
|
|
|
|
#endif
|
2007-07-05 16:01:31 +00:00
|
|
|
edev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
2007-07-05 16:01:42 +00:00
|
|
|
dev->type_data = edev;
|
2003-07-16 21:53:01 +00:00
|
|
|
fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
|
2007-07-05 16:01:31 +00:00
|
|
|
edev->priv = fec;
|
|
|
|
edev->dev = dev;
|
2007-07-05 16:02:06 +00:00
|
|
|
edev->open = mpc5xxx_fec_open,
|
|
|
|
edev->init = mpc5xxx_fec_init,
|
2007-07-05 16:01:31 +00:00
|
|
|
edev->send = mpc5xxx_fec_send,
|
|
|
|
edev->recv = mpc5xxx_fec_recv,
|
|
|
|
edev->halt = mpc5xxx_fec_halt,
|
2007-11-05 11:26:29 +00:00
|
|
|
edev->get_ethaddr = mpc5xxx_fec_get_hwaddr,
|
|
|
|
edev->set_ethaddr = mpc5xxx_fec_set_hwaddr,
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-10-09 16:59:18 +00:00
|
|
|
fec->eth = (ethernet_regs *)dev->map_base;
|
2007-11-05 11:26:29 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_MPC5200
|
2003-07-16 21:53:01 +00:00
|
|
|
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
|
|
|
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_IMX27
|
|
|
|
/* Reset chip. FIXME: shouldn't it be done for mpc5200 aswell? */
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(1, &fec->eth->ecntrl);
|
|
|
|
while(readl(&fec->eth->ecntrl) & 1) {
|
2007-11-05 11:26:29 +00:00
|
|
|
udelay(10);
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
unsigned long base;
|
|
|
|
|
2007-11-05 17:19:31 +00:00
|
|
|
base = ((unsigned long)xzalloc(sizeof(FEC_TBD) + 32) + 31) & ~0x1f;
|
2007-11-05 11:26:29 +00:00
|
|
|
fec->tbdBase = (FEC_TBD *)base;
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(fec->tbdBase, &fec->eth->etdsr);
|
|
|
|
base = ((unsigned long)xzalloc(FEC_RBD_NUM * sizeof(FEC_RBD) + 32) + 31) & ~0x1f;
|
2007-11-05 11:26:29 +00:00
|
|
|
fec->rbdBase = (FEC_RBD *)base;
|
2007-11-05 17:19:31 +00:00
|
|
|
writel(fec->rbdBase, &fec->eth->erdsr);
|
2007-11-05 11:26:29 +00:00
|
|
|
}
|
|
|
|
#endif
|
2007-07-05 16:01:28 +00:00
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
fec->xcv_type = pdata->xcv_type;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2003-07-26 08:08:08 +00:00
|
|
|
sprintf(dev->name, "FEC ETHERNET");
|
2007-11-05 11:26:29 +00:00
|
|
|
#ifdef CONFIG_MPC5200
|
2007-07-12 07:22:25 +00:00
|
|
|
loadtask(0, 2);
|
2007-11-05 11:26:29 +00:00
|
|
|
#endif
|
2007-07-05 16:02:06 +00:00
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
|
|
|
fec->miiphy.read = fec5xxx_miiphy_read;
|
|
|
|
fec->miiphy.write = fec5xxx_miiphy_write;
|
|
|
|
fec->miiphy.address = CONFIG_PHY_ADDR;
|
|
|
|
fec->miiphy.flags = pdata->xcv_type == MII10 ? MIIPHY_FORCE_10 : 0;
|
2007-11-05 11:26:29 +00:00
|
|
|
fec->miiphy.edev = edev;
|
2003-09-02 22:48:03 +00:00
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
miiphy_register(&fec->miiphy);
|
|
|
|
}
|
2005-10-28 20:30:33 +00:00
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
eth_register(edev);
|
2007-07-05 16:01:31 +00:00
|
|
|
return 0;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
static struct driver_d mpc5xxx_driver = {
|
|
|
|
.name = "fec_mpc5xxx",
|
|
|
|
.probe = mpc5xxx_fec_probe,
|
|
|
|
.type = DEVICE_TYPE_ETHER,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mpc5xxx_fec_register(void)
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{
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register_driver(&mpc5xxx_driver);
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return 0;
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}
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device_initcall(mpc5xxx_fec_register);
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2007-11-05 17:19:31 +00:00
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/**
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* @file
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* @brief Network driver for FreeScale's FEC implementation.
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* This type of hardware can be found on MPC52xx and i.MX27 CPUs
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*/
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