2009-12-15 10:32:02 +00:00
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/*
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Raghavendra KH <r-khandenahally@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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2008-08-20 08:08:47 +00:00
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/**
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* @file
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* @brief Beagle Specific Board Initialization routines
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2009-12-15 10:32:02 +00:00
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*/
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/**
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* @page ti_beagle Texas Instruments Beagle Board
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2008-08-20 08:08:47 +00:00
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*
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2010-07-22 03:00:13 +00:00
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* FileName: arch/arm/boards/omap/board-beagle.c
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2008-08-20 08:08:47 +00:00
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*
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* Beagle Board from Texas Instruments as described here:
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* http://www.beagleboard.org
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*
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* This board is based on OMAP3530.
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* More on OMAP3530 (including documentation can be found here):
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* http://focus.ti.com/docs/prod/folders/print/omap3530.html
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*
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* This file provides initialization in two stages:
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* @li boot time initialization - do basics required to get SDRAM working.
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* This is run from SRAM - so no case constructs and global vars can be used.
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* @li run time initialization - this is for the rest of the initializations
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* such as flash, uart etc.
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*
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* Boot time initialization includes:
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* @li SDRAM initialization.
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* @li Pin Muxing relevant for Beagle.
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*
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* Run time initialization includes
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* @li serial @ref serial_ns16550.c driver device definition
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*
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2010-07-22 03:00:13 +00:00
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* Originally from arch/arm/boards/omap/board-sdp343x.c
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2008-08-20 08:08:47 +00:00
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*/
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#include <common.h>
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#include <console.h>
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#include <init.h>
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#include <driver.h>
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#include <asm/io.h>
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#include <ns16550.h>
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2009-12-09 08:35:51 +00:00
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#include <asm/armlinux.h>
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2009-10-22 12:21:25 +00:00
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#include <mach/silicon.h>
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#include <mach/sdrc.h>
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#include <mach/sys_info.h>
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#include <mach/syslib.h>
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#include <mach/control.h>
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#include <mach/omap3-mux.h>
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#include <mach/gpmc.h>
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2010-08-03 17:50:46 +00:00
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#include <mach/gpmc_nand.h>
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2008-08-20 08:08:47 +00:00
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#include "board.h"
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/******************** Board Boot Time *******************/
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/**
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* @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
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*
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* @return void
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*/
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static void sdrc_init(void)
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{
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2010-06-23 12:17:18 +00:00
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/* SDRAM software reset */
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/* No idle ack and RESET enable */
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writel(0x1A, SDRC_REG(SYSCONFIG));
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sdelay(100);
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/* No idle ack and RESET disable */
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writel(0x18, SDRC_REG(SYSCONFIG));
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/* SDRC Sharing register */
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/* 32-bit SDRAM on data lane [31:0] - CS0 */
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/* pin tri-stated = 1 */
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writel(0x00000100, SDRC_REG(SHARING));
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/* ----- SDRC Registers Configuration --------- */
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/* SDRC_MCFG0 register */
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writel(0x02584099, SDRC_REG(MCFG_0));
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/* SDRC_RFR_CTRL0 register */
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writel(0x54601, SDRC_REG(RFR_CTRL_0));
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/* SDRC_ACTIM_CTRLA0 register */
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writel(0xA29DB4C6, SDRC_REG(ACTIM_CTRLA_0));
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/* SDRC_ACTIM_CTRLB0 register */
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writel(0x12214, SDRC_REG(ACTIM_CTRLB_0));
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/* Disble Power Down of CKE due to 1 CKE on combo part */
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writel(0x00000081, SDRC_REG(POWER));
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/* SDRC_MANUAL command register */
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/* NOP command */
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writel(0x00000000, SDRC_REG(MANUAL_0));
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/* Precharge command */
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writel(0x00000001, SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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writel(0x00000002, SDRC_REG(MANUAL_0));
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/* Auto-refresh command */
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writel(0x00000002, SDRC_REG(MANUAL_0));
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/* SDRC MR0 register Burst length=4 */
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writel(0x00000032, SDRC_REG(MR_0));
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/* SDRC DLLA control register */
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writel(0x0000000A, SDRC_REG(DLLA_CTRL));
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return;
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2008-08-20 08:08:47 +00:00
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}
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/**
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* @brief Do the pin muxing required for Board operation.
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* We enable ONLY the pins we require to set. OMAP provides pins which do not
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* have alternate modes. Such pins done need to be set.
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*
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* See @ref MUX_VAL for description of the muxing mode.
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*
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* @return void
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*/
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static void mux_config(void)
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{
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2010-06-23 12:17:18 +00:00
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/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
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/* GPMC */
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MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
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/* D0-D7 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
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/* GPMC_NADV_ALE default mux mode is mode0 */
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/* GPMC_NOE default mux mode is mode0 */
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/* GPMC_NWE default mux mode is mode0 */
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/* GPMC_NBE0_CLE default mux mode is mode0 */
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MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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/* GPMC_WAIT0 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
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2008-08-20 08:08:47 +00:00
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2010-06-23 12:17:18 +00:00
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/* SERIAL INTERFACE */
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MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
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/* I2C1_SCL default mux mode is mode0 */
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/* I2C1_SDA default mux mode is mode0 */
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2010-08-04 09:59:10 +00:00
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/* USB EHCI (port 2) */
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MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
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MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
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2008-08-20 08:08:47 +00:00
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}
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/**
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* @brief The basic entry point for board initialization.
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*
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* This is called as part of machine init (after arch init).
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* This is again called with stack in SRAM, so not too many
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* constructs possible here.
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*
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* @return void
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*/
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void board_init(void)
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{
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2010-06-23 12:17:18 +00:00
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int in_sdram = running_in_sdram();
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mux_config();
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/* Dont reconfigure SDRAM while running in SDRAM! */
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if (!in_sdram)
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sdrc_init();
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2008-08-20 08:08:47 +00:00
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}
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/******************** Board Run Time *******************/
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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static struct NS16550_plat serial_plat = {
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2010-06-23 12:17:18 +00:00
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.clock = 48000000, /* 48MHz (APLL96/2) */
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.f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR,
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.reg_read = omap_uart_read,
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.reg_write = omap_uart_write,
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2008-08-20 08:08:47 +00:00
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};
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static struct device_d beagle_serial_device = {
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2010-06-23 12:17:18 +00:00
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.name = "serial_ns16550",
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.map_base = OMAP_UART3_BASE,
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.size = 1024,
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.platform_data = (void *)&serial_plat,
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2008-08-20 08:08:47 +00:00
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};
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/**
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* @brief UART serial port initialization - remember to enable COM clocks in
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* arch
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*
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* @return result of device registration
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*/
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static int beagle_console_init(void)
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{
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2010-06-23 12:17:18 +00:00
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/* Register the serial port */
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return register_device(&beagle_serial_device);
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2008-08-20 08:08:47 +00:00
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}
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console_initcall(beagle_console_init);
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#endif /* CONFIG_DRIVER_SERIAL_NS16550 */
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2009-06-10 22:12:02 +00:00
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static struct memory_platform_data sram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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2008-08-20 08:08:47 +00:00
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2009-06-10 22:12:02 +00:00
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static struct device_d sdram_dev = {
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.name = "mem",
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.map_base = 0x80000000,
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.size = 128 * 1024 * 1024,
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2009-12-09 08:35:51 +00:00
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.platform_data = &sram_pdata,
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2008-08-20 08:08:47 +00:00
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};
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static int beagle_devices_init(void)
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{
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2010-06-23 12:17:18 +00:00
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int ret;
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ret = register_device(&sdram_dev);
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if (ret)
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goto failed;
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2010-07-05 10:32:14 +00:00
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2008-09-11 15:26:16 +00:00
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#ifdef CONFIG_GPMC
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/* WP is made high and WAIT1 active Low */
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gpmc_generic_init(0x10);
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#endif
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2010-06-23 12:17:18 +00:00
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gpmc_generic_nand_devices_init(0, 16, 1);
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armlinux_add_dram(&sdram_dev);
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2008-08-20 08:08:47 +00:00
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failed:
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2010-06-23 12:17:18 +00:00
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return ret;
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2008-08-20 08:08:47 +00:00
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}
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device_initcall(beagle_devices_init);
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