2003-07-16 21:53:01 +00:00
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/*
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2005-04-13 23:15:10 +00:00
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* (C) Copyright 2003-2005
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2003-07-16 21:53:01 +00:00
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* This file is based on mpc4200fec.c,
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* (C) Copyright Motorola, Inc., 2000
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*/
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#include <common.h>
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2009-10-22 12:21:30 +00:00
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#include <mach/mpc5xxx.h>
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2003-07-16 21:53:01 +00:00
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#include <malloc.h>
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#include <net.h>
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2007-07-05 16:01:31 +00:00
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#include <init.h>
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2010-08-26 16:33:28 +00:00
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#include <miidev.h>
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2007-07-05 16:01:31 +00:00
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#include <driver.h>
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2009-10-22 12:21:30 +00:00
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#include <mach/sdma.h>
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#include <mach/fec.h>
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#include <mach/clocks.h>
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2010-08-26 16:33:28 +00:00
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#include <miidev.h>
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2007-07-05 16:01:31 +00:00
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#include "fec_mpc5200.h"
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2007-11-05 17:19:31 +00:00
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2007-07-05 16:01:31 +00:00
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#define CONFIG_PHY_ADDR 1 /* FIXME */
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2003-07-16 21:53:01 +00:00
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2003-07-26 08:08:08 +00:00
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typedef struct {
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2008-04-04 09:59:52 +00:00
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uint8_t data[1500]; /* actual data */
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2007-10-09 16:17:41 +00:00
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int length; /* actual length */
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int used; /* buffer in use or not */
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2008-04-04 09:59:52 +00:00
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uint8_t head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
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2003-07-26 08:08:08 +00:00
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} NBUF;
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2007-10-09 16:17:41 +00:00
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/*
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* MII-interface related functions
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*/
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2010-08-26 16:33:28 +00:00
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static int fec5xxx_miidev_read(struct mii_device *mdev, int phyAddr, int regAddr)
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2007-10-09 16:13:06 +00:00
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{
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2007-10-09 16:59:18 +00:00
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struct eth_device *edev = mdev->edev;
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
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2008-04-04 09:59:52 +00:00
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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2008-02-20 16:48:31 +00:00
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int timeout = 0xffff;
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2007-10-09 16:13:06 +00:00
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/*
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* reading from any PHY's register is done by properly
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* programming the FEC's MII data register.
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*/
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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2008-02-20 16:48:31 +00:00
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fec->eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
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2007-10-09 16:13:06 +00:00
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/*
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* wait for the related interrupt
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*/
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2008-02-20 16:48:31 +00:00
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while ((timeout--) && (!(fec->eth->ievent & FEC_IEVENT_MII))) ;
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if (timeout == 0) {
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debug("Read MDIO failed...\n");
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return -1;
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2007-10-09 16:13:06 +00:00
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}
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/*
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* clear mii interrupt bit
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*/
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2008-02-20 16:48:31 +00:00
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fec->eth->ievent = FEC_IEVENT_MII;
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2007-10-09 16:13:06 +00:00
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/*
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* it's now safe to read the PHY's register
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*/
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2010-08-26 16:33:28 +00:00
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return fec->eth->mii_data;
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2007-10-09 16:13:06 +00:00
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}
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2010-08-26 16:33:28 +00:00
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static int fec5xxx_miidev_write(struct mii_device *mdev, int phyAddr,
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int regAddr, int data)
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2007-10-09 16:13:06 +00:00
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{
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2007-10-09 16:59:18 +00:00
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struct eth_device *edev = mdev->edev;
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
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2008-04-04 09:59:52 +00:00
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uint32_t reg; /* convenient holder for the PHY register */
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uint32_t phy; /* convenient holder for the PHY */
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2008-02-20 16:48:31 +00:00
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int timeout = 0xffff;
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2007-10-09 16:13:06 +00:00
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reg = regAddr << FEC_MII_DATA_RA_SHIFT;
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phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
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2008-02-20 16:48:31 +00:00
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fec->eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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FEC_MII_DATA_TA | phy | reg | data);
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2007-10-09 16:13:06 +00:00
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/*
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* wait for the MII interrupt
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*/
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2008-02-20 16:48:31 +00:00
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while ((timeout--) && (!(fec->eth->ievent & FEC_IEVENT_MII))) ;
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if (timeout == 0) {
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debug("Write MDIO failed...\n");
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return -1;
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2007-10-09 16:13:06 +00:00
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}
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/*
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* clear MII interrupt bit
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*/
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2008-02-20 16:48:31 +00:00
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fec->eth->ievent = FEC_IEVENT_MII;
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2007-11-05 11:26:29 +00:00
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return 0;
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}
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2008-02-20 16:48:31 +00:00
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static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
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2003-07-16 21:53:01 +00:00
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{
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int ix;
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2008-02-20 16:48:31 +00:00
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char *data;
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2003-07-26 08:08:08 +00:00
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static int once = 0;
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2007-11-05 17:19:31 +00:00
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2008-02-20 16:48:31 +00:00
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for (ix = 0; ix < FEC_RBD_NUM; ix++) {
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2003-07-26 08:08:08 +00:00
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if (!once) {
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2008-02-20 16:48:31 +00:00
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data = (char *)malloc(FEC_MAX_PKT_SIZE);
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if (data == NULL) {
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printf ("RBD INIT FAILED\n");
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return -1;
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}
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2008-04-04 09:59:52 +00:00
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fec->rbdBase[ix].dataPointer = (uint32_t)data;
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2003-07-16 21:53:01 +00:00
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}
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2008-02-20 16:48:31 +00:00
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fec->rbdBase[ix].status = FEC_RBD_EMPTY;
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fec->rbdBase[ix].dataLength = 0;
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2003-07-16 21:53:01 +00:00
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}
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2003-07-26 08:08:08 +00:00
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once ++;
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2003-07-16 21:53:01 +00:00
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/*
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* have the last RBD to close the ring
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*/
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2008-02-20 16:48:31 +00:00
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fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
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2003-07-16 21:53:01 +00:00
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fec->rbdIndex = 0;
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return 0;
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}
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static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
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{
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2008-02-20 16:48:31 +00:00
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int ix;
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for (ix = 0; ix < FEC_TBD_NUM; ix++) {
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fec->tbdBase[ix].status = 0;
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}
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/*
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* Have the last TBD to close the ring
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*/
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fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
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/*
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* Initialize some indices
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*/
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fec->tbdIndex = 0;
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fec->usedTbdIndex = 0;
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fec->cleanTbdNum = FEC_TBD_NUM;
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2003-07-16 21:53:01 +00:00
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}
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2008-02-20 16:48:31 +00:00
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static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
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2003-07-16 21:53:01 +00:00
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{
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/*
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* Reset buffer descriptor as empty
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*/
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2008-02-20 16:48:31 +00:00
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if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
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pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
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2003-07-16 21:53:01 +00:00
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else
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2008-02-20 16:48:31 +00:00
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pRbd->status = FEC_RBD_EMPTY;
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pRbd->dataLength = 0;
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/*
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* Now, we have an empty RxBD, restart the SmartDMA receive task
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*/
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SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
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/*
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* Increment BD count
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*/
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fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
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}
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static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
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{
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volatile FEC_TBD *pUsedTbd;
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2003-07-16 21:53:01 +00:00
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/*
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2008-02-20 16:48:31 +00:00
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* process all the consumed TBDs
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2003-07-16 21:53:01 +00:00
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*/
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2008-02-20 16:48:31 +00:00
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while (fec->cleanTbdNum < FEC_TBD_NUM) {
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pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
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if (pUsedTbd->status & FEC_TBD_READY) {
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debug("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
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return;
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}
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/*
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* clean this buffer descriptor
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*/
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if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
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pUsedTbd->status = FEC_TBD_WRAP;
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else
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pUsedTbd->status = 0;
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/*
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* update some indeces for a correct handling of the TBD ring
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*/
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fec->cleanTbdNum++;
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fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
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}
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2003-07-16 21:53:01 +00:00
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}
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2008-02-20 16:48:31 +00:00
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static int mpc5xxx_fec_get_ethaddr(struct eth_device *dev, unsigned char *mac)
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2003-07-16 21:53:01 +00:00
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{
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2007-07-05 16:02:00 +00:00
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/* no eeprom */
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return -1;
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2007-07-05 16:01:31 +00:00
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}
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2008-02-20 16:48:31 +00:00
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static int mpc5xxx_fec_set_ethaddr(struct eth_device *dev, unsigned char *mac)
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2007-07-05 16:01:31 +00:00
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{
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
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2008-04-04 09:59:52 +00:00
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uint8_t currByte; /* byte for which to compute the CRC */
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2003-07-16 21:53:01 +00:00
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int byte; /* loop - counter */
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int bit; /* loop - counter */
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2008-04-04 09:59:52 +00:00
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uint32_t crc = 0xffffffff; /* initial value */
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2007-11-05 17:19:31 +00:00
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2003-07-16 21:53:01 +00:00
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/*
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* The algorithm used is the following:
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* we loop on each of the six bytes of the provided address,
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* and we compute the CRC by left-shifting the previous
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* value by one position, so that each bit in the current
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* byte of the address may contribute the calculation. If
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* the latter and the MSB in the CRC are different, then
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* the CRC value so computed is also ex-ored with the
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* "polynomium generator". The current byte of the address
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* is also shifted right by one bit at each iteration.
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* This is because the CRC generatore in hardware is implemented
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* as a shift-register with as many ex-ores as the radixes
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* in the polynomium. This suggests that we represent the
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* polynomiumm itself as a 32-bit constant.
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*/
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for (byte = 0; byte < 6; byte++) {
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currByte = mac[byte];
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for (bit = 0; bit < 8; bit++) {
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if ((currByte & 0x01) ^ (crc & 0x01)) {
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crc >>= 1;
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crc = crc ^ 0xedb88320;
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} else {
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crc >>= 1;
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}
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currByte >>= 1;
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}
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}
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crc = crc >> 26;
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/*
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* Set individual hash table register
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*/
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if (crc >= 32) {
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fec->eth->iaddr1 = (1 << (crc - 32));
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fec->eth->iaddr2 = 0;
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} else {
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fec->eth->iaddr1 = 0;
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fec->eth->iaddr2 = (1 << crc);
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}
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2008-02-20 16:48:31 +00:00
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2003-07-16 21:53:01 +00:00
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/*
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* Set physical address
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*/
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2008-02-20 16:48:31 +00:00
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fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
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fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
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2007-07-05 16:01:31 +00:00
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return 0;
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2003-07-16 21:53:01 +00:00
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}
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2007-07-05 16:01:31 +00:00
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static int mpc5xxx_fec_init(struct eth_device *dev)
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2003-07-16 21:53:01 +00:00
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{
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mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
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struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
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2008-02-20 16:48:31 +00:00
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2007-10-09 16:34:26 +00:00
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debug("mpc5xxx_fec_init... Begin\n");
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2003-07-16 21:53:01 +00:00
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2007-07-05 16:02:00 +00:00
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/*
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2003-07-16 21:53:01 +00:00
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* Initialize RxBD/TxBD rings
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*/
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2008-02-20 16:48:31 +00:00
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mpc5xxx_fec_rbd_init(fec);
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2003-07-16 21:53:01 +00:00
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mpc5xxx_fec_tbd_init(fec);
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2007-07-05 16:02:00 +00:00
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/*
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2003-07-16 21:53:01 +00:00
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* Clear FEC-Lite interrupt event register(IEVENT)
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*/
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2008-02-20 16:48:31 +00:00
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fec->eth->ievent = 0xffffffff;
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2003-07-16 21:53:01 +00:00
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/*
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* Set interrupt mask register
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*/
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2008-02-20 16:48:31 +00:00
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fec->eth->imask = 0x00000000;
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2003-07-16 21:53:01 +00:00
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/*
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* Set FEC-Lite receive control register(R_CNTRL):
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*/
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|
|
if (fec->xcv_type == SEVENWIRE) {
|
|
|
|
/*
|
|
|
|
* Frame length=1518; 7-wire mode
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
|
2003-07-16 21:53:01 +00:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* Frame length=1518; MII mode;
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
|
|
|
|
}
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
2003-09-05 23:19:14 +00:00
|
|
|
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
|
2003-07-16 21:53:01 +00:00
|
|
|
* and do not drop the Preamble.
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->mii_speed = (((get_ipb_clock() >> 20) / 5) << 1); /* No MII for 7-wire mode */
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set Opcode/Pause Duration Register
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->op_pause = 0x00010020; /*FIXME 0xffff0020; */
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set Rx FIFO alarm and granularity value
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->rfifo_cntrl = 0x0c000000
|
|
|
|
| (fec->eth->rfifo_cntrl & ~0x0f000000);
|
|
|
|
fec->eth->rfifo_alarm = 0x0000030c;
|
2007-10-09 16:34:26 +00:00
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
if (fec->eth->rfifo_status & 0x00700000 ) {
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("mpc5xxx_fec_init() RFIFO error\n");
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set Tx FIFO granularity value
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->tfifo_cntrl = 0x0c000000
|
|
|
|
| (fec->eth->tfifo_cntrl & ~0x0f000000);
|
2007-10-09 16:34:26 +00:00
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
debug("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
|
|
|
|
debug("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set transmit fifo watermark register(X_WMRK), default = 64
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->tfifo_alarm = 0x00000080;
|
|
|
|
fec->eth->x_wmrk = 0x2;
|
2007-11-05 11:26:29 +00:00
|
|
|
|
|
|
|
/*
|
2008-02-20 16:48:31 +00:00
|
|
|
* Set multicast address filter
|
2007-11-05 11:26:29 +00:00
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->gaddr1 = 0x00000000;
|
|
|
|
fec->eth->gaddr2 = 0x00000000;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
2008-02-20 16:48:31 +00:00
|
|
|
* Turn ON cheater FSM: ????
|
2003-07-16 21:53:01 +00:00
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->xmit_fsm = 0x03000000;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Set priority of different initiators
|
|
|
|
*/
|
|
|
|
sdma->IPR0 = 7; /* always */
|
|
|
|
sdma->IPR3 = 6; /* Eth RX */
|
|
|
|
sdma->IPR4 = 5; /* Eth Tx */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear SmartDMA task interrupt pending bits
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Initialize SmartDMA parameters stored in SRAM
|
|
|
|
*/
|
2005-02-24 22:44:16 +00:00
|
|
|
*(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
|
|
|
|
*(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
|
|
|
|
*(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
|
|
|
|
*(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
|
2008-02-20 16:48:31 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("mpc5xxx_fec_init... Done \n");
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
if (fec->xcv_type != SEVENWIRE)
|
2010-08-26 16:33:28 +00:00
|
|
|
miidev_restart_aneg(&fec->miidev);
|
2004-05-12 22:18:31 +00:00
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
return 0;
|
2004-05-12 22:18:31 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
static int mpc5xxx_fec_open(struct eth_device *edev)
|
2004-05-12 22:18:31 +00:00
|
|
|
{
|
2007-07-05 16:02:06 +00:00
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)edev->priv;
|
2004-05-12 22:18:31 +00:00
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
#if defined(CONFIG_MPC5200)
|
|
|
|
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
|
|
|
|
/*
|
|
|
|
* Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
|
|
|
|
* work w/ the current receive task.
|
|
|
|
*/
|
|
|
|
sdma->PtdCntrl |= 0x00000001;
|
2004-05-12 22:18:31 +00:00
|
|
|
#endif
|
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
|
2007-07-05 16:02:06 +00:00
|
|
|
|
2004-05-12 22:18:31 +00:00
|
|
|
/*
|
2007-07-05 16:02:06 +00:00
|
|
|
* Enable FEC-Lite controller
|
2004-05-12 22:18:31 +00:00
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->ecntrl |= 0x00000006;
|
|
|
|
|
2004-05-12 22:18:31 +00:00
|
|
|
/*
|
2007-07-05 16:02:06 +00:00
|
|
|
* Enable SmartDMA receive task
|
2004-05-12 22:18:31 +00:00
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
|
2004-05-12 22:18:31 +00:00
|
|
|
|
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
2010-08-26 16:33:28 +00:00
|
|
|
miidev_wait_aneg(&fec->miidev);
|
|
|
|
miidev_print_status(&fec->miidev);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
return 0;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mpc5xxx_fec_halt(struct eth_device *dev)
|
|
|
|
{
|
2003-07-26 08:08:08 +00:00
|
|
|
#if defined(CONFIG_MPC5200)
|
2003-07-16 21:53:01 +00:00
|
|
|
struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
|
2003-07-26 08:08:08 +00:00
|
|
|
#endif
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2003-07-16 21:53:01 +00:00
|
|
|
int counter = 0xffff;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* issue graceful stop command to the FEC transmitter if necessary
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->x_cntrl |= 0x00000001;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* wait for graceful stop to register
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
while ((counter--) && (!(fec->eth->ievent & FEC_IEVENT_GRA))) ;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable SmartDMA tasks
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
|
|
|
|
SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
#if defined(CONFIG_MPC5200)
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Turn on COMM bus prefetch in the MGT5200 BestComm after we're
|
|
|
|
* done. It doesn't work w/ the current receive task.
|
|
|
|
*/
|
|
|
|
sdma->PtdCntrl &= ~0x00000001;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable the Ethernet Controller
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->ecntrl &= 0xfffffffd;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Clear FIFO status registers
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->rfifo_status &= 0x00700000;
|
|
|
|
fec->eth->tfifo_status &= 0x00700000;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
// fec->eth->reset_cntrl = 0x01000000;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
debug("Ethernet task stopped\n");
|
|
|
|
}
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
#ifdef DEBUG_FIFO
|
2005-10-28 20:30:33 +00:00
|
|
|
static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
2008-02-20 16:48:31 +00:00
|
|
|
if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
|
|
|
|
|| (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
|
|
|
|
|
|
|
|
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
|
|
|
|
printf("ievent: 0x%08x\n", fec->eth->ievent);
|
|
|
|
printf("x_status: 0x%08x\n", fec->eth->x_status);
|
|
|
|
printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
|
|
|
|
|
|
|
|
printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
|
|
|
|
printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
|
|
|
|
printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
|
|
|
|
printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
|
|
|
|
printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
|
|
|
|
printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-10-28 20:30:33 +00:00
|
|
|
static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
2008-02-20 16:48:31 +00:00
|
|
|
if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
|
|
|
|
|| (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
|
|
|
|
|
|
|
|
printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
|
|
|
|
printf("ievent: 0x%08x\n", fec->eth->ievent);
|
|
|
|
printf("x_status: 0x%08x\n", fec->eth->x_status);
|
|
|
|
printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
|
|
|
|
|
|
|
|
printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
|
|
|
|
printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
|
|
|
|
printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
|
|
|
|
printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
|
|
|
|
printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
|
|
|
|
printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
}
|
2007-10-09 16:34:26 +00:00
|
|
|
#endif /* DEBUG_FIFO */
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-07-05 16:02:00 +00:00
|
|
|
static int mpc5xxx_fec_send(struct eth_device *dev, void *eth_data,
|
2003-07-16 21:53:01 +00:00
|
|
|
int data_length)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* This routine transmits one frame. This routine only accepts
|
|
|
|
* 6-byte Ethernet addresses.
|
|
|
|
*/
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2005-02-24 22:44:16 +00:00
|
|
|
volatile FEC_TBD *pTbd;
|
2007-07-05 16:02:00 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
#ifdef DEBUG_FIFO
|
|
|
|
debug_fifo("tbd status: 0x%04x\n", fec->tbdBase[0].status);
|
2005-10-28 20:30:33 +00:00
|
|
|
tfifo_print(dev->name, fec);
|
2003-07-16 21:53:01 +00:00
|
|
|
#endif
|
2008-02-20 16:48:31 +00:00
|
|
|
/*
|
|
|
|
* Clear Tx BD ring at first
|
|
|
|
*/
|
|
|
|
mpc5xxx_fec_tbd_scrub(fec);
|
|
|
|
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Check for valid length of data.
|
|
|
|
*/
|
|
|
|
if ((data_length > 1500) || (data_length <= 0)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
/*
|
|
|
|
* Check the number of vacant TxBDs.
|
|
|
|
*/
|
|
|
|
if (fec->cleanTbdNum < 1) {
|
|
|
|
printf("No available TxBDs ...\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2003-07-16 21:53:01 +00:00
|
|
|
/*
|
|
|
|
* Get the first TxBD to send the mac header
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
pTbd = &fec->tbdBase[fec->tbdIndex];
|
2003-07-16 21:53:01 +00:00
|
|
|
pTbd->dataLength = data_length;
|
2008-04-04 09:59:52 +00:00
|
|
|
pTbd->dataPointer = (uint32_t)eth_data;
|
2008-02-20 16:48:31 +00:00
|
|
|
pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
|
|
|
|
fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Kick the MII i/f
|
|
|
|
*/
|
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
2008-04-04 09:59:52 +00:00
|
|
|
uint16_t phyStatus;
|
2010-09-20 07:20:59 +00:00
|
|
|
phyStatus = fec5xxx_miidev_read(&fec->miidev, 0, 0x1);
|
2008-02-20 16:48:31 +00:00
|
|
|
}
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable SmartDMA transmit task
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
|
|
|
|
// tfifo_print(dev->name, fec);
|
|
|
|
|
|
|
|
SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
|
|
|
|
|
|
|
|
// tfifo_print(dev->name, fec);
|
|
|
|
|
|
|
|
fec->cleanTbdNum -= 1;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* wait until frame is sent .
|
|
|
|
*/
|
|
|
|
while (pTbd->status & FEC_TBD_READY) {
|
2007-10-09 16:34:26 +00:00
|
|
|
/* FIXME: Timeout */
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int mpc5xxx_fec_recv(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
/*
|
|
|
|
* This command pulls one frame from the card
|
|
|
|
*/
|
|
|
|
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
|
2008-02-20 16:48:31 +00:00
|
|
|
volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
|
2003-07-16 21:53:01 +00:00
|
|
|
unsigned long ievent;
|
2003-07-26 08:08:08 +00:00
|
|
|
int frame_length, len = 0;
|
|
|
|
NBUF *frame;
|
2005-10-13 14:45:02 +00:00
|
|
|
uchar buff[FEC_MAX_PKT_SIZE];
|
2003-07-16 21:53:01 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Check if any critical events have happened
|
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
ievent = fec->eth->ievent;
|
|
|
|
fec->eth->ievent = ievent;
|
2007-10-09 16:09:17 +00:00
|
|
|
if (ievent & (FEC_IEVENT_BABT | FEC_IEVENT_XFIFO_ERROR |
|
|
|
|
FEC_IEVENT_RFIFO_ERROR)) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/* BABT, Rx/Tx FIFO errors */
|
|
|
|
mpc5xxx_fec_halt(dev);
|
2007-07-05 16:01:31 +00:00
|
|
|
mpc5xxx_fec_init(dev);
|
2003-07-16 21:53:01 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2007-10-09 16:09:17 +00:00
|
|
|
if (ievent & FEC_IEVENT_HBERR) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/* Heartbeat error */
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->x_cntrl |= 0x00000001;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
2007-10-09 16:09:17 +00:00
|
|
|
if (ievent & FEC_IEVENT_GRA) {
|
2003-07-16 21:53:01 +00:00
|
|
|
/* Graceful stop complete */
|
2008-02-20 16:48:31 +00:00
|
|
|
if (fec->eth->x_cntrl & 0x00000001) {
|
2003-07-16 21:53:01 +00:00
|
|
|
mpc5xxx_fec_halt(dev);
|
2008-02-20 16:48:31 +00:00
|
|
|
fec->eth->x_cntrl &= ~0x00000001;
|
2007-07-05 16:01:31 +00:00
|
|
|
mpc5xxx_fec_init(dev);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2003-07-26 08:08:08 +00:00
|
|
|
if (!(pRbd->status & FEC_RBD_EMPTY)) {
|
|
|
|
if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
|
|
|
|
((pRbd->dataLength - 4) > 14)) {
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2003-07-26 08:08:08 +00:00
|
|
|
/*
|
|
|
|
* Get buffer address and size
|
|
|
|
*/
|
|
|
|
frame = (NBUF *)pRbd->dataPointer;
|
|
|
|
frame_length = pRbd->dataLength - 4;
|
2008-02-20 16:48:31 +00:00
|
|
|
|
2007-10-09 16:34:26 +00:00
|
|
|
#ifdef DEBUG_RX_HEADER
|
2003-07-26 08:08:08 +00:00
|
|
|
{
|
2008-02-20 16:48:31 +00:00
|
|
|
int i;
|
|
|
|
printf("recv data hdr:");
|
|
|
|
for (i = 0; i < 14; i++)
|
|
|
|
printf("%02x ", *(frame->head + i));
|
|
|
|
printf("\n");
|
2003-07-26 08:08:08 +00:00
|
|
|
}
|
2007-07-05 16:02:00 +00:00
|
|
|
#endif
|
2003-07-26 08:08:08 +00:00
|
|
|
/*
|
|
|
|
* Fill the buffer and pass it to upper layers
|
|
|
|
*/
|
|
|
|
memcpy(buff, frame->head, 14);
|
|
|
|
memcpy(buff + 14, frame->data, frame_length);
|
2010-06-02 13:59:16 +00:00
|
|
|
net_receive(buff, frame_length);
|
2003-07-26 08:08:08 +00:00
|
|
|
len = frame_length;
|
|
|
|
}
|
|
|
|
/*
|
2008-02-20 16:48:31 +00:00
|
|
|
* Reset buffer descriptor as empty
|
2003-07-26 08:08:08 +00:00
|
|
|
*/
|
2008-02-20 16:48:31 +00:00
|
|
|
mpc5xxx_fec_rbd_clean(fec, pRbd);
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
2007-07-05 16:02:00 +00:00
|
|
|
|
2008-02-20 16:48:31 +00:00
|
|
|
SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
|
2003-07-26 08:08:08 +00:00
|
|
|
return len;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
int mpc5xxx_fec_probe(struct device_d *dev)
|
2003-07-16 21:53:01 +00:00
|
|
|
{
|
2007-07-05 16:01:31 +00:00
|
|
|
struct mpc5xxx_fec_platform_data *pdata = (struct mpc5xxx_fec_platform_data *)dev->platform_data;
|
|
|
|
struct eth_device *edev;
|
2003-07-16 21:53:01 +00:00
|
|
|
mpc5xxx_fec_priv *fec;
|
|
|
|
|
2011-01-06 15:23:01 +00:00
|
|
|
edev = (struct eth_device *)xmalloc(sizeof(struct eth_device));
|
2007-07-05 16:01:42 +00:00
|
|
|
dev->type_data = edev;
|
2011-01-06 15:23:01 +00:00
|
|
|
fec = (mpc5xxx_fec_priv *)xmalloc(sizeof(*fec));
|
2007-07-05 16:01:31 +00:00
|
|
|
edev->priv = fec;
|
2007-07-05 16:02:06 +00:00
|
|
|
edev->open = mpc5xxx_fec_open,
|
|
|
|
edev->init = mpc5xxx_fec_init,
|
2007-07-05 16:01:31 +00:00
|
|
|
edev->send = mpc5xxx_fec_send,
|
|
|
|
edev->recv = mpc5xxx_fec_recv,
|
|
|
|
edev->halt = mpc5xxx_fec_halt,
|
2008-02-20 16:48:31 +00:00
|
|
|
edev->get_ethaddr = mpc5xxx_fec_get_ethaddr,
|
|
|
|
edev->set_ethaddr = mpc5xxx_fec_set_ethaddr,
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-10-09 16:59:18 +00:00
|
|
|
fec->eth = (ethernet_regs *)dev->map_base;
|
2003-07-16 21:53:01 +00:00
|
|
|
fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
|
|
|
|
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
|
2007-07-05 16:01:28 +00:00
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
fec->xcv_type = pdata->xcv_type;
|
2003-07-16 21:53:01 +00:00
|
|
|
|
2007-07-12 07:22:25 +00:00
|
|
|
loadtask(0, 2);
|
2008-02-20 16:48:31 +00:00
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
if (fec->xcv_type != SEVENWIRE) {
|
2010-08-26 16:33:28 +00:00
|
|
|
fec->miidev.read = fec5xxx_miidev_read;
|
|
|
|
fec->miidev.write = fec5xxx_miidev_write;
|
|
|
|
fec->miidev.address = CONFIG_PHY_ADDR;
|
|
|
|
fec->miidev.flags = pdata->xcv_type == MII10 ? MIIDEV_FORCE_10 : 0;
|
|
|
|
fec->miidev.edev = edev;
|
2003-09-02 22:48:03 +00:00
|
|
|
|
2010-08-26 16:33:28 +00:00
|
|
|
mii_register(&fec->miidev);
|
2007-07-05 16:02:06 +00:00
|
|
|
}
|
2005-10-28 20:30:33 +00:00
|
|
|
|
2007-07-05 16:02:06 +00:00
|
|
|
eth_register(edev);
|
2007-07-05 16:01:31 +00:00
|
|
|
return 0;
|
2003-07-16 21:53:01 +00:00
|
|
|
}
|
|
|
|
|
2007-07-05 16:01:31 +00:00
|
|
|
static struct driver_d mpc5xxx_driver = {
|
|
|
|
.name = "fec_mpc5xxx",
|
|
|
|
.probe = mpc5xxx_fec_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int mpc5xxx_fec_register(void)
|
|
|
|
{
|
|
|
|
register_driver(&mpc5xxx_driver);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
device_initcall(mpc5xxx_fec_register);
|
|
|
|
|