ARM mxs: add bcb command to create 'boot control block' for NAND boot
We write a proper FCB, but no DBBT since it is unresolved how to keep it in sync with Linux-based BBTs. Also, we imply searchcount = 4 and stride = 64 (which is the default) until we can verify via ocotp. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This commit is contained in:
parent
eb76c8e827
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0256d59a41
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@ -80,6 +80,14 @@ config MXS_OCOTP
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internal view). Don't use register offsets here, the SET, CLR and
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TGL registers are not mapped!
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config MXS_CMD_BCB
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depends on NAND_MXS
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tristate "Nand bcb command"
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help
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To be able to boot from NAND the i.MX23/28 need a Boot Control Block
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in flash. This option enabled the 'bcb' command which can be used to
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generate this block during runtime.
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endmenu
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menu "Board specific settings "
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@ -3,3 +3,4 @@ obj-$(CONFIG_DRIVER_VIDEO_STM) += imx_lcd_clk.o
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obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb.o
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obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o
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obj-$(CONFIG_MXS_OCOTP) += ocotp.o
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obj-$(CONFIG_MXS_CMD_BCB) += bcb.o
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@ -0,0 +1,399 @@
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/*
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* (C) Copyright 2011 Wolfram Sang, Pengutronix e.K.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Based on a similar function in Karo Electronics TX28-U-Boot (flash.c).
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* Probably written by Lothar Waßmann (like tx28.c).
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*/
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#include <common.h>
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#include <command.h>
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#include <environment.h>
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#include <malloc.h>
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#include <nand.h>
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#include <sizes.h>
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#include <errno.h>
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#include <io.h>
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#include <mach/imx-regs.h>
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#include <linux/err.h>
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#include <linux/mtd/nand.h>
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#define FCB_START_BLOCK 0
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#define NUM_FCB_BLOCKS 1
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#define MAX_FCB_BLOCKS 32768
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#define GPMI_TIMING0 0x00000070
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#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16)
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#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16
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#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8)
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#define GPMI_TIMING0_DATA_HOLD_OFFSET 8
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#define GPMI_TIMING0_DATA_SETUP_MASK 0xff
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#define GPMI_TIMING0_DATA_SETUP_OFFSET 0
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#define GPMI_TIMING1 0x00000080
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#define BCH_MODE 0x00000020
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#define BCH_FLASH0LAYOUT0 0x00000080
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#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24)
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#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
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#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
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#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
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#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12)
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#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
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#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
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#define BCH_FLASH0LAYOUT1 0x00000090
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
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#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12)
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#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
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#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
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struct mx28_nand_timing {
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u8 data_setup;
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u8 data_hold;
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u8 address_setup;
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u8 dsample_time;
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u8 nand_timing_state;
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u8 tREA;
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u8 tRLOH;
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u8 tRHOH;
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};
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struct mx28_fcb {
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u32 checksum;
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u32 fingerprint;
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u32 version;
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struct mx28_nand_timing timing;
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u32 page_data_size;
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u32 total_page_size;
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u32 sectors_per_block;
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u32 number_of_nands; /* not used by ROM code */
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u32 total_internal_die; /* not used by ROM code */
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u32 cell_type; /* not used by ROM code */
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u32 ecc_blockn_type;
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u32 ecc_block0_size;
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u32 ecc_blockn_size;
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u32 ecc_block0_type;
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u32 metadata_size;
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u32 ecc_blocks_per_page;
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u32 rsrvd[6]; /* not used by ROM code */
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u32 bch_mode;
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u32 boot_patch;
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u32 patch_sectors;
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u32 fw1_start_page;
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u32 fw2_start_page;
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u32 fw1_sectors;
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u32 fw2_sectors;
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u32 dbbt_search_area;
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u32 bb_mark_byte;
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u32 bb_mark_startbit;
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u32 bb_mark_phys_offset;
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};
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struct mx28_dbbt_header {
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u32 checksum;
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u32 fingerprint;
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u32 version;
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u32 number_bb;
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u32 number_pages;
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u8 spare[492];
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};
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struct mx28_dbbt {
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u32 nand_number;
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u32 number_bb;
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u32 bb_num[2040 / 4];
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};
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#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET)
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#define GETBIT(v,n) (((v) >> (n)) & 0x1)
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static u8 calculate_parity_13_8(u8 d)
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{
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u8 p = 0;
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p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2)) << 0;
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p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^ GETBIT(d, 1)) << 1;
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p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 2;
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p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0)) << 3;
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p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 4;
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return p;
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}
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static void encode_hamming_13_8(void *_src, void *_ecc, size_t size)
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{
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int i;
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u8 *src = _src;
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u8 *ecc = _ecc;
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for (i = 0; i < size; i++)
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ecc[i] = calculate_parity_13_8(src[i]);
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}
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static u32 calc_chksum(void *buf, size_t size)
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{
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u32 chksum = 0;
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u8 *bp = buf;
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size_t i;
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for (i = 0; i < size; i++)
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chksum += bp[i];
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return ~chksum;
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}
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/*
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Physical organisation of data in NAND flash:
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metadata
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payload chunk 0 (may be empty)
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ecc for metadata + payload chunk 0
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payload chunk 1
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ecc for payload chunk 1
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...
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payload chunk n
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ecc for payload chunk n
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*/
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static int calc_bb_offset(struct mtd_info *mtd, struct mx28_fcb *fcb)
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{
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int bb_mark_offset;
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int chunk_data_size = fcb->ecc_blockn_size * 8;
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int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13;
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int chunk_total_size = chunk_data_size + chunk_ecc_size;
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int bb_mark_chunk, bb_mark_chunk_offs;
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bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8;
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if (fcb->ecc_block0_size == 0)
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bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13;
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bb_mark_chunk = bb_mark_offset / chunk_total_size;
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bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size);
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if (bb_mark_chunk_offs > chunk_data_size) {
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printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n",
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bb_mark_chunk_offs);
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return -EINVAL;
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}
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bb_mark_offset -= bb_mark_chunk * chunk_ecc_size;
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return bb_mark_offset;
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}
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static struct mx28_fcb *create_fcb(struct mtd_info *mtd, void *buf, unsigned fw1_start_block,
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size_t fw_size, unsigned fw2_start_block)
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{
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u32 fl0, fl1, t0;
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int metadata_size;
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int bb_mark_bit_offs;
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struct mx28_fcb *fcb;
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int fcb_offs;
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void __iomem *bch_regs = (void *)MXS_BCH_BASE;
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void __iomem *gpmi_regs = (void *)MXS_GPMI_BASE;
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fl0 = readl(bch_regs + BCH_FLASH0LAYOUT0);
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fl1 = readl(bch_regs + BCH_FLASH0LAYOUT1);
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t0 = readl(gpmi_regs + GPMI_TIMING0);
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metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
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fcb = buf + ALIGN(metadata_size, 4);
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fcb_offs = (void *)fcb - buf;
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memset(buf, 0x00, fcb_offs);
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memset(fcb, 0x00, sizeof(*fcb));
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memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb));
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strncpy((char *)&fcb->fingerprint, "FCB ", 4);
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fcb->version = cpu_to_be32(1);
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fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP);
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fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD);
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fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP);
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fcb->page_data_size = mtd->writesize;
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fcb->total_page_size = mtd->writesize + mtd->oobsize;
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fcb->sectors_per_block = mtd->erasesize / mtd->writesize;
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fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0);
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fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE);
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fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN);
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fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE);
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fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE);
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fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS);
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fcb->bch_mode = readl(bch_regs + BCH_MODE);
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/*
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fcb->boot_patch = 0;
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fcb->patch_sectors = 0;
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*/
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fcb->fw1_start_page = fw1_start_block / mtd->writesize;
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fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize);
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if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) {
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fcb->fw2_start_page = fw2_start_block / mtd->writesize;
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fcb->fw2_sectors = fcb->fw1_sectors;
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}
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fcb->dbbt_search_area = 1;
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bb_mark_bit_offs = calc_bb_offset(mtd, fcb);
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if (bb_mark_bit_offs < 0)
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return ERR_PTR(bb_mark_bit_offs);
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fcb->bb_mark_byte = bb_mark_bit_offs / 8;
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fcb->bb_mark_startbit = bb_mark_bit_offs % 8;
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fcb->bb_mark_phys_offset = mtd->writesize;
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fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4);
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return fcb;
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}
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static int find_fcb(struct mtd_info *mtd, void *ref, int page)
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{
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int ret = 0;
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struct nand_chip *chip = mtd->priv;
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void *buf = malloc(mtd->erasesize);
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if (buf == NULL)
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return -ENOMEM;
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chip->select_chip(mtd, 0);
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chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
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ret = chip->ecc.read_page_raw(mtd, chip, buf);
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if (ret) {
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printf("Failed to read FCB from page %u: %d\n", page, ret);
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return ret;
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}
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chip->select_chip(mtd, -1);
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if (memcmp(buf, ref, mtd->writesize) == 0) {
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printf("%s: Found FCB in page %u (%08x)\n", __func__,
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page, page * mtd->writesize);
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ret = 1;
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}
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free(buf);
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return ret;
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}
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static int write_fcb(struct mtd_info *mtd, void *buf, int block)
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{
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int ret;
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struct nand_chip *chip = mtd->priv;
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int page = block / mtd->writesize;
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struct erase_info erase_opts = {
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.mtd = mtd,
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.addr = block,
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.len = mtd->erasesize,
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.callback = NULL,
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};
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ret = find_fcb(mtd, buf, page);
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if (ret > 0) {
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printf("FCB at block %08x is up to date\n", block);
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return 0;
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}
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ret = mtd->erase(mtd, &erase_opts);
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if (ret) {
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printf("Failed to erase FCB block %08x\n", block);
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return ret;
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}
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printf("Writing FCB to block %08x\n", block);
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chip->select_chip(mtd, 0);
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ret = chip->write_page(mtd, chip, buf, page, 0, 1);
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if (ret) {
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printf("Failed to write FCB to block %08x: %d\n", block, ret);
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}
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chip->select_chip(mtd, -1);
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return ret;
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}
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int update_bcb(int argc, char *argv[])
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{
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int ret;
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int block;
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void *buf;
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struct mx28_fcb *fcb;
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struct cdev *tmp_cdev, *bcb_cdev, *firmware_cdev;
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unsigned long fw2_offset = 0;
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struct mtd_info *mtd;
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unsigned fcb_written = 0;
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if (argc == 1)
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return COMMAND_ERROR_USAGE;
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tmp_cdev = cdev_by_name("nand0");
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if (!tmp_cdev || !tmp_cdev->mtd) {
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pr_err("%s: No NAND device!\n", __func__);
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return -ENODEV;
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}
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mtd = tmp_cdev->mtd;
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bcb_cdev = cdev_by_name("nand0.bcb");
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if (!bcb_cdev) {
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pr_err("%s: No FCB device!\n", __func__);
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return -ENODEV;
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}
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firmware_cdev = cdev_by_name(argv[1]);
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if (!firmware_cdev) {
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pr_err("%s: Bootstream-Image not found!\n", __func__);
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return -ENODEV;
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}
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if (argc > 2) {
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tmp_cdev = cdev_by_name(argv[2]);
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if (!tmp_cdev) {
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pr_err("%s: Redundant Bootstream-Image not found!\n", __func__);
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return -ENODEV;
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}
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fw2_offset = tmp_cdev->offset;
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}
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buf = malloc(mtd->erasesize);
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if (!buf)
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return -ENOMEM;
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fcb = create_fcb(mtd, buf, firmware_cdev->offset, firmware_cdev->size, fw2_offset);
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if (IS_ERR(fcb)) {
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printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb));
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return PTR_ERR(fcb);
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}
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encode_hamming_13_8(fcb, (void *)fcb + 512, 512);
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for (block = bcb_cdev->offset; block < bcb_cdev->offset + bcb_cdev->size / 2;
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block += mtd->erasesize) {
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if (nand_isbad_bbt(mtd, block, false))
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continue;
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ret = write_fcb(mtd, buf, block);
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if (ret) {
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printf("Failed to write FCB to block %u\n", block);
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return ret;
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}
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fcb_written++;
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}
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return fcb_written ? 0 : -ENOSPC;
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}
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BAREBOX_CMD_HELP_START(bcb)
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BAREBOX_CMD_HELP_USAGE("bcb <first_bootstream> [second_bootstream]\n")
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BAREBOX_CMD_HELP_SHORT("Write a BCB to NAND flash which an MX23/28 needs to boot.\n")
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BAREBOX_CMD_HELP_TEXT ("Example: bcb nand0.bootstream\n")
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BAREBOX_CMD_HELP_END
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BAREBOX_CMD_START(bcb)
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.cmd = update_bcb,
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.usage = "Writes a MX23/28 BCB data structure to flash",
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BAREBOX_CMD_HELP(cmd_bcb_help)
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BAREBOX_CMD_END
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