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Merge branch 'for-next/imx'

This commit is contained in:
Sascha Hauer 2017-01-11 19:00:03 +01:00
parent 005a81e173 f4d4b659e4
commit 0c3f4d1da2
29 changed files with 721 additions and 128 deletions
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32
arch/arm/boards/phytec-phycore-omap4460/lowlevel.c
View File

@ -30,6 +30,13 @@
#include <asm/barebox-arm-head.h>
#define TPS62361_VSEL0_GPIO 182
#define LPDDR2_2G 0x5
#define LPDDR2_4G 0x6
#define LPDDR2_DENSITY_MASK 0x3C
#define LPDDR2_DENSITY_SHIFT 2
#define EMIF_SDRAM_CONFIG 0x0008
#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050
#define EMIF_LPDDR2_MODE_REG_DATA 0x0040
void set_muxconf_regs(void);
@ -61,8 +68,23 @@ static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = {
.mr2 = 0x4
};
static const struct ddr_regs ddr_regs_mt42L128M64D2LL_25_400_mhz = {
.tim1 = 0x10EB0662,
.tim2 = 0x205715D2,
.tim3 = 0x00B1C53F,
.phy_ctrl_1 = 0x849FF409,
.ref_ctrl = 0x00000618,
.config_init = 0x80001AB2,
.config_final = 0x80001AB2,
.zq_config = 0x500B3214,
.mr1 = 0x83,
.mr2 = 0x4
};
static void noinline pcm049_init_lowlevel(void)
{
unsigned int density;
struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400;
struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000;
struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920;
@ -75,9 +97,17 @@ static void noinline pcm049_init_lowlevel(void)
set_muxconf_regs();
#ifdef CONFIG_1024MB_DDR2RAM
omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE +
EMIF_LPDDR2_MODE_REG_CONFIG);
density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) &
LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT;
if (density == LPDDR2_2G)
omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core);
else if (density == LPDDR2_4G)
omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core);
#else
omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core);
#endif
/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */

1
arch/arm/boards/phytec-som-imx6/Makefile
View File

@ -2,3 +2,4 @@ obj-y += board.o
lwl-y += lowlevel.o
bbenv-y += defaultenv-physom-imx6
bbenv-y += defaultenv-physom-imx6-phycore
bbenv-y += defaultenv-physom-imx6ul-phycore

60
arch/arm/boards/phytec-som-imx6/board.c
View File

@ -30,6 +30,9 @@
#include <of.h>
#include <mach/bbu.h>
#include <platform_data/eth-fec.h>
#include <mfd/imx6q-iomuxc-gpr.h>
#include <linux/clk.h>
#include <linux/micrel_phy.h>
#include <globalvar.h>
@ -86,6 +89,56 @@ static unsigned int get_module_rev(void)
return 16 - val;
}
int ksz8081_phy_fixup(struct phy_device *phydev)
{
phy_write(phydev, 0x1f, 0x8190);
phy_write(phydev, 0x16, 0x202);
return 0;
}
static int imx6ul_setup_fec(void)
{
void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
uint32_t val;
struct clk *clk;
phy_register_fixup_for_uid(PHY_ID_KSZ8081, MICREL_PHY_ID_MASK,
ksz8081_phy_fixup);
clk = clk_lookup("enet_ptp");
if (IS_ERR(clk))
goto err;
clk_enable(clk);
clk = clk_lookup("enet_ref");
if (IS_ERR(clk))
goto err;
clk_enable(clk);
clk = clk_lookup("enet_ref_125m");
if (IS_ERR(clk))
goto err;
clk_enable(clk);
val = readl(gprbase + IOMUXC_GPR1);
/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
val &= ~(1 << 13);
val |= (1 << 17);
/* Use 50M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], set gpr1[18]*/
val &= ~(1 << 14);
val |= (1 << 18);
writel(val, gprbase + IOMUXC_GPR1);
return 0;
err:
pr_err("Setting up DFEC\n");
return -EIO;
}
static int physom_imx6_devices_init(void)
{
int ret;
@ -121,6 +174,11 @@ static int physom_imx6_devices_init(void)
default_environment_path = "/chosen/environment-spinor";
default_envdev = "SPI NOR flash";
} else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
barebox_set_hostname("phyCORE-i.MX6UL");
default_environment_path = "/chosen/environment-nand";
default_envdev = "NAND flash";
imx6ul_setup_fec();
} else
return 0;
@ -171,6 +229,8 @@ static int physom_imx6_devices_init(void)
|| of_machine_is_compatible("phytec,imx6dl-pcm058-nand")
|| of_machine_is_compatible("phytec,imx6dl-pcm058-emmc")) {
defaultenv_append_directory(defaultenv_physom_imx6_phycore);
} else if (of_machine_is_compatible("phytec,imx6ul-pcl063")) {
defaultenv_append_directory(defaultenv_physom_imx6ul_phycore);
}
return 0;

8
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/boot/nand Normal file
View File

@ -0,0 +1,8 @@
#!/bin/sh
[ ! -e /dev/nand0.root.ubi ] && ubiattach /dev/nand0.root
global.bootm.image="/dev/nand0.root.ubi.kernel"
global.bootm.oftree="/dev/nand0.root.ubi.oftree"
global.linux.bootargs.dyn.root="root=ubi0:root ubi.mtd=root rootfstype=ubifs rw"

9
arch/arm/boards/phytec-som-imx6/defaultenv-physom-imx6ul-phycore/init/automount Normal file
View File

@ -0,0 +1,9 @@
#!/bin/sh
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp'
mkdir -p /mnt/mmc
automount -d /mnt/mmc 'mmc0.probe=1 && [ -e /dev/mmc0.0 ] && mount /dev/mmc0.0 /mnt/mmc'

9
arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg Normal file
View File

@ -0,0 +1,9 @@
#define SETUP_MDCFG0 \
wm 32 0x021B000C 0x676B52F3
#define SETUP_MDASP_MDCTL \
wm 32 0x021B0040 0x0000004F; \
wm 32 0x021B0000 0x84180000
#include "flash-header-phytec-pcl063.h"

70
arch/arm/boards/phytec-som-imx6/flash-header-phytec-pcl063.h Normal file
View File

@ -0,0 +1,70 @@
loadaddr 0x80000000
soc imx6
dcdofs 0x400
wm 32 0x020c4068 0xffffffff
wm 32 0x020c406c 0xffffffff
wm 32 0x020c4070 0xffffffff
wm 32 0x020c4074 0xffffffff
wm 32 0x020c4078 0xffffffff
wm 32 0x020c407c 0xffffffff
wm 32 0x020c4080 0xffffffff
wm 32 0x020E04B4 0x000C0000
wm 32 0x020E04AC 0x00000000
wm 32 0x020E027C 0x00000030
wm 32 0x020E0250 0x00000030
wm 32 0x020E024C 0x00000030
wm 32 0x020E0490 0x00000030
wm 32 0x020E0288 0x00000030
wm 32 0x020E0270 0x00000000
wm 32 0x020E0260 0x00000030
wm 32 0x020E0264 0x00000030
wm 32 0x020E04A0 0x00000030
wm 32 0x020E0494 0x00020000
wm 32 0x020E0280 0x00000030
wm 32 0x020E0284 0x00000030
wm 32 0x020E04B0 0x00020000
wm 32 0x020E0498 0x00000030
wm 32 0x020E04A4 0x00000030
wm 32 0x020E0244 0x00000030
wm 32 0x020E0248 0x00000030
wm 32 0x021B001C 0x00008000
wm 32 0x021B0800 0xA1390003
wm 32 0x021B080C 0x00000000
wm 32 0x021B083C 0x41480148
wm 32 0x021B0848 0x40403E42
wm 32 0x021B0850 0x40405852
wm 32 0x021B081C 0x33333333
wm 32 0x021B0820 0x33333333
wm 32 0x021B082C 0xf3333333
wm 32 0x021B0830 0xf3333333
wm 32 0x021B08C0 0x00922012
wm 32 0x021B0858 0x00000F00
wm 32 0x021B08b8 0x00000800
wm 32 0x021B0004 0x0002002D
wm 32 0x021B0008 0x1B333030
SETUP_MDCFG0
wm 32 0x021B0010 0xB66D0B63
wm 32 0x021B0014 0x01FF00DB
wm 32 0x021B0018 0x00211740
wm 32 0x021B001C 0x00008000
wm 32 0x021B002C 0x000026D2
wm 32 0x021B0030 0x006B1023
SETUP_MDASP_MDCTL
wm 32 0x021b0890 0x00400A38
wm 32 0x021B001C 0x02008032
wm 32 0x021B001C 0x00008033
wm 32 0x021B001C 0x00048031
wm 32 0x021B001C 0x15208030
wm 32 0x021B001C 0x04008040
wm 32 0x021B0020 0x00007800
wm 32 0x021B0818 0x00000227
wm 32 0x021B0004 0x0002556D
wm 32 0x021B0404 0x00011006
wm 32 0x021B001C 0x00000000

21
arch/arm/boards/phytec-som-imx6/lowlevel.c
View File

@ -51,17 +51,28 @@ static void __noreturn start_imx6_phytec_common(uint32_t size,
bool do_early_uart_config,
void *fdt_blob_fixed_offset)
{
int cpu_type = __imx6_cpu_type();
void *fdt;
imx6_cpu_lowlevel_init();
arm_setup_stack(0x00920000 - 8);
if (cpu_type == IMX6_CPUTYPE_IMX6UL) {
arm_cpu_lowlevel_init();
/* OCRAM Free Area is 0x00907000 to 0x00918000 (68KB) */
arm_setup_stack(0x00910000 - 8);
} else {
imx6_cpu_lowlevel_init();
/* OCRAM Free Area is 0x00907000 to 0x00938000 (196KB) */
arm_setup_stack(0x00920000 - 8);
}
if (do_early_uart_config && IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
fdt = fdt_blob_fixed_offset - get_runtime_offset();
barebox_arm_entry(0x10000000, size, fdt);
if (cpu_type == IMX6_CPUTYPE_IMX6UL)
barebox_arm_entry(0x80000000, size, fdt);
else
barebox_arm_entry(0x10000000, size, fdt);
}
#define PHYTEC_ENTRY(name, fdt_name, memory_size, do_early_uart_config) \
@ -98,3 +109,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6dl_som_emmc_1gib, imx6dl_phytec_phycore_so
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_nand_1gib, imx6q_phytec_phycore_som_nand, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_emmc, SZ_1G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);

3
arch/arm/dts/Makefile
View File

@ -51,7 +51,8 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
imx6q-phytec-phycore-som-nand.dtb.o \
imx6q-phytec-phycore-som-emmc.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6ul-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += kirkwood-openblocks_a6-bb.dtb.o
pbl-dtb-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o

17
arch/arm/dts/imx6dl-phytec-phycore-som-emmc.dts
View File

@ -29,21 +29,12 @@
status = "okay";
};
&ethphy {
max-speed = <100>;
};
&fec {
status = "okay";
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 14 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
reg = <3>;
max-speed = <100>;
};
};
};
&flash {

17
arch/arm/dts/imx6dl-phytec-phycore-som-nand.dts
View File

@ -24,21 +24,12 @@
status = "okay";
};
&ethphy {
max-speed = <100>;
};
&fec {
status = "okay";
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 14 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
reg = <3>;
max-speed = <100>;
};
};
};
&gpmi {

17
arch/arm/dts/imx6q-phytec-phycore-som-emmc.dts
View File

@ -28,21 +28,12 @@
status = "okay";
};
&ethphy {
max-speed = <1000>;
};
&fec {
status = "okay";
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 14 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
reg = <3>;
max-speed = <1000>;
};
};
};
&flash {

17
arch/arm/dts/imx6q-phytec-phycore-som-nand.dts
View File

@ -29,21 +29,12 @@
status = "okay";
};
&ethphy {
max-speed = <1000>;
};
&fec {
status = "okay";
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 14 1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
reg = <3>;
max-speed = <1000>;
};
};
};
&flash {

20
arch/arm/dts/imx6qdl-phytec-phycore-som.dtsi
View File

@ -9,7 +9,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx6qdl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
@ -76,7 +76,21 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-handle = <&ethphy>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
status = "disabled";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@3 {
reg = <3>;
txc-skew-ps = <1680>;
rxc-skew-ps = <1860>;
};
};
};
&gpmi {
@ -119,9 +133,9 @@
clock-frequency = <400000>;
status = "okay";
eeprom: 24c32@50 {
eeprom: eeprom@50 {
status = "disabled";
compatible = "st,24c32";
compatible = "24c32";
reg = <0x50>;
};
};

185
arch/arm/dts/imx6ul-phytec-phycore-som.dts Normal file
View File

@ -0,0 +1,185 @@
/*
* Copyright (C) 2016 PHYTEC Messtechnik GmbH
* Author: Christian Hemp <c.hemp@phytec.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include <arm/imx6ul.dtsi>
/ {
model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
chosen {
linux,stdout-path = &uart1;
environment-nand {
compatible = "barebox,environment";
device-path = &gpmi, "partname:barebox-environment";
status = "disabled";
};
environment-sd1 {
compatible = "barebox,environment";
device-path = &usdhc1, "partname:barebox-environment";
status = "disabled";
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
reg = <1>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "barebox-environment";
reg = <0x400000 0x100000>;
};
partition@500000 {
label = "root";
reg = <0x500000 0x0>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 =<&pinctrl_i2c1>;
clock-frequency = <100000>;
status = "okay";
eeprom@52 {
compatible = "cat,24c32";
reg = <0x52>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0xe0000>;
};
partition@e0000 {
label = "barebox-environment";
reg = <0xe0000 0x20000>;
};
};
&iomuxc {
pinctrl-names = "default";
imx6ul-phytec-phycore-som {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_i2c1: i2cgrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
>;
};
};
};

5
arch/arm/mach-imx/Kconfig
View File

@ -80,6 +80,10 @@ config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
depends on MTD_WRITE
default y
config RESET_IMX_SRC
def_bool y
depends on ARCH_IMX6 || ARCH_IMX50 || ARCH_IMX51 || ARCH_IMX53
comment "Freescale i.MX System-on-Chip"
config ARCH_IMX1
@ -258,6 +262,7 @@ config MACH_FREESCALE_MX53_VMX53
config MACH_PHYTEC_SOM_IMX6
bool "Phytec phyCARD-i.MX6 and phyFLEX-i.MX6"
select ARCH_IMX6
select ARCH_IMX6UL
config MACH_DFI_FS700_M60
bool "DFI i.MX6 FS700 M60 Q7 Board"

1
arch/arm/mach-imx/Makefile
View File

@ -25,5 +25,6 @@ obj-y += devices.o imx.o
obj-pbl-y += esdctl.o boot.o
obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
obj-$(CONFIG_RESET_IMX_SRC) += src.o
lwl-y += cpu_init.o
pbl-y += xload-spi.o xload-esdhc.o xload-common.o xload-imx-nand.o

57
arch/arm/mach-imx/src.c Normal file
View File

@ -0,0 +1,57 @@
/*
* Copyright 2016 Sascha Hauer <s.hauer@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <common.h>
#include <init.h>
#include <io.h>
#include <linux/err.h>
#define SRC_SCR 0x0
#define SCR_WARM_RESET_ENABLE BIT(0)
static int imx_src_reset_probe(struct device_d *dev)
{
struct resource *res;
u32 val;
void __iomem *membase;
res = dev_request_mem_resource(dev, 0);
if (IS_ERR(res))
return PTR_ERR(res);
membase = IOMEM(res->start);
/*
* Generate cold reset for warm reset sources. Needed for
* some boards to come up properly after reset.
*/
val = readl(membase + SRC_SCR);
val &= ~SCR_WARM_RESET_ENABLE;
writel(val, membase + SRC_SCR);
return 0;
}
static const struct of_device_id imx_src_dt_ids[] = {
{ .compatible = "fsl,imx51-src", },
{ /* sentinel */ },
};
static struct driver_d imx_src_reset_driver = {
.name = "imx-src",
.probe = imx_src_reset_probe,
.of_compatible = DRV_OF_COMPAT(imx_src_dt_ids),
};
static int imx_src_reset_init(void)
{
return platform_driver_register(&imx_src_reset_driver);
}
postcore_initcall(imx_src_reset_init);

83
common/imx-bbu-nand-fcb.c
View File

@ -167,6 +167,46 @@ static uint32_t calc_chksum(void *buf, size_t size)
return ~chksum;
}
struct fcb_block *read_fcb_hamming_13_8(void *rawpage)
{
int i;
int bitflips = 0, bit_to_flip;
u8 parity, np, syndrome;
u8 *fcb, *ecc;
fcb = rawpage + 12;
ecc = rawpage + 512 + 12;
for (i = 0; i < 512; i++) {
parity = ecc[i];
np = calculate_parity_13_8(fcb[i]);
syndrome = np ^ parity;
if (syndrome == 0)
continue;
if (!(hweight8(syndrome) & 1)) {
pr_err("Uncorrectable error at offset %d\n", i);
return ERR_PTR(-EIO);
}
bit_to_flip = lookup_single_error_13_8(syndrome);
if (bit_to_flip < 0) {
pr_err("Uncorrectable error at offset %d\n", i);
return ERR_PTR(-EIO);
}
bitflips++;
if (bit_to_flip > 7)
ecc[i] ^= 1 << (bit_to_flip - 8);
else
fcb[i] ^= 1 << bit_to_flip;
}
return xmemdup(rawpage + 12, 512);
}
static __maybe_unused void dump_fcb(void *buf)
{
struct fcb_block *fcb = buf;
@ -258,11 +298,8 @@ static ssize_t raw_write_page(struct mtd_info *mtd, void *buf, loff_t offset)
static int read_fcb(struct mtd_info *mtd, int num, struct fcb_block **retfcb)
{
int i;
int bitflips = 0, bit_to_flip;
u8 parity, np, syndrome;
u8 *fcb, *ecc;
int ret;
struct fcb_block *fcb;
void *rawpage;
*retfcb = NULL;
@ -275,40 +312,14 @@ static int read_fcb(struct mtd_info *mtd, int num, struct fcb_block **retfcb)
goto err;
}
fcb = rawpage + 12;
ecc = rawpage + 512 + 12;
for (i = 0; i < 512; i++) {
parity = ecc[i];
np = calculate_parity_13_8(fcb[i]);
syndrome = np ^ parity;
if (syndrome == 0)
continue;
if (!(hweight8(syndrome) & 1)) {
pr_err("Uncorrectable error at offset %d\n", i);
ret = -EIO;
goto err;
}
bit_to_flip = lookup_single_error_13_8(syndrome);
if (bit_to_flip < 0) {
pr_err("Uncorrectable error at offset %d\n", i);
ret = -EIO;
goto err;
}
bitflips++;
if (bit_to_flip > 7)
ecc[i] ^= 1 << (bit_to_flip - 8);
else
fcb[i] ^= 1 << bit_to_flip;
fcb = read_fcb_hamming_13_8(rawpage);
if (IS_ERR(fcb)) {
pr_err("Cannot read fcb\n");
ret = PTR_ERR(fcb);
goto err;
}
*retfcb = xmemdup(rawpage + 12, 512);
*retfcb = fcb;
ret = 0;
err:
free(rawpage);

7
drivers/hab/habv4.c
View File

@ -27,6 +27,7 @@
#define HABV4_RVT_IMX28 0xffff8af8
#define HABV4_RVT_IMX6_OLD 0x00000094
#define HABV4_RVT_IMX6_NEW 0x00000098
#define HABV4_RVT_IMX6UL 0x00000100
enum hab_tag {
HAB_TAG_IVT = 0xd1, /* Image Vector Table */
@ -227,6 +228,10 @@ int imx6_hab_get_status(void)
if (rvt->header.tag == HAB_TAG_RVT)
return habv4_get_status(rvt);
rvt = (void *)HABV4_RVT_IMX6UL;
if (rvt->header.tag == HAB_TAG_RVT)
return habv4_get_status(rvt);
pr_err("ERROR - RVT not found!\n");
return -EINVAL;
@ -237,4 +242,4 @@ int imx28_hab_get_status(void)
const struct habv4_rvt *rvt = (void *)HABV4_RVT_IMX28;
return habv4_get_status(rvt);
}
}

2
drivers/mci/imx-esdhc.c
View File

@ -647,6 +647,8 @@ static __maybe_unused struct of_device_id fsl_esdhc_compatible[] = {
.compatible = "fsl,imx6q-usdhc",
}, {
.compatible = "fsl,imx6sl-usdhc",
}, {
.compatible = "fsl,imx6sx-usdhc",
}, {
/* sentinel */
}

4
drivers/pwm/core.c
View File

@ -281,6 +281,8 @@ unsigned int pwm_get_duty_cycle(struct pwm_device *pwm)
*/
int pwm_enable(struct pwm_device *pwm)
{
pwm->p_enable = 1;
if (!test_and_set_bit(FLAG_ENABLED, &pwm->flags))
return pwm->chip->ops->enable(pwm->chip);
@ -293,6 +295,8 @@ EXPORT_SYMBOL_GPL(pwm_enable);
*/
void pwm_disable(struct pwm_device *pwm)
{
pwm->p_enable = 0;
if (test_and_clear_bit(FLAG_ENABLED, &pwm->flags))
pwm->chip->ops->disable(pwm->chip);
}

8
drivers/spi/imx_spi.c
View File

@ -348,6 +348,13 @@ static u32 imx_xchg_single(struct spi_device *spi, u32 tx_val)
return imx_spi_maybe_reverse_bits(spi, rx_val);
}
static void cspi_2_3_init(struct imx_spi *imx)
{
void __iomem *base = imx->regs;
writel(0, base + CSPI_2_3_CTRL);
}
static void imx_spi_do_transfer(struct spi_device *spi)
{
struct imx_spi *imx = container_of(spi->master, struct imx_spi, master);
@ -519,6 +526,7 @@ static __maybe_unused struct spi_imx_devtype_data spi_imx_devtype_data_2_3 = {
.chipselect = cspi_2_3_chipselect,
.do_transfer = cspi_2_3_do_transfer,
.xchg_single = cspi_2_3_xchg_single,
.init = cspi_2_3_init,
};
static int imx_spi_dt_probe(struct imx_spi *imx)

4
drivers/video/imx-ipu-v3/Kconfig
View File

@ -16,4 +16,8 @@ config DRIVER_VIDEO_IMX_IPUV3_HDMI
depends on DRIVER_VIDEO_EDID
select OFDEVICE
config DRIVER_VIDEO_IMX_IPUV3_PARALLEL
bool "IPUv3 parallel display support"
select OFDEVICE
endif

1
drivers/video/imx-ipu-v3/Makefile
View File

@ -3,3 +3,4 @@ obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-dp.o ipuv3-plane.o ipufb.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3) += ipu-dc.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3_LVDS) += imx-ldb.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3_HDMI) += imx-hdmi.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPUV3_PARALLEL) += imx-pd.o

118
drivers/video/imx-ipu-v3/imx-pd.c Normal file
View File

@ -0,0 +1,118 @@
/*
* i.MX drm driver - parallel display implementation
*
* Copyright (C) 2016 Philippe Leduc
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <fb.h>
#include <io.h>
#include <of_graph.h>
#include <driver.h>
#include <malloc.h>
#include <errno.h>
#include <init.h>
#include <video/vpl.h>
#include <video/media-bus-format.h>
#include <linux/err.h>
#include "imx-ipu-v3.h"
struct imx_pd {
struct device_d *dev;
struct display_timings *timings;
u32 bus_format;
struct vpl vpl;
};
static int imx_pd_ioctl(struct vpl *vpl, unsigned int port,
unsigned int cmd, void *data)
{
struct imx_pd *imx_pd = container_of(vpl, struct imx_pd, vpl);
struct ipu_di_mode *mode;
struct display_timings *timings;
switch (cmd) {
case IMX_IPU_VPL_DI_MODE:
mode = data;
mode->di_clkflags = IPU_DI_CLKMODE_SYNC;
mode->bus_format = imx_pd->bus_format;
return 0;
case VPL_GET_VIDEOMODES:
timings = data;
timings->num_modes = imx_pd->timings->num_modes;
timings->native_mode = imx_pd->timings->native_mode;
timings->modes = imx_pd->timings->modes;
timings->edid = NULL;
return 0;
}
return 0;
}
static int imx_pd_probe(struct device_d *dev)
{
struct device_node *node = dev->device_node;
struct imx_pd *imx_pd;
const char *fmt;
int ret;
imx_pd = xzalloc(sizeof(*imx_pd));
imx_pd->dev = dev;
ret = of_property_read_string(node, "interface-pix-fmt", &fmt);
if (!ret) {
if (!strcmp(fmt, "rgb24"))
imx_pd->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
else if (!strcmp(fmt, "rgb565"))
imx_pd->bus_format = MEDIA_BUS_FMT_RGB565_1X16;
else if (!strcmp(fmt, "bgr666"))
imx_pd->bus_format = MEDIA_BUS_FMT_RGB666_1X18;
else {
dev_err(dev, "invalid interface-pix-fmt\n");
return -EINVAL;
}
}
imx_pd->timings = of_get_display_timings(node);
if (!imx_pd->timings) {
dev_err(dev, "No display timings panel found\n");
return -EINVAL;
}
imx_pd->vpl.node = node;
imx_pd->vpl.ioctl = &imx_pd_ioctl;
ret = vpl_register(&imx_pd->vpl);
if (ret)
return ret;
return 0;
}
static struct of_device_id imx_pd_dt_ids[] = {
{ .compatible = "fsl,imx-parallel-display", },
{ /* sentinel */ }
};
static struct driver_d imx_pd_driver = {
.probe = imx_pd_probe,
.of_compatible = imx_pd_dt_ids,
.name = "imx-parallel-display",
};
device_platform_driver(imx_pd_driver);
MODULE_DESCRIPTION("i.MX Parallel display driver");
MODULE_AUTHOR("Philippe Leduc");
MODULE_LICENSE("GPL");

5
drivers/video/imx-ipu-v3/ipufb.c
View File

@ -128,8 +128,9 @@ int ipu_crtc_mode_set(struct ipufb_info *fbi,
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
sig_cfg.Vsync_pol = 1;
sig_cfg.enable_pol = 1;
sig_cfg.clk_pol = 0;
sig_cfg.enable_pol = !(mode->display_flags & DISPLAY_FLAGS_DE_LOW);
/* Default to driving pixel data on negative clock edges */
sig_cfg.clk_pol = !!(mode->display_flags & DISPLAY_FLAGS_PIXDATA_POSEDGE);
sig_cfg.width = mode->xres;
sig_cfg.height = mode->yres;
sig_cfg.h_start_width = mode->left_margin;

5
images/Makefile.imx
View File

@ -394,6 +394,11 @@ CFG_start_phytec_phycore_imx6dl_som_emmc_1gib.pblx.imximg = $(board)/phytec-som-
FILE_barebox-phytec-phycore-imx6dl-som-emmc-1gib.img = start_phytec_phycore_imx6dl_som_emmc_1gib.pblx.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6dl-som-emmc-1gib.img
pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ul_som_512mb
CFG_start_phytec_phycore_imx6ul_som_512mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
FILE_barebox-phytec-phycore-imx6ul-512mb.img = start_phytec_phycore_imx6ul_som_512mb.pblx.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img
pblx-$(CONFIG_MACH_GW_VENTANA) += start_imx6q_gw54xx_1gx64
CFG_start_imx6q_gw54xx_1gx64.pblx.imximg = $(board)/gateworks-ventana/flash-header-ventana-quad-1gx64.imxcfg
FILE_barebox-gateworks-imx6q-ventana-1gx64.img = start_imx6q_gw54xx_1gx64.pblx.imximg

63
scripts/imx/imx-usb-loader.c
View File

@ -82,6 +82,34 @@ struct mach_id imx_ids[] = {
.pid = 0x3780,
.name = "i.MX23",
.mode = MODE_BULK,
}, {
.vid = 0x15a2,
.pid = 0x0030,
.name = "i.MX35",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
}, {
.vid = 0x15a2,
.pid = 0x003a,
.name = "i.MX25",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
}, {
.vid = 0x15a2,
.pid = 0x0041,
.name = "i.MX51",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
}, {
.vid = 0x15a2,
.pid = 0x004e,
.name = "i.MX53",
.header_type = HDR_MX53,
.mode = MODE_BULK,
.max_transfer = 512,
}, {
.vid = 0x15a2,
.pid = 0x004f,
@ -107,6 +135,13 @@ struct mach_id imx_ids[] = {
.header_type = HDR_MX53,
.mode = MODE_HID,
.max_transfer = 1024,
}, {
.vid = 0x15a2,
.pid = 0x0063,
.name = "i.MX6sl",
.header_type = HDR_MX53,
.mode = MODE_HID,
.max_transfer = 1024,
}, {
.vid = 0x15a2,
.pid = 0x0071,
@ -121,34 +156,6 @@ struct mach_id imx_ids[] = {
.header_type = HDR_MX53,
.mode = MODE_HID,
.max_transfer = 1024,
}, {
.vid = 0x15a2,
.pid = 0x0041,
.name = "i.MX51",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
}, {
.vid = 0x15a2,
.pid = 0x004e,
.name = "i.MX53",
.header_type = HDR_MX53,
.mode = MODE_BULK,
.max_transfer = 512,
}, {
.vid = 0x15a2,
.pid = 0x0030,
.name = "i.MX35",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
}, {
.vid = 0x15a2,
.pid = 0x003a,
.name = "i.MX25",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
},
};