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barebox
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Merge branch 'for-next/imx'

This commit is contained in:
Sascha Hauer 2013-12-06 08:22:48 +01:00
parent 28124d02f2 f87af10fb1
commit 0cb6f2c19e
38 changed files with 1348 additions and 206 deletions
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2
arch/arm/boards/Makefile
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@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_FREESCALE_MX35_3STACK) += freescale-mx35-3-stack/
obj-$(CONFIG_MACH_FREESCALE_MX51_PDK) += freescale-mx51-pdk/
obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += freescale-mx53-loco/
obj-$(CONFIG_MACH_FREESCALE_MX53_SMD) += freescale-mx53-smd/
obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/
obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/
obj-$(CONFIG_MACH_GK802) += gk802/
obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/
@ -77,6 +78,7 @@ obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += solidrun-carrier-1/
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/

3
arch/arm/boards/freescale-mx53-vmx53/Makefile Normal file
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@ -0,0 +1,3 @@
obj-y += board.o flash-header-imx53-vmx53.dcd.o
extra-y += flash-header-imx53-vmx53.dcd.S flash-header-imx53-vmx53.dcd
lwl-y += lowlevel.o

57
arch/arm/boards/freescale-mx53-vmx53/board.c Normal file
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@ -0,0 +1,57 @@
/*
* Copyright (C) 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
*
* Board specific file for Voipac X53-DMM-668 module equipped
* with i.MX53 CPU
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <init.h>
#include <sizes.h>
#include <generated/mach-types.h>
#include <mach/imx5.h>
#include <asm/armlinux.h>
#include <mach/bbu.h>
extern char flash_header_imx53_vmx53_start[];
extern char flash_header_imx53_vmx53_end[];
static int vmx53_late_init(void)
{
armlinux_set_bootparams((void *)0x70000100);
armlinux_set_architecture(MACH_TYPE_VMX53);
barebox_set_model("Voipac VMX53");
barebox_set_hostname("vmx53");
imx53_bbu_internal_nand_register_handler("nand",
BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_imx53_vmx53_start,
flash_header_imx53_vmx53_end - flash_header_imx53_vmx53_start,
SZ_512K, 0);
return 0;
}
late_initcall(vmx53_late_init);
static int vmx53_postcore_init(void)
{
if (!of_machine_is_compatible("voipac,imx53-dmm-668"))
return 0;
imx53_init_lowlevel(800);
return 0;
}
postcore_initcall(vmx53_postcore_init);

7
arch/arm/boards/freescale-mx53-vmx53/env/config-board vendored Normal file
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@ -0,0 +1,7 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=vmx53
global.linux.bootargs.base="console=ttymxc0,115200"

54
arch/arm/boards/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg Normal file
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@ -0,0 +1,54 @@
loadaddr 0x70000000
soc imx53
dcdofs 0x400
wm 32 0x53fa8554 0x00300000
wm 32 0x53fa8558 0x00300040
wm 32 0x53fa8560 0x00300000
wm 32 0x53fa8564 0x00300040
wm 32 0x53fa8568 0x00300040
wm 32 0x53fa8570 0x00300000
wm 32 0x53fa8574 0x00300000
wm 32 0x53fa8578 0x00300000
wm 32 0x53fa857c 0x00300040
wm 32 0x53fa8580 0x00300040
wm 32 0x53fa8584 0x00300000
wm 32 0x53fa8588 0x00300000
wm 32 0x53fa8590 0x00300040
wm 32 0x53fa8594 0x00300000
wm 32 0x53fa86f0 0x00300000
wm 32 0x53fa86f4 0x00000000
wm 32 0x53fa86fc 0x00000000
wm 32 0x53fa8714 0x00000000
wm 32 0x53fa8718 0x00300000
wm 32 0x53fa871c 0x00300000
wm 32 0x53fa8720 0x00300000
wm 32 0x53fa8724 0x04000000
wm 32 0x53fa8728 0x00300000
wm 32 0x53fa872c 0x00300000
wm 32 0x63fd9088 0x35343535
wm 32 0x63fd9090 0x4d444c44
wm 32 0x63fd907c 0x01370138
wm 32 0x63fd9080 0x013b013c
wm 32 0x63fd9018 0x00011740
wm 32 0x63fd9000 0xc4190000
wm 32 0x63fd900c 0x9f5152e3
wm 32 0x63fd9010 0xb68e8a63
wm 32 0x63fd9014 0x01ff00db
wm 32 0x63fd902c 0x000026d2
wm 32 0x63fd9030 0x009f0e21
wm 32 0x63fd9008 0x12273030
wm 32 0x63fd9004 0x0002002d
wm 32 0x63fd901c 0x00008032
wm 32 0x63fd901c 0x00008033
wm 32 0x63fd901c 0x00028031
wm 32 0x63fd901c 0x052080b0
wm 32 0x63fd901c 0x04008040
wm 32 0x63fd901c 0x0000803a
wm 32 0x63fd901c 0x0000803b
wm 32 0x63fd901c 0x00028039
wm 32 0x63fd901c 0x05208138
wm 32 0x63fd901c 0x04008048
wm 32 0x63fd9020 0x00005800
wm 32 0x63fd9040 0x04b80003
wm 32 0x63fd9058 0x00022227
wm 32 0x63fd901c 0x00000000

19
arch/arm/boards/freescale-mx53-vmx53/lowlevel.c Normal file
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@ -0,0 +1,19 @@
#include <common.h>
#include <mach/esdctl.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
extern char __dtb_imx53_voipac_bsb_start[];
ENTRY_FUNCTION(start_imx53_vmx53)(void)
{
uint32_t fdt;
__barebox_arm_head();
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx53_voipac_bsb_start - get_runtime_offset();
imx53_barebox_entry(fdt);
}

4
arch/arm/boards/freescale-mx6-sabrelite/Makefile
View File

@ -1,3 +1,3 @@
obj-y += board.o
lwl-y += flash_header.o
obj-y += board.o flash-header-mx6-sabrelite.dcd.o
extra-y += flash-header-mx6-sabrelite.dcd.S flash-header-mx6-sabrelite.dcd
lwl-y += lowlevel.o

23
arch/arm/boards/freescale-mx6-sabrelite/board.c
View File

@ -20,6 +20,7 @@
#include <mach/imx6-regs.h>
#include <fec.h>
#include <gpio.h>
#include <mach/bbu.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
@ -107,26 +108,24 @@ fs_initcall(sabrelite_ksz9021rn_setup);
static void sabrelite_ehci_init(void)
{
imx6_usb_phy2_disable_oc();
imx6_usb_phy2_enable();
/* hub reset */
gpio_direction_output(204, 0);
udelay(2000);
gpio_set_value(204, 1);
add_generic_usb_ehci_device(1, MX6_USBOH3_USB_BASE_ADDR + 0x200, NULL);
}
static int sabrelite_devices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite"))
return 0;
sabrelite_ehci_init();
armlinux_set_bootparams((void *)0x10000100);
armlinux_set_architecture(3769);
devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("m25p0", SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, "env0");
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT, NULL, 0, 0);
return 0;
}
@ -134,18 +133,24 @@ device_initcall(sabrelite_devices_init);
static int sabrelite_coredevices_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite"))
return 0;
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
return 0;
}
coredevice_initcall(sabrelite_coredevices_init);
static int sabrelite_core_init(void)
static int sabrelite_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("sabrelite");
return 0;
}
core_initcall(sabrelite_core_init);
postcore_initcall(sabrelite_postcore_init);

106
arch/arm/boards/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg Normal file
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@ -0,0 +1,106 @@
soc imx6
loadaddr 0x20000000
dcdofs 0x400
wm 32 0x020e05a8 0x00000030
wm 32 0x020e05b0 0x00000030
wm 32 0x020e0524 0x00000030
wm 32 0x020e051c 0x00000030
wm 32 0x020e0518 0x00000030
wm 32 0x020e050c 0x00000030
wm 32 0x020e05b8 0x00000030
wm 32 0x020e05c0 0x00000030
wm 32 0x020e05ac 0x00020030
wm 32 0x020e05b4 0x00020030
wm 32 0x020e0528 0x00020030
wm 32 0x020e0520 0x00020030
wm 32 0x020e0514 0x00020030
wm 32 0x020e0510 0x00020030
wm 32 0x020e05bc 0x00020030
wm 32 0x020e05c4 0x00020030
wm 32 0x020e056c 0x00020030
wm 32 0x020e0578 0x00020030
wm 32 0x020e0588 0x00020030
wm 32 0x020e0594 0x00020030
wm 32 0x020e057c 0x00020030
wm 32 0x020e0590 0x00003000
wm 32 0x020e0598 0x00003000
wm 32 0x020e058c 0x00000000
wm 32 0x020e059c 0x00003030
wm 32 0x020e05a0 0x00003030
wm 32 0x020e0784 0x00000030
wm 32 0x020e0788 0x00000030
wm 32 0x020e0794 0x00000030
wm 32 0x020e079c 0x00000030
wm 32 0x020e07a0 0x00000030
wm 32 0x020e07a4 0x00000030
wm 32 0x020e07a8 0x00000030
wm 32 0x020e0748 0x00000030
wm 32 0x020e074c 0x00000030
wm 32 0x020e0750 0x00020000
wm 32 0x020e0758 0x00000000
wm 32 0x020e0774 0x00020000
wm 32 0x020e078c 0x00000030
wm 32 0x020e0798 0x000c0000
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b481c 0x33333333
wm 32 0x021b4820 0x33333333
wm 32 0x021b4824 0x33333333
wm 32 0x021b4828 0x33333333
wm 32 0x021b0018 0x00081740
wm 32 0x021b001c 0x00008000
wm 32 0x021b000c 0x555a7975
wm 32 0x021b0010 0xff538e64
wm 32 0x021b0014 0x01ff00db
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 0x005b0e21
wm 32 0x021b0008 0x09444040
wm 32 0x021b0004 0x00025576
wm 32 0x021b0040 0x00000027
wm 32 0x021b0000 0x831a0000
wm 32 0x021b001c 0x04088032
wm 32 0x021b001c 0x0408803a
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x0000803b
wm 32 0x021b001c 0x00428031
wm 32 0x021b001c 0x00428039
wm 32 0x021b001c 0x09408030
wm 32 0x021b001c 0x09408038
wm 32 0x021b001c 0x04008040
wm 32 0x021b001c 0x04008048
wm 32 0x021b0800 0xa1380003
wm 32 0x021b4800 0xa1380003
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00022227
wm 32 0x021b4818 0x00022227
wm 32 0x021b083c 0x434b0350
wm 32 0x021b0840 0x034c0359
wm 32 0x021b483c 0x434b0350
wm 32 0x021b4840 0x03650348
wm 32 0x021b0848 0x4436383b
wm 32 0x021b4848 0x39393341
wm 32 0x021b0850 0x35373933
wm 32 0x021b4850 0x48254A36
wm 32 0x021b080c 0x001f001f
wm 32 0x021b0810 0x001f001f
wm 32 0x021b480c 0x00440044
wm 32 0x021b4810 0x00440044
wm 32 0x021b08b8 0x00000800
wm 32 0x021b48b8 0x00000800
wm 32 0x021b001c 0x00000000
wm 32 0x021b0404 0x00011006
wm 32 0x020c4068 0x00c03f3f
wm 32 0x020c406c 0x0030fc03
wm 32 0x020c4070 0x0fffc000
wm 32 0x020c4074 0x3ff00000
wm 32 0x020c4078 0x00fff300
wm 32 0x020c407c 0x0f0000c3
wm 32 0x020c4080 0x000003ff
/* enable AXI cache for VDOA/VPU/IPU */
wm 32 0x020e0010 0xf00000cf
/* set IPU AXI-id0 Qos=0xf(bypass AXI-id1 Qos=0x7 */
wm 32 0x020e0018 0x007f007f
wm 32 0x020e001c 0x007f007f

178
arch/arm/boards/freescale-mx6-sabrelite/flash_header.c
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@ -1,178 +0,0 @@
/*
* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <asm/byteorder.h>
#include <mach/imx-flash-header.h>
#include <mach/imx6-regs.h>
#include <asm/barebox-arm-head.h>
void __naked __flash_header_start go(void)
{
barebox_arm_head();
}
#define DCD(a, v) { .addr = cpu_to_be32(a), .val = cpu_to_be32(v), }
struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
DCD(MX6_IOMUXC_BASE_ADDR + 0x5a8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x524, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x51c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x518, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x50c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5c0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5ac, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5b4, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x528, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x520, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x514, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x510, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5bc, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5c4, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x56c, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x578, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x588, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x594, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x57c, 0x00020030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x590, 0x00003000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x598, 0x00003000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x58c, 0x00000000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x59c, 0x00003030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x5a0, 0x00003030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x784, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x788, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x794, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x79c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a0, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a4, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x7a8, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x748, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x74c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x750, 0x00020000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x758, 0x00000000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x774, 0x00020000),
DCD(MX6_IOMUXC_BASE_ADDR + 0x78c, 0x00000030),
DCD(MX6_IOMUXC_BASE_ADDR + 0x798, 0x000C0000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x81c, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x820, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x824, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x828, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x81c, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x820, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x824, 0x33333333),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x828, 0x33333333),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x018, 0x00081740),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x008, 0x09444040),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x004, 0x00025576),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x040, 0x00000027),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x000, 0x831A0000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04088032),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00008033),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428031),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00428039),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408030),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x09408038),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008040),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x04008048),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x800, 0xA1380003),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x800, 0xA1380003),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x020, 0x00005800),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x818, 0x00022227),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x818, 0x00022227),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x840, 0x034C0359),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x840, 0x03650348),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x848, 0x4436383B),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x848, 0x39393341),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x850, 0x35373933),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x850, 0x48254A36),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x810, 0x001F001F),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x80c, 0x00440044),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x810, 0x00440044),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800),
DCD(MX6_MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x01c, 0x00000000),
DCD(MX6_MMDC_P0_BASE_ADDR + 0x404, 0x00011006),
DCD(MX6_CCM_BASE_ADDR + 0x068, 0x00c03f3f),
DCD(MX6_CCM_BASE_ADDR + 0x06c, 0x0030fc03),
DCD(MX6_CCM_BASE_ADDR + 0x070, 0x0fffc000),
DCD(MX6_CCM_BASE_ADDR + 0x074, 0x3ff00000),
DCD(MX6_CCM_BASE_ADDR + 0x078, 0x00fff300),
DCD(MX6_CCM_BASE_ADDR + 0x07c, 0x0f0000c3),
DCD(MX6_CCM_BASE_ADDR + 0x080, 0x000003ff),
/* enable AXI cache for VDOA/VPU/IPU */
DCD(MX6_IOMUXC_BASE_ADDR + 0x010, 0xf00000cf),
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DCD(MX6_IOMUXC_BASE_ADDR + 0x018, 0x007f007f),
DCD(MX6_IOMUXC_BASE_ADDR + 0x01c, 0x007f007f),
};
#define APP_DEST CONFIG_TEXT_BASE
struct imx_flash_header_v2 __flash_header_section flash_header = {
.header.tag = IVT_HEADER_TAG,
.header.length = cpu_to_be16(32),
.header.version = IVT_VERSION,
.entry = (u32)_stext,
.dcd_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, dcd),
.boot_data_ptr = APP_DEST + FLASH_HEADER_OFFSET + offsetof(struct imx_flash_header_v2, boot_data),
.self = APP_DEST + FLASH_HEADER_OFFSET,
.boot_data.start = APP_DEST,
.boot_data.size = barebox_image_size,
.dcd.header.tag = DCD_HEADER_TAG,
.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
.dcd.header.version = DCD_VERSION,
.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
};

13
arch/arm/boards/freescale-mx6-sabrelite/lowlevel.c
View File

@ -3,8 +3,17 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
void __naked barebox_arm_reset_vector(void)
extern char __dtb_imx6q_sabrelite_start[];
ENTRY_FUNCTION(start_imx6_sabrelite)(void)
{
uint32_t fdt;
__barebox_arm_head();
arm_cpu_lowlevel_init();
barebox_arm_entry(0x10000000, SZ_1G, 0);
fdt = (uint32_t)__dtb_imx6q_sabrelite_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_1G, fdt);
}

23
arch/arm/boards/karo-tx25/flash-header-tx25.imxcfg Normal file
View File

@ -0,0 +1,23 @@
#
# currently unused in barebox, but useful to generate
# a imx-image to use with imx-usb-loader
#
soc imx25
loadaddr 0x80000000
dcdofs 0x400
wm 32 0xb8001010 0x00000002
wm 32 0xb8001004 0x00095728
wm 32 0xb8001000 0x92116480
wm 32 0x80000400 0x92116480
wm 32 0xb8001000 0xa2116480
wm 32 0xb8001000 0xb2116480
wm 8 0x80000033 0x80
wm 32 0xb8001000 0x82116480
wm 32 0xb800100c 0x00095728
wm 32 0xb8001008 0x92116480
wm 32 0x80000400 0x92116480
wm 32 0xb8001008 0xa2116480
wm 32 0xb8001008 0xb2116480
wm 8 0x90000033 0x80
wm 32 0xb8001008 0x82116480

23
arch/arm/boards/karo-tx25/lowlevel.c
View File

@ -29,6 +29,27 @@
#include <asm/system.h>
#include <asm/sections.h>
#include <asm-generic/memory_layout.h>
#include <debug_ll.h>
static inline void setup_uart(void)
{
void __iomem *uartbase = (void *)MX25_UART1_BASE_ADDR;
void __iomem *iomuxbase = (void *)MX25_IOMUXC_BASE_ADDR;
writel(0x0, iomuxbase + 0x174);
writel(0x00000000, uartbase + 0x80);
writel(0x00004027, uartbase + 0x84);
writel(0x00000704, uartbase + 0x88);
writel(0x00000a81, uartbase + 0x90);
writel(0x0000002b, uartbase + 0x9c);
writel(0x00013880, uartbase + 0xb0);
writel(0x0000047f, uartbase + 0xa4);
writel(0x0000a259, uartbase + 0xa8);
writel(0x00000001, uartbase + 0x80);
putc_ll('>');
}
static inline void __bare_init setup_sdram(uint32_t base, uint32_t esdctl,
uint32_t esdcfg)
@ -113,6 +134,8 @@ void __bare_init __naked barebox_arm_reset_vector(void)
writel(0xffffffff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR1);
writel(0x000fdfff, MX25_CCM_BASE_ADDR + MX25_CCM_CGCR2);
setup_uart();
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0xa0000000)

3
arch/arm/boards/solidrun-carrier-1/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y += board.o flash-header-solidrun-carrier-1.dcd.o
extra-y += flash-header-solidrun-carrier-1.dcd.S flash-header-solidrun-carrier-1.dcd
lwl-y += lowlevel.o

89
arch/arm/boards/solidrun-carrier-1/board.c Normal file
View File

@ -0,0 +1,89 @@
/*
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/armlinux.h>
#include <asm/io.h>
#include <bootsource.h>
#include <common.h>
#include <environment.h>
#include <envfs.h>
#include <gpio.h>
#include <init.h>
#include <mach/generic.h>
#include <mach/imx6-regs.h>
#include <mach/imx6.h>
#include <mfd/imx6q-iomuxc-gpr.h>
#include <sizes.h>
#include <linux/phy.h>
static int ar8035_phy_fixup(struct phy_device *dev)
{
u16 val;
/* Ar803x phy SmartEEE feature cause link status generates glitch,
* which cause ethernet link down/up issue, so disable SmartEEE
*/
phy_write(dev, 0xd, 0x3);
phy_write(dev, 0xe, 0x805d);
phy_write(dev, 0xd, 0x4003);
val = phy_read(dev, 0xe);
phy_write(dev, 0xe, val & ~(1 << 8));
/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
phy_write(dev, 0xd, 0x7);
phy_write(dev, 0xe, 0x8016);
phy_write(dev, 0xd, 0x4007);
val = phy_read(dev, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(dev, 0xe, val);
/* introduce tx clock delay */
phy_write(dev, 0x1d, 0x5);
val = phy_read(dev, 0x1e);
val |= 0x0100;
phy_write(dev, 0x1e, val);
return 0;
}
static int carrier1_device_init(void)
{
if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1"))
return 0;
phy_register_fixup_for_uid(0x004dd072, 0xffffffef, ar8035_phy_fixup);
/* enable USB VBUS */
gpio_direction_output(IMX_GPIO_NR(3, 22), 1);
gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
return 0;
}
device_initcall(carrier1_device_init);
static int carrier1_lwl_init(void)
{
if (!of_machine_is_compatible("solidrun,cubox-i-carrier-1"))
return 0;
barebox_set_hostname("carrier-1");
imx6_init_lowlevel();
return 0;
}
postcore_initcall(carrier1_lwl_init);

79
arch/arm/boards/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg Normal file
View File

@ -0,0 +1,79 @@
loadaddr 0x10000000
soc imx6
dcdofs 0x400
wm 32 0x020e0774 0x000c0000
wm 32 0x020e0754 0x00000000
wm 32 0x020e04ac 0x00000030
wm 32 0x020e04b0 0x00000030
wm 32 0x020e0464 0x00000030
wm 32 0x020e0490 0x00000030
wm 32 0x020e074c 0x00000030
wm 32 0x020e0494 0x00000030
wm 32 0x020e04a4 0x00003000
wm 32 0x020e04a8 0x00003000
wm 32 0x020e04a0 0x00000000
wm 32 0x020e04b4 0x00003030
wm 32 0x020e04b8 0x00003030
wm 32 0x020e076c 0x00000030
wm 32 0x020e0750 0x00000000
wm 32 0x020e04bc 0x00000030
wm 32 0x020e04c0 0x00000030
wm 32 0x020e04c4 0x00000030
wm 32 0x020e04c8 0x00000030
wm 32 0x020e04cc 0x00000000
wm 32 0x020e04d0 0x00000000
wm 32 0x020e04d4 0x00000000
wm 32 0x020e04d8 0x00000000
wm 32 0x020e0760 0x00000000
wm 32 0x020e0764 0x00000030
wm 32 0x020e0770 0x00000030
wm 32 0x020e0778 0x00000030
wm 32 0x020e077c 0x00000030
wm 32 0x020e0780 0x00000000
wm 32 0x020e0784 0x00000000
wm 32 0x020e078c 0x00000000
wm 32 0x020e0748 0x00000000
wm 32 0x020e0470 0x00000030
wm 32 0x020e0474 0x00000030
wm 32 0x020e0478 0x00000030
wm 32 0x020e047c 0x00000030
wm 32 0x020e0480 0x00000000
wm 32 0x020e0484 0x00000000
wm 32 0x020e0488 0x00000000
wm 32 0x020e048c 0x00000000
wm 32 0x021b0800 0xa1390003
wm 32 0x021b4800 0xa1390003
wm 32 0x021b080c 0x000F0011
wm 32 0x021b0810 0x000E000F
wm 32 0x021b083c 0x42240229
wm 32 0x021b0840 0x021a0219
wm 32 0x021b0848 0x4e4f5150
wm 32 0x021b0850 0x35363136
wm 32 0x021b081c 0x33333333
wm 32 0x021b0820 0x33333333
wm 32 0x021b0824 0x33333333
wm 32 0x021b0828 0x33333333
wm 32 0x021b08b8 0x00000800
wm 32 0x021b48b8 0x00000800
wm 32 0x021b0004 0x0002002d
wm 32 0x021b0008 0x00333030
wm 32 0x021b000c 0x40445323
wm 32 0x021b0010 0xb68e8c63
wm 32 0x021b0014 0x01ff00db
wm 32 0x021b0018 0x00001740
wm 32 0x021b001c 0x00008000
wm 32 0x021b002c 0x000026d2
wm 32 0x021b0030 0x00440e21
wm 32 0x021b0040 0x00000017
wm 32 0x021b0400 0x11420000
wm 32 0x021b0000 0x83190000
wm 32 0x021b001c 0x04008032
wm 32 0x021b001c 0x00008033
wm 32 0x021b001c 0x00428031
wm 32 0x021b001c 0x07208030
wm 32 0x021b001c 0x04008040
wm 32 0x021b0020 0x00005800
wm 32 0x021b0818 0x00000007
wm 32 0x021b0004 0x0002556d
wm 32 0x021b0404 0x00011006
wm 32 0x021b001c 0x00000000

18
arch/arm/boards/solidrun-carrier-1/lowlevel.c Normal file
View File

@ -0,0 +1,18 @@
#include <common.h>
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
extern char __dtb_imx6dl_cubox_i_carrier_1_start[];
ENTRY_FUNCTION(start_imx6dl_cubox_i_carrier_1)(void)
{
uint32_t fdt;
__barebox_arm_head();
arm_cpu_lowlevel_init();
fdt = (uint32_t)__dtb_imx6dl_cubox_i_carrier_1_start - get_runtime_offset();
barebox_arm_entry(0x10000000, SZ_512M, fdt);
}

4
arch/arm/configs/freescale-mx6-sabrelite_defconfig
View File

@ -1,7 +1,5 @@
CONFIG_BUILTIN_DTB=y
CONFIG_BUILTIN_DTB_NAME="imx6q-sabrelite"
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX6=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_SABRELITE=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y

2
arch/arm/configs/imx_v7_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_MACH_DFI_FS700_M60=y
CONFIG_MACH_REALQ7=y
CONFIG_MACH_GK802=y
CONFIG_MACH_TQMA6X=y
CONFIG_MACH_SOLIDRUN_CARRIER1=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_IMX_OCOTP=y
@ -87,6 +88,7 @@ CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_AT803X_PHY=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y

9
arch/arm/dts/Makefile
View File

@ -1,6 +1,7 @@
dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
imx51-genesi-efika-sb.dtb
dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb
dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb \
imx53-voipac-bsb.dtb
dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6dl-dfi-fs700-m60-6s.dtb \
imx6q-dfi-fs700-m60-6q.dtb \
@ -9,7 +10,8 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6q-sabresd.dtb \
imx6dl-mba6x.dtb \
imx6q-mba6x.dtb \
imx6q-phytec-pbab01.dtb
imx6q-phytec-pbab01.dtb \
imx6dl-cubox-i-carrier-1.dtb
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb
@ -23,6 +25,7 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o
pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o
pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o
pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6q-phytec-pbab01.dtb.o
pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
@ -33,6 +36,8 @@ pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += imx6dl-cubox-i-carrier-1.dtb.o
pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o
.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
.SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y))

135
arch/arm/dts/imx53-voipac-bsb.dts Normal file
View File

@ -0,0 +1,135 @@
/*
* Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53-voipac-dmm-668.dtsi"
/ {
sound {
compatible = "fsl,imx53-voipac-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-voipac-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio>;
led1 {
label = "led-red";
gpios = <&gpio3 29 0>;
default-state = "off";
};
led2 {
label = "led-orange";
gpios = <&gpio2 31 0>;
default-state = "off";
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
/* SD2_CD */
MX53_PAD_EIM_D25__GPIO3_25 0x80000000
/* SD2_WP */
MX53_PAD_EIM_A19__GPIO2_19 0x80000000
>;
};
led_pin_gpio: led_gpio {
fsl,pins = <
MX53_PAD_EIM_D29__GPIO3_29 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
>;
};
};
/* Keyboard controller */
kpp {
pinctrl_kpp_1: kppgrp-1 {
fsl,pins = <
MX53_PAD_GPIO_9__KPP_COL_6 0xe8
MX53_PAD_GPIO_4__KPP_COL_7 0xe8
MX53_PAD_KEY_COL2__KPP_COL_2 0xe8
MX53_PAD_KEY_COL3__KPP_COL_3 0xe8
MX53_PAD_KEY_COL4__KPP_COL_4 0xe8
MX53_PAD_GPIO_2__KPP_ROW_6 0xe0
MX53_PAD_GPIO_5__KPP_ROW_7 0xe0
MX53_PAD_KEY_ROW2__KPP_ROW_2 0xe0
MX53_PAD_KEY_ROW3__KPP_ROW_3 0xe0
MX53_PAD_KEY_ROW4__KPP_ROW_4 0xe0
>;
};
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>; /* SSI1 */
status = "okay";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio3 25 0>;
wp-gpios = <&gpio2 19 0>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_2>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
clocks = <&clks 150>;
};
};
&kpp {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp_1>;
linux,keymap = <
0x0203003b /* KEY_F1 */
0x0603003c /* KEY_F2 */
0x0207003d /* KEY_F3 */
0x0607003e /* KEY_F4 */
>;
keypad,num-rows = <8>;
keypad,num-columns = <1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};

204
arch/arm/dts/imx53-voipac-dmm-668.dtsi Normal file
View File

@ -0,0 +1,204 @@
/*
* Copyright 2013 Rostislav Lisovy <lisovy@gmail.com>, PiKRON s.r.o.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx53.dtsi"
/ {
model = "Voipac i.MX53 X53-DMM-668";
compatible = "voipac,imx53-dmm-668", "fsl,imx53";
memory@70000000 {
device_type = "memory";
reg = <0x70000000 0x20000000>;
};
memory@b0000000 {
device_type = "memory";
reg = <0xb0000000 0x20000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_3p3v: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
/* Make DA9053 regulator functional */
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
/* FEC Power enable */
MX53_PAD_GPIO_11__GPIO4_1 0x80000000
/* FEC RST */
MX53_PAD_GPIO_12__GPIO4_2 0x80000000
>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio4 2 0>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_2>;
status = "okay";
pmic: dialog@48 {
compatible = "dlg,da9053-aa", "dlg,da9052";
reg = <0x48>;
interrupt-parent = <&gpio7>;
interrupts = <11 0x8>; /* low-level active IRQ at GPIO7_11 */
regulators {
buck1_reg: buck1 {
regulator-name = "BUCKCORE";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-name = "BUCKPRO";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-name = "BUCKMEM";
regulator-min-microvolt = <1420000>;
regulator-max-microvolt = <1580000>;
regulator-always-on;
};
buck4_reg: buck4 {
regulator-name = "BUCKPERI";
regulator-min-microvolt = <2370000>;
regulator-max-microvolt = <2630000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-name = "ldo1_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-name = "ldo2_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-name = "ldo3_3v3";
regulator-min-microvolt = <3250000>;
regulator-max-microvolt = <3350000>;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-name = "ldo4_2v775";
regulator-min-microvolt = <2770000>;
regulator-max-microvolt = <2780000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-name = "ldo5_3v3";
regulator-min-microvolt = <3250000>;
regulator-max-microvolt = <3350000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-name = "ldo6_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
ldo7_reg: ldo7 {
regulator-name = "ldo7_2v75";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
ldo8_reg: ldo8 {
regulator-name = "ldo8_1v8";
regulator-min-microvolt = <1750000>;
regulator-max-microvolt = <1850000>;
regulator-always-on;
};
ldo9_reg: ldo9 {
regulator-name = "ldo9_1v5";
regulator-min-microvolt = <1450000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
ldo10_reg: ldo10 {
regulator-name = "ldo10_1v3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
};
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_1>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};

15
arch/arm/dts/imx53.dtsi
View File

@ -269,6 +269,14 @@
#interrupt-cells = <2>;
};
kpp: kpp@53f94000 {
compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
reg = <0x53f94000 0x4000>;
interrupts = <60>;
clocks = <&clks 0>;
status = "disabled";
};
wdog1: wdog@53f98000 {
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
@ -587,6 +595,13 @@
MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
>;
};
pinctrl_i2c3_2: i2c3grp-2 {
fsl,pins = <
MX53_PAD_GPIO_3__I2C3_SCL 0xc0000000
MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
>;
};
};
ipu_disp0 {

116
arch/arm/dts/imx6dl-cubox-i-carrier-1.dts Normal file
View File

@ -0,0 +1,116 @@
/*
* Copyright (C) 2013 Russell King
*
* The code contained herein is licensed under the GNU General Public
* License version 2.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
/ {
model = "SolidRun Cubox-i DL/Solo Carrier-1 Board";
compatible = "solidrun,cubox-i-carrier-1", "fsl,imx6dl";
chosen {
linux,stdout-path = &uart1;
environment@0 {
compatible = "barebox,environment";
device-path = &usdhc2, "partname:barebox-environment";
};
};
memory {
reg = <0x10000000 0x20000000>;
};
ir_recv: ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 2 1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_carrier1_gpio1_2>;
};
codec: spdif-transmitter {
compatible = "linux,spdif-dit";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_carrier1_spdif>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
};
&iomuxc {
carrier1 {
pinctrl_carrier1_gpio1_2: carrier1-gpio1_2 {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
>;
};
pinctrl_carrier1_spdif: carrier1-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0>;
};
pinctrl_carrier1_usdhc2: carrier1-usdhc2 {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1f071
>;
};
};
};
&spdif {
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_carrier1_usdhc2>;
vmmc-supply = <&reg_3p3v>;
fsl,cd-controller;
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};

23
arch/arm/dts/imx6q-sabrelite.dts
View File

@ -18,7 +18,12 @@
compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
chosen {
linux,stdout-path = "/soc/aips-bus@02100000/serial@021e8000";
linux,stdout-path = &uart2;
environment@0 {
compatible = "barebox,environment";
device-path = &flash, "partname:barebox-environment";
};
};
memory {
@ -80,6 +85,18 @@
compatible = "sst,sst25vf016b", "m25p80";
spi-max-frequency = <20000000>;
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "barebox";
reg = <0x0 0x80000>;
};
partition@1 {
label = "barebox-environment";
reg = <0x80000 0x80000>;
};
};
};
@ -117,10 +134,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg_1>;
disable-over-current;
phy-mode = "utmi";
dr_mode = "host";
status = "okay";
};
&usbh1 {
phy-mode = "utmi";
dr_mode = "host";
status = "okay";
};

58
arch/arm/dts/imx6qdl-microsom-ar8035.dtsi Normal file
View File

@ -0,0 +1,58 @@
/*
* Copyright 2013 Russell King
*
* The code contained herein is licensed under the GNU General Public
* License version 2.
*
* This describes the hookup for an AR8035 to the IMX6 on the Cubox-i
* MicroSOM.
*
* FIXME: we need to configure PLL_ENET to produce 25MHz, but there
* doesn't seem to be a way to do that yet from DT. (Writing 0x2000
* to 0x020c80e0 phys will do this.)
*/
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-mode = "rgmii";
phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 0>;
status = "okay";
};
&iomuxc {
enet {
pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
/* AR8035 reset */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
/* AR8035 interrupt */
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
/* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
/* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
/* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
/* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
/* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
/* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
/* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
>;
};
};
};

84
arch/arm/dts/imx6qdl-microsom.dtsi Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright 2013 Russell King
*
* The code contained herein is licensed under the GNU General Public
* License version 2.
*/
/ {
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_h1_vbus: usb_h1_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 0 0>;
enable-active-high;
};
reg_usb_otg_vbus: usb_otg_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 0>;
enable-active-high;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_flexcan1>;
status = "okay";
};
&iomuxc {
microsom {
pinctrl_microsom_flexcan1: microsom-flexcan1 {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
>;
};
pinctrl_microsom_usbotg: microsom-usbotg {
/*
* Similar to pinctrl_usbotg_2, but we want it
* pulled down for a fixed host connection.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&usbotg {
phy_type = "utmi";
dr_mode = "host";
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_usbotg>;
status = "okay";
};
&usbh1 {
phy_type = "utmi";
dr_mode = "host";
vbus-supply = <&reg_usb_h1_vbus>;
status = "okay";
};

23
arch/arm/mach-imx/Kconfig
View File

@ -20,6 +20,7 @@ config ARCH_TEXT_BASE
default 0x97f00000 if MACH_FREESCALE_MX51_PDK
default 0x7ff00000 if MACH_FREESCALE_MX53_LOCO
default 0x7ff00000 if MACH_FREESCALE_MX53_SMD
default 0x7ff00000 if MACH_FREESCALE_MX53_VMX53
default 0x87f00000 if MACH_GUF_CUPID
default 0x93d00000 if MACH_TX25
default 0x7ff00000 if MACH_TQMA53
@ -197,6 +198,13 @@ config MACH_FREESCALE_MX53_LOCO
bool "Freescale i.MX53 LOCO"
select ARCH_IMX53
config MACH_FREESCALE_MX53_VMX53
bool "Voipac i.MX53"
select ARCH_IMX53
help
Say Y here if you are using the Voipac Technologies X53-DMM-668
module equipped with a Freescale i.MX53 Processor
config MACH_PHYTEC_PFLA02
bool "Phytec phyFLEX-i.MX6 Ouad"
select ARCH_IMX6
@ -219,6 +227,16 @@ config MACH_TQMA6X
bool "TQ tqma6x on mba6x"
select ARCH_IMX6
config MACH_SABRELITE
bool "Freescale i.MX6 Sabre Lite"
select ARCH_IMX6
select HAVE_DEFAULT_ENVIRONMENT_NEW
select HAVE_PBL_MULTI_IMAGES
config MACH_SOLIDRUN_CARRIER1
bool "SolidRun CuBox-i Carrier-1"
select ARCH_IMX6
endif
# ----------------------------------------------------------
@ -449,11 +467,6 @@ config MACH_MX6Q_ARM2
bool "Freescale i.MX6q Armadillo2"
select ARCH_IMX6
config MACH_SABRELITE
bool "Freescale i.MX6 Sabre Lite"
select ARCH_IMX6
select HAVE_DEFAULT_ENVIRONMENT_NEW
config MACH_SABRESD
bool "Freescale i.MX6 SabreSD"
select ARCH_IMX6

17
drivers/net/fec_imx.c
View File

@ -27,6 +27,8 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <of_net.h>
#include <of_gpio.h>
#include <gpio.h>
#include <asm/mmu.h>
@ -643,6 +645,7 @@ static int fec_probe(struct device_d *dev)
void *base;
int ret;
enum fec_type type;
int phy_reset;
ret = dev_get_drvdata(dev, (unsigned long *)&type);
if (ret)
@ -671,6 +674,20 @@ static int fec_probe(struct device_d *dev)
fec->regs = dev_request_mem_region(dev, 0);
phy_reset = of_get_named_gpio(dev->device_node, "phy-reset-gpios", 0);
if (gpio_is_valid(phy_reset)) {
ret = gpio_request(phy_reset, "phy-reset");
if (ret)
goto err_free;
ret = gpio_direction_output(phy_reset, 0);
if (ret)
goto err_free;
udelay(10);
gpio_set_value(phy_reset, 1);
}
/* Reset chip. */
writel(FEC_ECNTRL_RESET, fec->regs + FEC_ECNTRL);
while(readl(fec->regs + FEC_ECNTRL) & 1) {

5
drivers/net/phy/Kconfig
View File

@ -8,6 +8,11 @@ if PHYLIB
comment "MII PHY device drivers"
config AT803X_PHY
bool "Driver for Atheros AT803X PHYs"
---help---
Currently supports the AT8030, AT8031 and AT8035 PHYs.
config MICREL_PHY
bool "Driver for Micrel PHYs"
---help---

1
drivers/net/phy/Makefile
View File

@ -1,3 +1,4 @@
obj-y += phy.o mdio_bus.o
obj-$(CONFIG_AT803X_PHY) += at803x.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_SMSC_PHY) += smsc.o

121
drivers/net/phy/at803x.c Normal file
View File

@ -0,0 +1,121 @@
/*
* drivers/net/phy/at803x.c
*
* Driver for Atheros 803x PHY
*
* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <common.h>
#include <init.h>
#include <linux/phy.h>
#include <linux/string.h>
#define AT803X_INTR_ENABLE 0x12
#define AT803X_INTR_STATUS 0x13
#define AT803X_WOL_ENABLE 0x01
#define AT803X_DEVICE_ADDR 0x03
#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
#define AT803X_MMD_ACCESS_CONTROL 0x0D
#define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
#define AT803X_FUNC_DATA 0x4003
#define AT803X_DEBUG_ADDR 0x1D
#define AT803X_DEBUG_DATA 0x1E
#define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
#define AT803X_DEBUG_RGMII_TX_CLK_DLY (1 << 8)
static int at803x_config_init(struct phy_device *phydev)
{
int val;
int ret;
u32 features;
features = SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_AUI |
SUPPORTED_FIBRE | SUPPORTED_BNC;
val = phy_read(phydev, MII_BMSR);
if (val < 0)
return val;
if (val & BMSR_ANEGCAPABLE)
features |= SUPPORTED_Autoneg;
if (val & BMSR_100FULL)
features |= SUPPORTED_100baseT_Full;
if (val & BMSR_100HALF)
features |= SUPPORTED_100baseT_Half;
if (val & BMSR_10FULL)
features |= SUPPORTED_10baseT_Full;
if (val & BMSR_10HALF)
features |= SUPPORTED_10baseT_Half;
if (val & BMSR_ESTATEN) {
val = phy_read(phydev, MII_ESTATUS);
if (val < 0)
return val;
if (val & ESTATUS_1000_TFULL)
features |= SUPPORTED_1000baseT_Full;
if (val & ESTATUS_1000_THALF)
features |= SUPPORTED_1000baseT_Half;
}
phydev->supported = features;
phydev->advertising = features;
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
ret = phy_write(phydev, AT803X_DEBUG_ADDR,
AT803X_DEBUG_SYSTEM_MODE_CTRL);
if (ret)
return ret;
ret = phy_write(phydev, AT803X_DEBUG_DATA,
AT803X_DEBUG_RGMII_TX_CLK_DLY);
if (ret)
return ret;
}
return 0;
}
static struct phy_driver at803x_driver[] = {
{
/* ATHEROS 8035 */
.phy_id = 0x004dd072,
.phy_id_mask = 0xffffffef,
.drv.name = "Atheros 8035 ethernet",
.config_init = at803x_config_init,
.features = PHY_GBIT_FEATURES,
.config_aneg = &genphy_config_aneg,
.read_status = &genphy_read_status,
}, {
/* ATHEROS 8030 */
.phy_id = 0x004dd076,
.phy_id_mask = 0xffffffef,
.drv.name = "Atheros 8030 ethernet",
.config_init = at803x_config_init,
.features = PHY_GBIT_FEATURES,
.config_aneg = &genphy_config_aneg,
.read_status = &genphy_read_status,
}, {
/* ATHEROS 8031 */
.phy_id = 0x004dd074,
.phy_id_mask = 0xffffffef,
.drv.name = "Atheros 8031 ethernet",
.config_init = at803x_config_init,
.features = PHY_GBIT_FEATURES,
.config_aneg = &genphy_config_aneg,
.read_status = &genphy_read_status,
} };
static int atheros_phy_init(void)
{
return phy_drivers_register(at803x_driver,
ARRAY_SIZE(at803x_driver));
}
fs_initcall(atheros_phy_init);

5
drivers/of/Kconfig
View File

@ -19,6 +19,11 @@ config OF_NET
depends on NET
def_bool y
config OF_GPIO
depends on CONFIG_GPIOLIB
depends on CONFIG_OFDEVICE
def_bool y
config OF_BAREBOX_DRIVERS
depends on OFDEVICE
depends on ENV_HANDLING

2
drivers/of/Makefile
View File

@ -1,6 +1,6 @@
obj-y += address.o base.o fdt.o platform.o
obj-$(CONFIG_OFTREE_MEM_GENERIC) += mem_generic.o
obj-$(CONFIG_GPIOLIB) += of_gpio.o
obj-$(CONFIG_OF_GPIO) += of_gpio.o
obj-y += partition.o
obj-y += of_net.o
obj-$(CONFIG_MTD) += of_mtd.o

15
images/Makefile.imx
View File

@ -26,6 +26,11 @@ CFG_start_imx53_loco.pblx.imximg = $(board)/freescale-mx53-loco/flash-header-imx
FILE_barebox-freescale-imx53-loco.img = start_imx53_loco.pblx.imximg
image-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += barebox-freescale-imx53-loco.img
pblx-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += start_imx53_vmx53
CFG_start_imx53_vmx53.pblx.imximg = $(board)/freescale-mx53-vmx53/flash-header-imx53-vmx53.imxcfg
FILE_barebox-freescale-imx53-vmx53.img = start_imx53_vmx53.pblx.imximg
image-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += barebox-freescale-imx53-vmx53.img
# ----------------------- i.MX6 based boards ---------------------------
pblx-$(CONFIG_MACH_REALQ7) += start_imx6_realq7
CFG_start_imx6_realq7.pblx.imximg = $(board)/dmo-mx6-realq7/flash-header.imxcfg
@ -66,3 +71,13 @@ pblx-$(CONFIG_MACH_DFI_FS700_M60) += start_imx6q_dfi_fs700_m60_6q
CFG_start_imx6q_dfi_fs700_m60_6q.pblx.imximg = $(board)/dfi-fs700-m60/flash-header-fs700-m60-6q.imxcfg
FILE_barebox-dfi-fs700-m60-6q.img = start_imx6q_dfi_fs700_m60_6q.pblx.imximg
image-$(CONFIG_MACH_DFI_FS700_M60) += barebox-dfi-fs700-m60-6q.img
pblx-$(CONFIG_MACH_SABRELITE) += start_imx6_sabrelite
CFG_start_imx6_sabrelite.pblx.imximg = $(board)/freescale-mx6-sabrelite/flash-header-mx6-sabrelite.imxcfg
FILE_barebox-freescale-imx6q-sabrelite.img = start_imx6_sabrelite.pblx.imximg
image-$(CONFIG_MACH_SABRELITE) += barebox-freescale-imx6q-sabrelite.img
pblx-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += start_imx6dl_cubox_i_carrier_1
CFG_start_imx6dl_cubox_i_carrier_1.pblx.imximg = $(board)/solidrun-carrier-1/flash-header-solidrun-carrier-1.imxcfg
FILE_barebox-cubox-i-carrier-1.img = start_imx6dl_cubox_i_carrier_1.pblx.imximg
image-$(CONFIG_MACH_SOLIDRUN_CARRIER1) += barebox-cubox-i-carrier-1.img

6
include/of_gpio.h
View File

@ -21,11 +21,11 @@ enum of_gpio_flags {
OF_GPIO_ACTIVE_LOW = 0x1,
};
#ifdef CONFIG_OFTREE
#ifdef CONFIG_OF_GPIO
extern int of_get_named_gpio_flags(struct device_node *np,
const char *list_name, int index, enum of_gpio_flags *flags);
#else /* CONFIG_OFTREE */
#else /* CONFIG_OF_GPIO */
static inline int of_get_named_gpio_flags(struct device_node *np,
const char *list_name, int index, enum of_gpio_flags *flags)
@ -33,7 +33,7 @@ static inline int of_get_named_gpio_flags(struct device_node *np,
return -ENOSYS;
}
#endif /* CONFIG_OFTREE */
#endif /* CONFIG_OF_GPIO */
static inline int of_get_named_gpio(struct device_node *np,
const char *list_name, int index)

1
scripts/imx/imx-image.c
View File

@ -442,6 +442,7 @@ struct soc_type {
};
static struct soc_type socs[] = {
{ .name = "imx25", .header_version = 1, },
{ .name = "imx35", .header_version = 1, },
{ .name = "imx51", .header_version = 1, },
{ .name = "imx53", .header_version = 2, },

7
scripts/imx/imx-usb-loader.c
View File

@ -124,6 +124,13 @@ struct mach_id imx_ids[] = {
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
}, {
.vid = 0x15a2,
.pid = 0x003a,
.name = "i.MX25",
.header_type = HDR_MX51,
.mode = MODE_BULK,
.max_transfer = 64,
},
};