remove s3c24x0 specific stuff from arm start file, add
arch_init_lowlevel for this stuff instead.
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a99e03c847
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@ -119,48 +119,35 @@ reset:
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orr r0,r0,#0xd3
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msr cpsr,r0
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/* turn off the watchdog */
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#if defined(CONFIG_S3C2400)
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# define pWTCON 0x15300000
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# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
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# define CLKDIVN 0x14800014 /* clock divisor register */
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#elif defined(CONFIG_S3C2410)
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# define pWTCON 0x53000000
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# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
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# define INTSUBMSK 0x4A00001C
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# define CLKDIVN 0x4C000014 /* clock divisor register */
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#ifdef ARCH_HAS_INIT_LOWLEVEL
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/* Samsung S3C24x0 needs some stuff here */
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bl arch_init_lowlevel
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#endif
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#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
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ldr r0, =pWTCON
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mov r1, #0x0
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str r1, [r0]
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/*
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* mask all IRQs by setting all bits in the INTMR - default
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* flush v4 I/D caches
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*/
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mov r1, #0xffffffff
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ldr r0, =INTMSK
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str r1, [r0]
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# if defined(CONFIG_S3C2410)
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ldr r1, =0x3ff
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ldr r0, =INTSUBMSK
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str r1, [r0]
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# endif
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/* FCLK:HCLK:PCLK = 1:2:4 */
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/* default FCLK is 120 MHz ! */
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ldr r0, =CLKDIVN
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mov r1, #3
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str r1, [r0]
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#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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bl board_init_lowlevel
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#endif
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#ifndef CONFIG_SKIP_RELOCATE_UBOOT
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@ -204,48 +191,6 @@ clbss_l:str r2, [r0] /* clear loop... */
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_start_armboot: .word start_uboot
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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mov ip, lr
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bl lowlevel_init
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mov lr, ip
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mov pc, lr
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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/*
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*************************************************************************
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*
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