remove s3c24x0 specific stuff from arm start file, add
arch_init_lowlevel for this stuff instead.
This commit is contained in:
parent
a99e03c847
commit
0d26cc5df1
|
@ -119,48 +119,35 @@ reset:
|
||||||
orr r0,r0,#0xd3
|
orr r0,r0,#0xd3
|
||||||
msr cpsr,r0
|
msr cpsr,r0
|
||||||
|
|
||||||
/* turn off the watchdog */
|
#ifdef ARCH_HAS_INIT_LOWLEVEL
|
||||||
#if defined(CONFIG_S3C2400)
|
/* Samsung S3C24x0 needs some stuff here */
|
||||||
# define pWTCON 0x15300000
|
bl arch_init_lowlevel
|
||||||
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
|
|
||||||
# define CLKDIVN 0x14800014 /* clock divisor register */
|
|
||||||
#elif defined(CONFIG_S3C2410)
|
|
||||||
# define pWTCON 0x53000000
|
|
||||||
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
|
|
||||||
# define INTSUBMSK 0x4A00001C
|
|
||||||
# define CLKDIVN 0x4C000014 /* clock divisor register */
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
|
|
||||||
ldr r0, =pWTCON
|
|
||||||
mov r1, #0x0
|
|
||||||
str r1, [r0]
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* mask all IRQs by setting all bits in the INTMR - default
|
* flush v4 I/D caches
|
||||||
*/
|
*/
|
||||||
mov r1, #0xffffffff
|
mov r0, #0
|
||||||
ldr r0, =INTMSK
|
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
||||||
str r1, [r0]
|
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
||||||
# if defined(CONFIG_S3C2410)
|
|
||||||
ldr r1, =0x3ff
|
|
||||||
ldr r0, =INTSUBMSK
|
|
||||||
str r1, [r0]
|
|
||||||
# endif
|
|
||||||
|
|
||||||
/* FCLK:HCLK:PCLK = 1:2:4 */
|
|
||||||
/* default FCLK is 120 MHz ! */
|
|
||||||
ldr r0, =CLKDIVN
|
|
||||||
mov r1, #3
|
|
||||||
str r1, [r0]
|
|
||||||
#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* we do sys-critical inits only at reboot,
|
* disable MMU stuff and caches
|
||||||
* not when booting from ram!
|
*/
|
||||||
|
mrc p15, 0, r0, c1, c0, 0
|
||||||
|
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
|
||||||
|
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
|
||||||
|
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
|
||||||
|
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
|
||||||
|
mcr p15, 0, r0, c1, c0, 0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* before relocating, we have to setup RAM timing
|
||||||
|
* because memory timing is board-dependend, you will
|
||||||
|
* find a lowlevel_init.S in your board directory.
|
||||||
*/
|
*/
|
||||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
bl cpu_init_crit
|
bl board_init_lowlevel
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
|
||||||
|
@ -204,48 +191,6 @@ clbss_l:str r2, [r0] /* clear loop... */
|
||||||
|
|
||||||
_start_armboot: .word start_uboot
|
_start_armboot: .word start_uboot
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
*************************************************************************
|
|
||||||
*
|
|
||||||
* CPU_init_critical registers
|
|
||||||
*
|
|
||||||
* setup important registers
|
|
||||||
* setup memory timing
|
|
||||||
*
|
|
||||||
*************************************************************************
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
|
||||||
cpu_init_crit:
|
|
||||||
/*
|
|
||||||
* flush v4 I/D caches
|
|
||||||
*/
|
|
||||||
mov r0, #0
|
|
||||||
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
|
||||||
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* disable MMU stuff and caches
|
|
||||||
*/
|
|
||||||
mrc p15, 0, r0, c1, c0, 0
|
|
||||||
bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
|
|
||||||
bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
|
|
||||||
orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
|
|
||||||
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
|
|
||||||
mcr p15, 0, r0, c1, c0, 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* before relocating, we have to setup RAM timing
|
|
||||||
* because memory timing is board-dependend, you will
|
|
||||||
* find a lowlevel_init.S in your board directory.
|
|
||||||
*/
|
|
||||||
mov ip, lr
|
|
||||||
bl lowlevel_init
|
|
||||||
mov lr, ip
|
|
||||||
mov pc, lr
|
|
||||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*************************************************************************
|
*************************************************************************
|
||||||
*
|
*
|
||||||
|
|
Loading…
Reference in New Issue