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Merge branch 'for-next/at91' 

Conflicts:
	arch/arm/boards/at91rm9200ek/init.c
	arch/arm/boards/pm9263/init.c
	arch/arm/configs/at91sam9n12ek_defconfig
	arch/arm/mach-at91/Kconfig
This commit is contained in:
Sascha Hauer 2013-02-04 15:48:43 +01:00
parent ec2bfe6953 ab5418b570
commit 1b575024f6
165 changed files with 8853 additions and 647 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/Makefile
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@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_TEGRA) := tegra
# by CONFIG_* macro name.
board-$(CONFIG_MACH_A9M2410) := a9m2410
board-$(CONFIG_MACH_A9M2440) := a9m2440
board-$(CONFIG_MACH_ANIMEO_IP) := animeo_ip
board-$(CONFIG_MACH_AT91RM9200EK) := at91rm9200ek
board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek
board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek
@ -77,7 +78,9 @@ board-$(CONFIG_MACH_AT91SAM9G10EK) := at91sam9261ek
board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek
board-$(CONFIG_MACH_AT91SAM9N12EK) := at91sam9n12ek
board-$(CONFIG_MACH_AT91SAM9X5EK) := at91sam9x5ek
board-$(CONFIG_MACH_AT91SAM9M10IHD) := at91sam9m10ihd
board-$(CONFIG_MACH_AT91SAM9M10G45EK) := at91sam9m10g45ek
board-$(CONFIG_MACH_SAMA5D3XEK) := sama5d3xek
board-$(CONFIG_MACH_CLEP7212) := clep7212
board-$(CONFIG_MACH_DSS11) := dss11
board-$(CONFIG_MACH_EDB9301) := edb93xx
@ -94,6 +97,7 @@ board-$(CONFIG_MACH_EUKREA_CPUIMX35) := eukrea_cpuimx35
board-$(CONFIG_MACH_EUKREA_CPUIMX51SD) := eukrea_cpuimx51
board-$(CONFIG_MACH_FREESCALE_MX25_3STACK) := freescale-mx25-3-stack
board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
board-$(CONFIG_MACH_GE863) := telit-evk-pro3
board-$(CONFIG_MACH_IMX21ADS) := imx21ads
board-$(CONFIG_MACH_IMX27ADS) := imx27ads
board-$(CONFIG_MACH_IMX233_OLINUXINO) := imx233-olinuxino

1
arch/arm/boards/animeo_ip/Makefile Normal file
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@ -0,0 +1 @@
obj-y += init.o

6
arch/arm/boards/animeo_ip/config.h Normal file
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@ -0,0 +1,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#endif /* __CONFIG_H */

39
arch/arm/boards/animeo_ip/env/config vendored Normal file
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@ -0,0 +1,39 @@
#!/bin/sh
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp-barebox
global.dhcp.vendor_id=barebox-animeo-ip
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp', 'nor' or 'nand'
kernel_loc=nfs
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'nfs', 'tftp', 'nor', 'nand' or empty
oftree_loc=nfs
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root.$rootfs_type
kernelimage=zImage
#kernelimage=uImage
#kernelimage=Image
#kernelimage=Image.lzo
nand_device=atmel_nand
nand_parts="32k(at91bootstrap),256k(barebox)ro,32k(bareboxenv),704k(user_block),1728k(kernel),-(root)"
rootfs_mtdblock_nand=5
autoboot_timeout=3
bootargs="console=ttyS1,38400n8 earlyprintk"
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# "

251
arch/arm/boards/animeo_ip/init.c Normal file
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@ -0,0 +1,251 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Under GPLv2 only
*/
#include <common.h>
#include <net.h>
#include <init.h>
#include <environment.h>
#include <fec.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
#include <io.h>
#include <asm/hardware.h>
#include <nand.h>
#include <sizes.h>
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
static bool animeo_ip_is_buco;
static bool animeo_ip_is_io;
static int animeo_ip_get_pio_revision(int gpio, char *name)
{
int ret;
ret = gpio_request(gpio, name);
if (ret) {
pr_err("animeo_ip: can not request gpio %d as %s (%d)\n",
gpio, name, ret);
return ret;
}
ret = gpio_direction_input(gpio);
if (ret) {
pr_err("animeo_ip: can configure gpio %d (%s) as input (%d)\n",
gpio, name, ret);
return ret;
}
return gpio_get_value(gpio);
}
static void animeo_ip_detect_version(void)
{
struct device_d *dev = NULL;
char *model, *version;
int val;
animeo_ip_is_io = false;
animeo_ip_is_buco = false;
model = "SubCo";
version = "SDN";
dev = add_generic_device_res("animeo_ip", DEVICE_ID_SINGLE, NULL, 0, NULL);
val = animeo_ip_get_pio_revision(AT91_PIN_PC20, "is_buco");
if (val < 0) {
pr_warn("Can not detect model use %s by default\n", model);
} else if (val) {
animeo_ip_is_buco = true;
model = "SubCo";
}
val = animeo_ip_get_pio_revision(AT91_PIN_PC21, "is_io");
if (val < 0) {
pr_warn("Can not detect version use %s by default\n", model);
} else if (val) {
animeo_ip_is_io = true;
version = "IO";
}
dev_add_param_fixed(dev, "model", model);
dev_add_param_fixed(dev, "version", version);
}
static struct atmel_nand_data nand_pdata = {
.ale = 21,
.cle = 22,
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.bus_width_16 = 0,
.on_flash_bbt = 1,
};
static struct sam9_smc_config animeo_ip_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 1,
.ncs_write_setup = 0,
.nwe_setup = 1,
.ncs_read_pulse = 3,
.nrd_pulse = 3,
.ncs_write_pulse = 3,
.nwe_pulse = 3,
.read_cycle = 5,
.write_cycle = 5,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
.tdf_cycles = 2,
};
static void animeo_ip_add_device_nand(void)
{
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &animeo_ip_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
static struct at91_ether_platform_data macb_pdata = {
.phy_addr = 0,
};
/*
* MCI (SD/MMC)
*/
#if defined(CONFIG_MCI_ATMEL)
static struct atmel_mci_platform_data __initdata animeo_ip_mci_data = {
.bus_width = 4,
.slot_b = 1,
.detect_pin = -EINVAL,
.wp_pin = -EINVAL,
};
static void animeo_ip_add_device_mci(void)
{
at91_add_device_mci(0, &animeo_ip_mci_data);
}
#else
static void animeo_ip_add_device_mci(void) {}
#endif
struct gpio_bicolor_led leds[] = {
{
.gpio_c0 = AT91_PIN_PC17,
.gpio_c1 = AT91_PIN_PA2,
.led = {
.name = "power_red_green",
},
}, {
.gpio_c0 = AT91_PIN_PC19,
.gpio_c1 = AT91_PIN_PC18,
.led = {
.name = "tx_greem_rx_yellow",
},
},
};
static void __init animeo_ip_add_device_led(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(leds); i++) {
at91_set_gpio_output(leds[i].gpio_c0, leds[i].active_low);
at91_set_gpio_output(leds[i].gpio_c1, leds[i].active_low);
led_gpio_bicolor_register(&leds[i]);
}
led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
}
static int animeo_ip_mem_init(void)
{
at91_add_device_sdram(0);
return 0;
}
mem_initcall(animeo_ip_mem_init);
static void animeo_export_gpio_in(int gpio, const char *name)
{
at91_set_gpio_input(gpio, 0);
at91_set_deglitch(gpio, 1);
export_env_ull(name, gpio);
}
static void animeo_ip_add_device_buttons(void)
{
animeo_export_gpio_in(AT91_PIN_PB1, "keyswitch_in");
animeo_export_gpio_in(AT91_PIN_PB2, "error_in");
animeo_export_gpio_in(AT91_PIN_PC22, "jumper");
animeo_export_gpio_in(AT91_PIN_PC23, "btn");
}
static void animeo_export_gpio_out(int gpio, const char *name)
{
at91_set_gpio_output(gpio, 0);
export_env_ull(name, gpio);
}
static void animeo_ip_power_control(void)
{
animeo_export_gpio_out(AT91_PIN_PB0, "power_radio");
animeo_export_gpio_out(AT91_PIN_PB3, "error_out_relay");
animeo_export_gpio_out(AT91_PIN_PC4, "power_save");
}
static int animeo_ip_devices_init(void)
{
animeo_ip_detect_version();
animeo_ip_power_control();
animeo_ip_add_device_nand();
at91_add_device_eth(0, &macb_pdata);
animeo_ip_add_device_mci();
animeo_ip_add_device_buttons();
animeo_ip_add_device_led();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
/*
* in production the machine id used is the cpu module machine id
* PICOCOM1
*/
armlinux_set_architecture(MACH_TYPE_PICOCOM1);
devfs_add_partition("nand0", 0x00000, SZ_32K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_32K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_32K, SZ_32K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
return 0;
}
device_initcall(animeo_ip_devices_init);
static int animeo_ip_console_init(void)
{
/*
* disable the dbgu enable by the bootstrap
* so linux can detect that we only enable the uart2
* and use it for decompress
*/
#define ATMEL_US_BRGR 0x0020
at91_sys_write(AT91_DBGU + ATMEL_US_BRGR, 0);
at91_register_uart(3, 0);
return 0;
}
console_initcall(animeo_ip_console_init);

4
arch/arm/boards/at91rm9200ek/init.c
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@ -33,13 +33,13 @@
#include <spi/spi.h>
static struct at91_ether_platform_data ether_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
static int at91rm9200ek_mem_init(void)
{
at91_add_device_sdram(32 * 1024 * 1024);
at91_add_device_sdram(0);
return 0;
}

2
arch/arm/boards/at91sam9260ek/init.c
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@ -127,7 +127,7 @@ static void ek_add_device_nand(void)
}
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};

4
arch/arm/boards/at91sam9261ek/Makefile
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@ -1 +1,5 @@
obj-y += init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o

7
arch/arm/boards/at91sam9261ek/env/bin/init_board vendored
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@ -1,5 +1,12 @@
#!/bin/sh
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi
button_name="dfu_bp"
button_wait=5

10
arch/arm/boards/at91sam9261ek/env/config vendored
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@ -34,8 +34,14 @@ kernelimage=zImage
#kernelimage=Image.lzo
nand_device=atmel_nand
nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
rootfs_mtdblock_nand=6
if [ x$borebox_first_stage = x1 ]
then
nand_parts="384k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
rootfs_mtdblock_nand=5
else
nand_parts="128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),128k(oftree),4M(kernel),120M(rootfs),-(data)"
rootfs_mtdblock_nand=6
fi
autoboot_timeout=3

140
arch/arm/boards/at91sam9261ek/init.c
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@ -30,13 +30,14 @@
#include <linux/mtd/nand.h>
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <dm9000.h>
#include <gpio_keys.h>
#include <readkey.h>
#include <led.h>
#include <spi/spi.h>
static struct atmel_nand_data nand_pdata = {
.ale = 22,
@ -149,6 +150,86 @@ static void ek_add_device_udc(void)
static void ek_add_device_udc(void) {}
#endif
/*
* LCD Controller
*/
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
static int ek_gpio_request_output(int gpio, const char *name)
{
int ret;
ret = gpio_request(gpio, name);
if (ret) {
pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
return ret;
}
ret = gpio_direction_output(gpio, 1);
if (ret)
pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
return ret;
}
/* TFT */
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "TX09D50VM1CCA @ 60",
.refresh = 60,
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
.left_margin = 1, .right_margin = 33,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
};
#define AT91SAM9261_DEFAULT_TFT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
static void at91_lcdc_tft_power_control(int on)
{
if (on)
gpio_set_value(AT91_PIN_PA12, 0); /* power up */
else
gpio_set_value(AT91_PIN_PA12, 1); /* power down */
}
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9261_DEFAULT_TFT_LCDCON2,
.guard_time = 1,
.atmel_lcdfb_power_control = at91_lcdc_tft_power_control,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static int at91_lcdc_gpio(void)
{
return ek_gpio_request_output(AT91_PIN_PA12, "lcdc_tft_power");
}
static void ek_add_device_lcdc(void)
{
if (at91_lcdc_gpio())
return;
if (machine_is_at91sam9g10ek())
ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcdc(void) {}
#endif
#ifdef CONFIG_KEYBOARD_GPIO
struct gpio_keys_button keys[] = {
{
@ -229,6 +310,46 @@ static void ek_device_add_leds(void)
static void ek_device_add_leds(void) {}
#endif
/*
* SPI related devices
*/
#if defined(CONFIG_DRIVER_SPI_ATMEL)
/*
* SPI devices
*/
static struct spi_board_info ek_spi_devices[] = {
{ /* DataFlash chip */
.name = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
{ /* DataFlash card - jumper (J12) configurable to CS3 or CS0 */
.name = "mtd_dataflash",
.chip_select = 1,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#endif
};
static unsigned spi0_standard_cs[] = { AT91_PIN_PA3, AT91_PIN_PA6};
static struct at91_spi_platform_data spi_pdata = {
.chipselect = spi0_standard_cs,
.num_chipselect = ARRAY_SIZE(spi0_standard_cs),
};
static void ek_add_device_spi(void)
{
spi_register_board_info(ek_spi_devices,
ARRAY_SIZE(ek_spi_devices));
at91_add_device_spi(0, &spi_pdata);
}
#else
static void ek_add_device_spi(void) {}
#endif
static int at91sam9261ek_mem_init(void)
{
at91_add_device_sdram(0);
@ -239,15 +360,28 @@ mem_initcall(at91sam9261ek_mem_init);
static int at91sam9261ek_devices_init(void)
{
u32 barebox_part_start;
u32 barebox_part_size;
ek_add_device_nand();
ek_add_device_dm9000();
ek_add_device_udc();
ek_add_device_buttons();
ek_device_add_leds();
ek_add_device_lcdc();
ek_add_device_spi();
devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
if (IS_ENABLED(CONFIG_AT91_LOAD_BAREBOX_SRAM)) {
barebox_part_start = 0;
barebox_part_size = SZ_256K + SZ_128K;
export_env_ull("borebox_first_stage", 1);
} else {
devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
barebox_part_start = SZ_128K;
barebox_part_size = SZ_256K;
}
devfs_add_partition("nand0", barebox_part_start, barebox_part_size,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");

108
arch/arm/boards/at91sam9261ek/lowlevel_init.c Normal file
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@ -0,0 +1,108 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_CLOCK 200
#if MASTER_CLOCK == 200
#define MASTER_PLL_MUL 162
#define MASTER_PLL_DIV 15
#elif MASTER_CLOCK == 239
#define MASTER_PLL_MUL 13
#define MASTER_PLL_DIV 1
#endif
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_8 |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_TDF_(2);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3);
cfg->smc_setup =
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0);
cfg->pmc_mor =
AT91_PMC_MOSCEN |
(255 << 8); /* Main Oscillator Start-up Time */
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_OUT |
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x13C;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NC_9 |
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_2 |
AT91_SDRAMC_DBW_32 |
(2 << 8) | /* Write Recovery Delay */
(7 << 12) | /* Row Cycle Delay */
(2 << 16) | /* Row Precharge Delay */
(2 << 20) | /* Row to Column Delay */
(5 << 24) | /* Active to Precharge Delay */
(8 << 28); /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = (MASTER_CLOCK * 7);
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

4
arch/arm/boards/at91sam9263ek/Makefile
View File

@ -1 +1,5 @@
obj-y += init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o

87
arch/arm/boards/at91sam9263ek/config.h
View File

@ -3,91 +3,4 @@
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define MASTER_PLL_MUL 171
#define MASTER_PLL_DIV 14
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
AT91_PMC_OUT | \
AT91_PMC_PLLCOUNT | /* PLL Counter */ \
(2 << 28) | /* PLL Clock Frequency Range */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
AT91_MATRIX_EBI0_CS1A_SDRAMC)
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
AT91_SDRAMC_CAS_3 | \
AT91_SDRAMC_DBW_32 | \
(1 << 8) | /* Write Recovery Delay */ \
(7 << 12) | /* Row Cycle Delay */ \
(2 << 16) | /* Row Precharge Delay */ \
(2 << 20) | /* Row to Column Delay */ \
(5 << 24) | /* Active to Precharge Delay */ \
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC_CS 0
#define CONFIG_SYS_SMC_SETUP_VAL \
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
#define CONFIG_SYS_SMC_PULSE_VAL \
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
#define CONFIG_SYS_SMC_CYCLE_VAL \
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
#define CONFIG_SYS_SMC_MODE_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_PROCRST | \
AT91_RSTC_RSTTYP_WAKEUP | \
AT91_RSTC_RSTTYP_WATCHDOG)
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
AT91_WDT_WDV | \
AT91_WDT_WDDIS | \
AT91_WDT_WDD)
#endif /* __CONFIG_H */

7
arch/arm/boards/at91sam9263ek/env/bin/init_board vendored
View File

@ -1,5 +1,12 @@
#!/bin/sh
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi
button_name="dfu_bp"
button_wait=5

74
arch/arm/boards/at91sam9263ek/init.c
View File

@ -32,7 +32,7 @@
#include <linux/mtd/nand.h>
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
@ -83,7 +83,7 @@ static void ek_add_device_nand(void)
}
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
@ -149,6 +149,75 @@ static void ek_add_device_udc(void)
static void ek_add_device_udc(void) {}
#endif
/*
* LCD Controller
*/
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
static int ek_gpio_request_output(int gpio, const char *name)
{
int ret;
ret = gpio_request(gpio, name);
if (ret) {
pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
return ret;
}
ret = gpio_direction_output(gpio, 1);
if (ret)
pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
return ret;
}
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "TX09D50VM1CCA @ 60",
.refresh = 60,
.xres = 240, .yres = 320,
.pixclock = KHZ2PICOS(4965),
.left_margin = 1, .right_margin = 33,
.upper_margin = 1, .lower_margin = 0,
.hsync_len = 5, .vsync_len = 1,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
},
};
#define AT91SAM9263_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
static void at91_lcdc_power_control(int on)
{
gpio_set_value(AT91_PIN_PA30, on);
}
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9263_DEFAULT_LCDCON2,
.guard_time = 1,
.atmel_lcdfb_power_control = at91_lcdc_power_control,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
if (ek_gpio_request_output(AT91_PIN_PA30, "lcdc_power"))
return;
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcdc(void) {}
#endif
static void __init ek_add_device_buttons(void)
{
at91_set_gpio_input(AT91_PIN_PC5, 1);
@ -184,6 +253,7 @@ static int at91sam9263ek_devices_init(void)
ek_device_add_leds();
ek_add_device_udc();
ek_add_device_buttons();
ek_add_device_lcdc();
if (IS_ENABLED(CONFIG_DRIVER_CFI) && cdev_by_name("nor0")) {
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self");

104
arch/arm/boards/at91sam9263ek/lowlevel_init.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_PLL_MUL 171
#define MASTER_PLL_DIV 14
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
AT91_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_16 |
AT91_SMC_TDFMODE |
AT91_SMC_TDF_(6);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
cfg->smc_setup =
AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
cfg->pmc_mor =
AT91_PMC_MOSCEN |
(255 << 8); /* Main Oscillator Start-up Time */
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_OUT |
AT91_PMC_PLLCOUNT | /* PLL Counter */
(2 << 28) | /* PLL Clock Frequency Range */
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x13C;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NC_9 |
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_3 |
AT91_SDRAMC_DBW_32 |
(1 << 8) | /* Write Recovery Delay */
(7 << 12) | /* Row Cycle Delay */
(2 << 16) | /* Row Precharge Delay */
(2 << 20) | /* Row to Column Delay */
(5 << 24) | /* Active to Precharge Delay */
(1 << 28); /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = 1200;
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

7
arch/arm/boards/at91sam9m10g45ek/env/bin/boot_board vendored
View File

@ -5,6 +5,13 @@ export PATH
. /env/config
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi
menu -r -m boot
menu -a -m boot -d "\e[1;36mWelcome on Barebox Boot Sequence\e[0m"
menu -e -a -m boot -c 'menu_boot' -d "boot (default) "

67
arch/arm/boards/at91sam9m10g45ek/init.c
View File

@ -106,7 +106,7 @@ static void ek_add_device_nand(void)
}
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
@ -208,21 +208,84 @@ static void ek_device_add_keyboard(void)
static void ek_device_add_keyboard(void) {}
#endif
#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI)
/*
* USB HS Host port (common to OHCI & EHCI)
*/
static struct at91_usbh_data ek_usbh_hs_data = {
.ports = 2,
.vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3},
.vbus_pin_active_low = {1, 1},
};
static void ek_add_device_usb(void)
{
at91_add_device_usbh_ohci(&ek_usbh_hs_data);
at91_add_device_usbh_ehci(&ek_usbh_hs_data);
}
#else
static void ek_add_device_usb(void) {}
#endif
static int at91sam9m10g45ek_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_sdram(0);
return 0;
}
mem_initcall(at91sam9m10g45ek_mem_init);
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "LG",
.refresh = 60,
.xres = 480, .yres = 272,
.pixclock = KHZ2PICOS(9000),
.left_margin = 1, .right_margin = 1,
.upper_margin = 40, .lower_margin = 1,
.hsync_len = 45, .vsync_len = 1,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 32,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcdc(void) {}
#endif
static int at91sam9m10g45ek_devices_init(void)
{
ek_add_device_nand();
at91_add_device_eth(0, &macb_pdata);
ek_add_device_mci();
ek_add_device_usb();
ek_device_add_leds();
ek_device_add_keyboard();
ek_add_device_lcdc();
devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");

2
arch/arm/boards/at91sam9m10ihd/Makefile Normal file
View File

@ -0,0 +1,2 @@
obj-y += init.o
obj-y += hw_version.o

6
arch/arm/boards/at91sam9m10ihd/config.h Normal file
View File

@ -0,0 +1,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#endif /* __CONFIG_H */

11
arch/arm/boards/at91sam9m10ihd/env/boot/android vendored Normal file
View File

@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "android (nand)"
exit
fi
global.bootm.image="/dev/nand0.kernel.bb"
global.linux.bootargs.dyn.root="root=/dev/mtdblock1 rootfstype=jffs2 rw init=/init rootdelay=1"
# clean the mtdparts otherwise android does not boot
global -r linux.mtdparts.

19
arch/arm/boards/at91sam9m10ihd/env/boot/mmc vendored Normal file
View File

@ -0,0 +1,19 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "MMC slot"
exit
fi
path="/mnt/mmc"
global.bootm.image="${path}/zimage"
oftree=${path}/oftree
if [ -f $oftree ]; then
global.bootm.oftree="$oftree"
fi
# The rootdevice may actually be mmcblk1p2 if a card
# is inserted to the back MMC slot
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2"

16
arch/arm/boards/at91sam9m10ihd/env/boot/net vendored Normal file
View File

@ -0,0 +1,16 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "network (tftp, nfs) (macb)"
exit
fi
ethact eth0
path="/mnt/tftp"
global.bootm.image="${path}/${global.user}-linux-${global.hostname}"
#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}"
nfsroot="/home/${global.user}/nfsroot/${global.hostname}"
bootargs-ip
global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp"

22
arch/arm/boards/at91sam9m10ihd/env/boot/net-usb vendored Normal file
View File

@ -0,0 +1,22 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "network (tftp, nfs) (usb ethernet)"
exit
fi
usb -f
ethact eth1
if [ $? -ne 0 ]; then
echo "ERROR: usb ethernet not found"
exit 1
fi
path="/mnt/tftp"
global.bootm.image="${path}/${global.user}-linux-${global.hostname}"
#global.bootm.oftree="${path}/${global.user}-oftree-${global.hostname}"
nfsroot="/home/${global.user}/nfsroot/${global.hostname}"
bootargs-ip
global.linux.bootargs.dyn.root="root=/dev/nfs nfsroot=$nfsroot,v3,tcp"

21
arch/arm/boards/at91sam9m10ihd/env/config vendored Normal file
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@ -0,0 +1,21 @@
#!/bin/sh
# change network settings in /env/network/eth0
# change mtd partition settings and automountpoints in /env/init/*
#global.hostname=
# set to false if you do not want to have colors
global.allow_color=true
# user (used for network filenames)
global.user=none
# timeout in seconds before the default boot entry is started
global.autoboot_timeout=3
# default boot entry (one of /env/boot/*)
global.boot.default=android
# base bootargs
#global.linux.bootargs.base="console=ttyS0,115200"

17
arch/arm/boards/at91sam9m10ihd/env/init/automount vendored Normal file
View File

@ -0,0 +1,17 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "Automountpoints"
exit
fi
# automount tftp server based on $eth0.serverip
mkdir -p /mnt/tftp
automount /mnt/tftp 'ifup eth0 && mount -t tftp $eth0.serverip /mnt/tftp'
# automount nfs server example
# SD card slot, first partition
mkdir -p /mnt/mmc
automount -d /mnt/mmc 'mount /dev/disk0.0 /mnt/mmc'

8
arch/arm/boards/at91sam9m10ihd/env/init/config-board vendored Normal file
View File

@ -0,0 +1,8 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=at91sam9m10ihd
global.linux.bootargs.base="console=ttyS0,115200"
global.boot.default=android

11
arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-001-nand vendored Normal file
View File

@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "NAND partitions"
exit
fi
mtdparts="128k(nand0.at91bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),128k(nand0.bareboxenv2),128k(nand0.oftree),1280k(nand0.free),3M(nand0.kernel),195M(nand0.rootfs),300M(nand0.userdata),-(nand0.cache)"
kernelname="atmel_nand"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}

11
arch/arm/boards/at91sam9m10ihd/env/init/mtdparts-002-m25p80 vendored Normal file
View File

@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "SPI NOR partitions"
exit
fi
mtdparts="32k(m25p0.at91bootstrap)ro,256k(m25p0.barebox),128k(m25p0.bareboxenv),128k(m25p0.bareboxenv2),128k(m25p0.oftree),-(m25p0.kernel)"
kernelname="m25p0"
mtdparts-add -d m25p0 -k ${kernelname} -p ${mtdparts}

9
arch/arm/boards/at91sam9m10ihd/env/init/ps1 vendored Normal file
View File

@ -0,0 +1,9 @@
#!/bin/sh
/env/config
if [ ${global.allow_color} = "true" ]; then
export PS1="\e[1;32mbarebox@\e[1;36m\h:\w\e[0m\n# "
else
export PS1="barebox@\h:\w\n# "
fi

8
arch/arm/boards/at91sam9m10ihd/env/init/splash vendored Normal file
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@ -0,0 +1,8 @@
#!/bin/sh
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi

216
arch/arm/boards/at91sam9m10ihd/hw_version.c Normal file
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@ -0,0 +1,216 @@
/*
* Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <common.h>
#include <fs.h>
#include <fcntl.h>
#include <libbb.h>
#include <asm/armlinux.h>
#include <of.h>
#include <libfdt.h>
#include "hw_version.h"
enum board_type {
BOARD_TYPE_DB,
BOARD_TYPE_CPU,
};
static struct board_info {
char *name;
enum board_type type;
unsigned char id;
} board_list[] = {
{"SAM9M10-CM", BOARD_TYPE_CPU, 0},
{"IHD-DB-9M10", BOARD_TYPE_DB, 1},
};
static struct board_info* get_board_info_by_name(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(board_list); i++)
if (strcmp(name, board_list[i].name) == 0)
return &board_list[i];
return NULL;
}
static struct vendor_info {
char *name;
enum vendor_id id;
} vendor_list[] = {
{"ATMEL_SH", VENDOR_ATMEL},
{"FLEX", VENDOR_FLEX},
};
static struct vendor_info* get_vendor_info_by_name(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(vendor_list); i++)
if (strcmp(name, vendor_list[i].name) == 0)
return &vendor_list[i];
return NULL;
}
#define BOARD_NAME_LEN 12
#define VENDOR_NAME_LEN 10
#define VENDOR_COUNTRY_LEN 2
struct one_wire_info {
u8 total_bytes;
u8 vendor_name[VENDOR_NAME_LEN];
u8 vendor_country[VENDOR_COUNTRY_LEN];
u8 board_name[BOARD_NAME_LEN];
u8 year;
u8 week;
u8 revision_code;
u8 revision_id;
u8 reserved;
u8 checksum_l;
u8 checksum_h;
}__attribute__ ((packed));
static int at91sam9m10ihd_read_w1(const char *file, struct one_wire_info *info)
{
int fd;
int ret;
fd = open(file, O_RDONLY);
if (fd < 0) {
ret = fd;
goto err;
}
ret = read_full(fd, info, sizeof(*info));
if (ret < 0)
goto err_open;
if (ret < sizeof(*info)) {
ret = -EINVAL;
goto err_open;
}
pr_debug("total_bytes = %d\n", info->total_bytes);
pr_debug("vendor_name = %s\n", info->vendor_name);
pr_debug("vendor_country = %.2s\n", info->vendor_country);
pr_debug("board_name = %s\n", info->board_name);
pr_debug("year = %d\n", info->year);
pr_debug("week = %d\n", info->week);
pr_debug("revision_code = %x\n", info->revision_code);
pr_debug("revision_id = %x\n", info->revision_id);
pr_debug("reserved = %x\n", info->reserved);
pr_debug("checksum_l = %x\n", info->checksum_l);
pr_debug("checksum_h = %x\n", info->checksum_h);
ret = 0;
err_open:
close(fd);
err:
if (ret)
pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret));
return ret;
}
static u32 sn = 0;
static u32 rev = 0;
bool at91sam9m10ihd_cm_is_vendor(enum vendor_id vid)
{
return ((sn >> 5) & 0x1f) == vid;
}
bool at91sam9m10ihd_db_is_vendor(enum vendor_id vid)
{
return ((sn >> 15) & 0x1f) == vid;
}
static void at91sam9m10ihd_devices_detect_one(const char *name)
{
struct one_wire_info info;
struct board_info* binfo;
struct vendor_info* vinfo;
struct device_d *dev = NULL;
char str[16];
u8 vendor_id = 0;
if (at91sam9m10ihd_read_w1(name, &info))
return;
binfo = get_board_info_by_name(info.board_name);
if (!binfo) {
pr_err("board %s no supported\n", info.board_name);
return;
}
vinfo = get_vendor_info_by_name(info.vendor_name);
if (vinfo)
vendor_id = vinfo->id;
switch (binfo->type) {
case BOARD_TYPE_CPU:
dev = add_generic_device_res("at91sam9m10ihd", DEVICE_ID_SINGLE, NULL, 0, NULL);
if (!dev)
return;
sn |= (binfo->id & 0x1f);
sn |= ((vendor_id & 0x1f) << 5);
rev |= (info.revision_code - 'A');
rev |= (((info.revision_id - '0') & 0x3) << 15);
pr_info("CM");
break;
case BOARD_TYPE_DB:
dev = add_generic_device_res("at91sam9m10ihd-db", DEVICE_ID_SINGLE, NULL, 0, NULL);
if (!dev)
return;
sn |= ((binfo->id & 0x1f) << 20);
sn |= ((vendor_id & 0x1f) << 25);
rev |= ((info.revision_code - 'A') << 10);
rev |= (((info.revision_id - '0') & 0x3) << 21);
pr_info("DB");
break;
}
pr_info(": %s [%c%c] from %s\n",
info.board_name, info.revision_code, info.revision_id,
info.vendor_name);
dev_add_param_fixed(dev, "vendor", info.vendor_name);
dev_add_param_fixed(dev, "board", info.board_name);
sprintf(str, "%.2s", info.vendor_country);
dev_add_param_fixed(dev, "country", str);
sprintf(str, "%d", info.year);
dev_add_param_fixed(dev, "year", str);
sprintf(str, "%d", info.week);
dev_add_param_fixed(dev, "week", str);
sprintf(str, "%c", info.revision_code);
dev_add_param_fixed(dev, "revision_code", str);
sprintf(str, "%c", info.revision_id);
dev_add_param_fixed(dev, "revision_id", str);
}
void at91sam9m10ihd_devices_detect_hw(void)
{
at91sam9m10ihd_devices_detect_one("/dev/ds24310");
at91sam9m10ihd_devices_detect_one("/dev/ds24330");
pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev);
armlinux_set_revision(rev);
armlinux_set_serial(sn);
}

31
arch/arm/boards/at91sam9m10ihd/hw_version.h Normal file
View File

@ -0,0 +1,31 @@
/*
* Copyright (C) 2012-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __HW_REVISION_H__
#define __HW_REVISION_H__
enum vendor_id {
VENDOR_UNKNOWN = 0,
VENDOR_ATMEL = 1,
VENDOR_FLEX = 2,
};
void at91sam9m10ihd_devices_detect_hw(void);
bool at91sam9m10ihd_cm_is_vendor(enum vendor_id vid);
bool at91sam9m10ihd_db_is_vendor(enum vendor_id vid);
#endif /* __HW_REVISION_H__ */

287
arch/arm/boards/at91sam9m10ihd/init.c Normal file
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@ -0,0 +1,287 @@
/*
* Copyright (C) 2009-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Under GPLv2 only
*/
#include <common.h>
#include <net.h>
#include <mci.h>
#include <init.h>
#include <environment.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
#include <io.h>
#include <asm/hardware.h>
#include <nand.h>
#include <sizes.h>
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <input/qt1070.h>
#include <readkey.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
#include <spi/spi.h>
#include "hw_version.h"
struct w1_gpio_platform_data w1_pdata = {
.pin = AT91_PIN_PB25,
.ext_pullup_enable_pin = -EINVAL,
.is_open_drain = 0,
};
static struct atmel_nand_data nand_pdata = {
.ale = 21,
.cle = 22,
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
.bus_width_16 = 0,
.on_flash_bbt = 1,
};
static struct sam9_smc_config ek_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 2,
.ncs_write_setup = 0,
.nwe_setup = 2,
.ncs_read_pulse = 4,
.nrd_pulse = 4,
.ncs_write_pulse = 4,
.nwe_pulse = 4,
.read_cycle = 7,
.write_cycle = 7,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
.tdf_cycles = 3,
};
static void ek_add_device_nand(void)
{
/* setup bus-width (8 or 16) */
if (nand_pdata.bus_width_16)
ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
else
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &ek_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
static struct at91_ether_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
static void ek_add_device_eth(void)
{
if (w1_local_mac_address_register(0, "tml", "w1-2d-0"))
w1_local_mac_address_register(0, "tml", "w1-23-0");
at91_add_device_eth(0, &macb_pdata);
}
#if defined(CONFIG_MCI_ATMEL)
static struct atmel_mci_platform_data ek_mci0_data = {
.bus_width = 4,
.detect_pin = AT91_PIN_PC25,
};
static void ek_add_device_mci(void)
{
at91_add_device_mci(0, &ek_mci0_data);
}
#else
static void ek_add_device_mci(void) {}
#endif
struct qt1070_platform_data qt1070_pdata = {
.irq_pin = AT91_PIN_PB19,
.code = { KEY_ENTER, KEY_ENTER, KEY_UP, KEY_DOWN, },
.nb_code = 4,
};
static struct i2c_board_info i2c_devices[] = {
{
.platform_data = &qt1070_pdata,
I2C_BOARD_INFO("qt1070", 0x1b),
}, {
I2C_BOARD_INFO("24c512", 0x51)
},
};
static void ek_add_device_i2c(void)
{
at91_set_gpio_input(qt1070_pdata.irq_pin, 0);
at91_set_deglitch(qt1070_pdata.irq_pin, 1);
at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices));
}
static const struct spi_board_info ek_spi_devices[] = {
{
.name = "m25p80",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
}
};
static unsigned spi0_standard_cs[] = { AT91_PIN_PB3 };
static struct at91_spi_platform_data spi_pdata = {
.chipselect = spi0_standard_cs,
.num_chipselect = ARRAY_SIZE(spi0_standard_cs),
};
static void ek_add_device_spi(void)
{
spi_register_board_info(ek_spi_devices,
ARRAY_SIZE(ek_spi_devices));
at91_add_device_spi(0, &spi_pdata);
}
/*
* USB HS Host port (common to OHCI & EHCI)
*/
static struct at91_usbh_data ek_usbh_hs_data = {
.ports = 1,
.vbus_pin = {AT91_PIN_PC30, -EINVAL},
.vbus_pin_active_low = {1, 0},
};
static void ek_add_device_usb(void)
{
at91_add_device_usbh_ohci(&ek_usbh_hs_data);
at91_add_device_usbh_ehci(&ek_usbh_hs_data);
}
static int at91sam9m10g45ek_mem_init(void)
{
at91_add_device_sdram(0);
return 0;
}
mem_initcall(at91sam9m10g45ek_mem_init);
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
static int ek_gpio_request_output(int gpio, const char *name)
{
int ret;
ret = gpio_request(gpio, name);
if (ret) {
pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
return ret;
}
ret = gpio_direction_output(gpio, 1);
if (ret)
pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
return ret;
}
static struct fb_videomode at91fb_default_monspecs[] = {
{
.name = "MULTEK",
.refresh = 60,
.xres = 800, .yres = 480,
.pixclock = KHZ2PICOS(15000),
.left_margin = 40, .right_margin = 40,
.upper_margin = 29, .lower_margin = 13,
.hsync_len = 48, .vsync_len = 3,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
#define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \
| ATMEL_LCDC_DISTYPE_TFT \
| ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
static void at91_lcdc_power_control(int on)
{
gpio_set_value(AT91_PIN_PE6, on);
}
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
.atmel_lcdfb_power_control = at91_lcdc_power_control,
.mode_list = at91fb_default_monspecs,
.num_modes = ARRAY_SIZE(at91fb_default_monspecs),
};
static void ek_add_device_lcd(void)
{
if (ek_gpio_request_output(AT91_PIN_PE6, "lcdc_power"))
return;
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcd(void) {}
#endif
static void ek_add_device_w1(void)
{
at91_set_gpio_input(w1_pdata.pin, 0);
at91_set_multi_drive(w1_pdata.pin, 1);
add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata);
at91sam9m10ihd_devices_detect_hw();
}
static int at91sam9m10ihd_devices_init(void)
{
ek_add_device_w1();
ek_add_device_nand();
ek_add_device_eth();
ek_add_device_mci();
ek_add_device_spi();
ek_add_device_i2c();
ek_add_device_usb();
ek_add_device_lcd();
devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_128K, SZ_256K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_256K + SZ_128K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100));
/*
* The internal Atmel kernel use the SAM9M10G45EK machine id
* The mainline use DT
*/
armlinux_set_architecture(MACH_TYPE_AT91SAM9M10G45EK);
return 0;
}
device_initcall(at91sam9m10ihd_devices_init);
static int at91sam9m10ihd_console_init(void)
{
at91_register_uart(0, 0);
return 0;
}
console_initcall(at91sam9m10ihd_console_init);

7
arch/arm/boards/at91sam9n12ek/env/bin/init_board vendored
View File

@ -1,5 +1,12 @@
#!/bin/sh
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi
button_name="dfu_bp"
button_wait=5

72
arch/arm/boards/at91sam9n12ek/init.c
View File

@ -124,6 +124,75 @@ static void __init ek_add_device_ks8851(void)
static void __init ek_add_device_ks8851(void) {}
#endif /* CONFIG_DRIVER_NET_KS8851_MLL */
#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD)
static int ek_gpio_request_output(int gpio, const char *name)
{
int ret;
ret = gpio_request(gpio, name);
if (ret) {
pr_err("%s: can not request gpio %d (%d)\n", name, gpio, ret);
return ret;
}
ret = gpio_direction_output(gpio, 1);
if (ret)
pr_err("%s: can not configure gpio %d as output (%d)\n", name, gpio, ret);
return ret;
}
/*
* LCD Controller
*/
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "QD",
.refresh = 60,
.xres = 480, .yres = 272,
.pixclock = KHZ2PICOS(9000),
.left_margin = 8, .right_margin = 43,
.upper_margin = 4, .lower_margin = 12,
.hsync_len = 5, .vsync_len = 10,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
/* Default output mode is TFT 24 bit */
#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP)
static void at91_lcdc_power_control(int on)
{
gpio_set_value(AT91_PIN_PC25, !on);
}
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
.atmel_lcdfb_power_control = at91_lcdc_power_control,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
if (ek_gpio_request_output(AT91_PIN_PC25, "lcdc_power"))
return;
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcdc(void) {}
#endif
/*
* MCI (SD/MMC)
*/
@ -228,7 +297,7 @@ static void __init ek_add_device_buttons(void)
static int at91sam9n12ek_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_sdram(0);
return 0;
}
@ -244,6 +313,7 @@ static int at91sam9n12ek_devices_init(void)
ek_add_device_i2c();
ek_add_device_ks8851();
ek_add_device_buttons();
ek_add_device_lcdc();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(CONFIG_MACH_AT91SAM9N12EK);

15
arch/arm/boards/at91sam9x5ek/env/bin/init_board vendored Normal file
View File

@ -0,0 +1,15 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi
exit 1

68
arch/arm/boards/at91sam9x5ek/init.c
View File

@ -106,7 +106,7 @@ static void ek_add_device_nand(void)
}
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
@ -118,6 +118,49 @@ static void ek_add_device_eth(void)
at91_add_device_eth(0, &macb_pdata);
}
#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD)
/*
* LCD Controller
*/
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "LG",
.refresh = 60,
.xres = 800, .yres = 480,
.pixclock = KHZ2PICOS(33260),
.left_margin = 88, .right_margin = 168,
.upper_margin = 8, .lower_margin = 37,
.hsync_len = 128, .vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
/* Default output mode is TFT 24 bit */
#define AT91SAM9X5_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP)
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_lcdcon2 = AT91SAM9X5_DEFAULT_LCDCFG5,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcdc(void) {}
#endif
/*
* MCI (SD/MMC)
*/
@ -192,14 +235,24 @@ static void ek_add_device_spi(void)
at91_add_device_spi(0, &spi_pdata);
}
#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI)
/*
* USB Host port
* USB HS Host port (common to OHCI & EHCI)
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
.vbus_pin = {AT91_PIN_PD20, AT91_PIN_PD19},
static struct at91_usbh_data ek_usbh_hs_data = {
.ports = 2,
.vbus_pin = {AT91_PIN_PD19, AT91_PIN_PD20},
};
static void ek_add_device_usb(void)
{
at91_add_device_usbh_ohci(&ek_usbh_hs_data);
at91_add_device_usbh_ehci(&ek_usbh_hs_data);
}
#else
static void ek_add_device_usb(void) {}
#endif
struct gpio_led leds[] = {
{
.gpio = AT91_PIN_PB18,
@ -228,7 +281,7 @@ static void __init ek_add_led(void)
static int at91sam9x5ek_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_sdram(0);
return 0;
}
@ -250,9 +303,10 @@ static int at91sam9x5ek_devices_init(void)
ek_add_device_eth();
ek_add_device_spi();
ek_add_device_mci();
at91_add_device_usbh_ohci(&ek_usbh_data);
ek_add_device_usb();
ek_add_led();
ek_add_device_i2c();
ek_add_device_lcdc();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(CONFIG_MACH_AT91SAM9X5EK);

2
arch/arm/boards/beaglebone/board.c
View File

@ -27,7 +27,7 @@
#include <driver.h>
#include <fs.h>
#include <linux/stat.h>
#include <environment.h>
#include <envfs.h>
#include <sizes.h>
#include <io.h>
#include <ns16550.h>

4
arch/arm/boards/mmccpu/Makefile
View File

@ -1 +1,5 @@
obj-y += init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o

118
arch/arm/boards/mmccpu/config.h
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@ -3,122 +3,4 @@
#define AT91_MAIN_CLOCK 18432000
/* values */
#define MASTER_PLL_MUL 54
#define MASTER_PLL_DIV 4
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
AT91_PMC_OUT | \
AT91_PMC_PLLCOUNT | /* PLL Counter */ \
(2 << 28) | /* PLL Clock Frequency Range */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 1.8V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V | \
AT91_MATRIX_EBI0_CS1A_SDRAMC | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA)
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1 0x13c
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
AT91_SDRAMC_CAS_3 | \
AT91_SDRAMC_DBW_32 | \
(2 << 8) | /* tWR - Write Recovery Delay */ \
(8 << 12) | /* tRC - Row Cycle Delay */ \
(2 << 16) | /* tRP - Row Precharge Delay */ \
(2 << 20) | /* tRCD - Row to Column Delay */ \
(5 << 24) | /* tRAS - Active to Precharge Delay */ \
(12 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_TR_VAL2 780 /* SDRAM_TR */
/* setup CS0 (NOR Flash) - 16-bit */
#define CONFIG_SYS_SMC_CS 0
#if 1
#define CONFIG_SYS_SMC_SETUP_VAL \
(AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
#define CONFIG_SYS_SMC_PULSE_VAL \
(AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
#define CONFIG_SYS_SMC_CYCLE_VAL \
(AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16))
#define CONFIG_SYS_SMC_MODE_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(6))
#elif 0 /* slow setup */
#define CONFIG_SYS_SMC_SETUP_VAL \
(AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) | \
AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0))
#define CONFIG_SYS_SMC_PULSE_VAL \
(AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) | \
AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13))
#define CONFIG_SYS_SMC_CYCLE_VAL \
(AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00))
#define CONFIG_SYS_SMC_MODE_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(1))
#else /* RONETIX' original values */
#define CONFIG_SYS_SMC_SETUP_VAL \
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
#define CONFIG_SYS_SMC_PULSE_VAL \
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
#define CONFIG_SYS_SMC_CYCLE_VAL \
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
#define CONFIG_SYS_SMC_MODE_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(6))
#endif
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_PROCRST | \
AT91_RSTC_RSTTYP_WAKEUP | \
AT91_RSTC_RSTTYP_WATCHDOG)
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
AT91_WDT_WDV | \
AT91_WDT_WDDIS | \
AT91_WDT_WDD)
#endif /* __CONFIG_H */

135
arch/arm/boards/mmccpu/lowlevel_init.c Normal file
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@ -0,0 +1,135 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_PLL_MUL 54
#define MASTER_PLL_DIV 4
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_1_8V |
AT91_MATRIX_EBI0_CS1A_SDRAMC |
AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
cfg->smc_cs = 0;
#if 1
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_16 |
AT91_SMC_TDFMODE |
AT91_SMC_TDF_(6);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
cfg->smc_setup =
AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
#elif 0 /* slow setup */
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_16 |
AT91_SMC_TDFMODE |
AT91_SMC_TDF_(1);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(0xd00) | AT91_SMC_NRDCYCLE_(0xd00);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(5) | AT91_SMC_NCS_WRPULSE_(7) |
AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(13);
cfg->smc_setup =
AT91_SMC_NWESETUP_(3) | AT91_SMC_NCS_WRSETUP_(2) |
AT91_SMC_NRDSETUP_(8) | AT91_SMC_NCS_RDSETUP_(0);
#else /* RONETIX' original values */
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_16 |
AT91_SMC_TDFMODE |
AT91_SMC_TDF_(6);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
cfg->smc_setup =
AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
#endif
cfg->pmc_mor =
AT91_PMC_MOSCEN |
(255 << 8); /* Main Oscillator Start-up Time */
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_OUT |
AT91_PMC_PLLCOUNT | /* PLL Counter */
(2 << 28) | /* PLL Clock Frequency Range */
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x13C;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NC_9 |
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_3 |
AT91_SDRAMC_DBW_32 |
(2 << 8) | /* tWR - Write Recovery Delay */
(8 << 12) | /* tRC - Row Cycle Delay */
(2 << 16) | /* tRP - Row Precharge Delay */
(2 << 20) | /* tRCD - Row to Column Delay */
(5 << 24) | /* tRAS - Active to Precharge Delay */
(12 << 28); /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = 780;
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

2
arch/arm/boards/panda/board.c
View File

@ -19,7 +19,7 @@
#include <sizes.h>
#include <asm/mmu.h>
#include <mach/gpio.h>
#include <environment.h>
#include <envfs.h>
#include <mach/xload.h>
#include <i2c/i2c.h>
#include <gpio.h>

4
arch/arm/boards/pm9261/Makefile
View File

@ -1 +1,5 @@
obj-y += init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o

87
arch/arm/boards/pm9261/config.h
View File

@ -3,91 +3,4 @@
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
AT91_PMC_OUT | \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
#define CONFIG_SYS_MATRIX_EBICSA_VAL \
(AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
AT91_SDRAMC_CAS_3 | \
AT91_SDRAMC_DBW_32 | \
(1 << 8) | /* Write Recovery Delay */ \
(7 << 12) | /* Row Cycle Delay */ \
(3 << 16) | /* Row Precharge Delay */ \
(2 << 20) | /* Row to Column Delay */ \
(5 << 24) | /* Active to Precharge Delay */ \
(1 << 28)) /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC_CS 0
#define CONFIG_SYS_SMC_SETUP_VAL \
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
#define CONFIG_SYS_SMC_PULSE_VAL \
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
#define CONFIG_SYS_SMC_CYCLE_VAL \
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
#define CONFIG_SYS_SMC_MODE_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_PROCRST | \
AT91_RSTC_RSTTYP_WAKEUP | \
AT91_RSTC_RSTTYP_WATCHDOG)
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
AT91_WDT_WDV | \
AT91_WDT_WDDIS | \
AT91_WDT_WDD)
#endif /* __CONFIG_H */

102
arch/arm/boards/pm9261/lowlevel_init.c Normal file
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@ -0,0 +1,102 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
#define MAIN_PLL_DIV 2
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_16 |
AT91_SMC_TDFMODE |
AT91_SMC_TDF_(6);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
cfg->smc_setup =
AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
cfg->pmc_mor =
AT91_PMC_MOSCEN |
(255 << 8); /* Main Oscillator Start-up Time */
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_OUT |
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x13C;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NC_9 |
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_3 |
AT91_SDRAMC_DBW_32 |
(1 << 8) | /* Write Recovery Delay */
(7 << 12) | /* Row Cycle Delay */
(3 << 16) | /* Row Precharge Delay */
(2 << 20) | /* Row to Column Delay */
(5 << 24) | /* Active to Precharge Delay */
(1 << 28); /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = 1200;
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

4
arch/arm/boards/pm9263/Makefile
View File

@ -1 +1,5 @@
obj-y += init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o

103
arch/arm/boards/pm9263/config.h
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@ -3,107 +3,4 @@
#define AT91_MAIN_CLOCK 18432000
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
AT91_PMC_OUT | \
AT91_PMC_PLLCOUNT | /* PLL Counter */ \
(2 << 28) | /* PLL Clock Frequency Range */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#if (MAIN_PLL_DIV == 2)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
/* PCK/2 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91SAM9_PMC_MDIV_2 | \
AT91_PMC_PDIV_1)
#else
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR1_VAL \
(AT91_PMC_CSS_SLOW | \
AT91_PMC_PRES_1 | \
AT91RM9200_PMC_MDIV_3 | \
AT91_PMC_PDIV_1)
/* PCK/4 = MCK Master Clock from PLLA */
#define CONFIG_SYS_MCKR2_VAL \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91RM9200_PMC_MDIV_3 | \
AT91_PMC_PDIV_1)
#endif
/* define PDC[31:16] as DATA[31:16] */
#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
/* no pull-up for D[31:16] */
#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
(AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \
AT91_MATRIX_EBI0_CS1A_SDRAMC)
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_13 | \
AT91_SDRAMC_NB_4 | \
AT91_SDRAMC_CAS_2 | \
AT91_SDRAMC_DBW_32 | \
(2 << 8) | /* tWR - Write Recovery Delay */ \
(7 << 12) | /* tRC - Row Cycle Delay */ \
(2 << 16) | /* tRP - Row Precharge Delay */ \
(2 << 20) | /* tRCD - Row to Column Delay */ \
(5 << 24) | /* tRAS - Active to Precharge Delay */ \
(8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
#define CONFIG_SYS_SMC_CS 0
#define CONFIG_SYS_SMC_SETUP_VAL \
(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
#define CONFIG_SYS_SMC_PULSE_VAL \
(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
#define CONFIG_SYS_SMC_CYCLE_VAL \
(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
#define CONFIG_SYS_SMC_MODE_VAL \
(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
AT91_SMC_DBW_16 | \
AT91_SMC_TDFMODE | \
AT91_SMC_TDF_(6))
/* user reset enable */
#define CONFIG_SYS_RSTC_RMR_VAL \
(AT91_RSTC_KEY | \
AT91_RSTC_PROCRST | \
AT91_RSTC_RSTTYP_WAKEUP | \
AT91_RSTC_RSTTYP_WATCHDOG)
/* Disable Watchdog */
#define CONFIG_SYS_WDTC_WDMR_VAL \
(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
AT91_WDT_WDV | \
AT91_WDT_WDDIS | \
AT91_WDT_WDD)
#endif /* __CONFIG_H */

2
arch/arm/boards/pm9263/init.c
View File

@ -89,7 +89,7 @@ static void pm_add_device_nand(void)
}
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = -1,
};

121
arch/arm/boards/pm9263/lowlevel_init.c Normal file
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@ -0,0 +1,121 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65
#define MAIN_PLL_DIV 2 /* 2 or 4 */
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
AT91_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_16 |
AT91_SMC_TDFMODE |
AT91_SMC_TDF_(6);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) |
AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11);
cfg->smc_setup =
AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) |
AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10);
cfg->pmc_mor =
AT91_PMC_MOSCEN |
(255 << 8); /* Main Oscillator Start-up Time */
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_OUT |
AT91_PMC_PLLCOUNT | /* PLL Counter */
(2 << 28) | /* PLL Clock Frequency Range */
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
if (MAIN_PLL_DIV == 2) {
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
} else {
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91RM9200_PMC_MDIV_3 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91RM9200_PMC_MDIV_3 |
AT91_PMC_PDIV_1;
}
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x3AA;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NC_9 |
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_2 |
AT91_SDRAMC_DBW_32 |
(2 << 8) | /* tWR - Write Recovery Delay */
(7 << 12) | /* tRC - Row Cycle Delay */
(2 << 16) | /* tRP - Row Precharge Delay */
(2 << 20) | /* tRCD - Row to Column Delay */
(5 << 24) | /* tRAS - Active to Precharge Delay */
(8 << 28); /* tXSR - Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = 1200;
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

4
arch/arm/boards/pm9g45/init.c
View File

@ -113,7 +113,7 @@ static void __init pm9g45_add_device_usbh(void) {}
#endif
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
@ -137,7 +137,7 @@ static void pm9g45_add_device_eth(void)
static int pm9g45_mem_init(void)
{
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_sdram(0);
return 0;
}

2
arch/arm/boards/qil-a9260/init.c
View File

@ -78,7 +78,7 @@ static void qil_a9260_add_device_mci(void) {}
#ifdef CONFIG_CALAO_MB_QIL_A9260
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = -1,
};

2
arch/arm/boards/sama5d3xek/Makefile Normal file
View File

@ -0,0 +1,2 @@
obj-y += init.o
obj-$(CONFIG_W1) += hw_version.o

6
arch/arm/boards/sama5d3xek/config.h Normal file
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@ -0,0 +1,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
#endif /* __CONFIG_H */

15
arch/arm/boards/sama5d3xek/env/bin/init_board vendored Normal file
View File

@ -0,0 +1,15 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
splash=/env/splash.png
if [ -f ${splash} -a -e /dev/fb0 ]; then
splash -o ${splash}
fb0.enable=1
fi
exit 1

44
arch/arm/boards/sama5d3xek/env/config vendored Normal file
View File

@ -0,0 +1,44 @@
#!/bin/sh
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp-barebox
global.dhcp.vendor_id=barebox-sama5d3xek
global.dhcp.client_id="${sama5d3xcm.board}-${sama5d3xcm.vendor}"
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp', 'nor' or 'nand'
kernel_loc=nfs
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'nfs', 'tftp', 'nand' or empty
oftree_loc=nfs
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root.$rootfs_type
ubiroot=rootfs
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage=zImage
#kernelimage=uImage
#kernelimage=Image
#kernelimage=Image.lzo
nand_device=atmel_nand
nand_parts="256k(at91bootstrap),384k(barebox)ro,256k@768k(bareboxenv),256k(bareboxenv2),128k@1536k(oftree),5M@2M(kernel),-@8M(rootfs)"
rootfs_mtdblock_nand=7
m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)"
autoboot_timeout=3
bootargs="console=ttyS0,115200"
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# "

251
arch/arm/boards/sama5d3xek/hw_version.c Normal file
View File

@ -0,0 +1,251 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <common.h>
#include <fs.h>
#include <fcntl.h>
#include <libbb.h>
#include <asm/armlinux.h>
#include <of.h>
#include <libfdt.h>
#include "hw_version.h"
enum board_type {
BOARD_TYPE_MB,
BOARD_TYPE_DM,
BOARD_TYPE_CPU,
};
static struct board_info {
char *name;
enum board_type type;
unsigned char id;
} board_list[] = {
{"SAMA5D3x-MB", BOARD_TYPE_MB, 0},
{"SAMA5D3x-DM", BOARD_TYPE_DM, 1},
{"SAMA5D31-CM", BOARD_TYPE_CPU, 2},
{"SAMA5D33-CM", BOARD_TYPE_CPU, 3},
{"SAMA5D34-CM", BOARD_TYPE_CPU, 4},
{"SAMA5D35-CM", BOARD_TYPE_CPU, 5},
{"PDA-DM", BOARD_TYPE_DM, 7},
};
static struct board_info* get_board_info_by_name(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(board_list); i++) {
char *bname = board_list[i].name;
if (strncmp(name, bname, strlen(bname)) == 0)
return &board_list[i];
}
return NULL;
}
static struct vendor_info {
char *name;
enum vendor_id id;
} vendor_list[] = {
{"EMBEST", VENDOR_EMBEST},
{"FLEX", VENDOR_FLEX},
{"RONETIX", VENDOR_RONETIX},
{"COGENT", VENDOR_COGENT},
{"PDA", VENDOR_PDA},
};
static struct vendor_info* get_vendor_info_by_name(const char *name)
{
int i;
for (i = 0; i < ARRAY_SIZE(vendor_list); i++) {
char *vname = vendor_list[i].name;
if (strncmp(name, vname, strlen(vname)) == 0)
return &vendor_list[i];
}
return NULL;
}
#define BOARD_NAME_LEN 12
#define VENDOR_NAME_LEN 10
#define VENDOR_COUNTRY_LEN 2
struct one_wire_info {
u8 total_bytes;
u8 vendor_name[VENDOR_NAME_LEN];
u8 vendor_country[VENDOR_COUNTRY_LEN];
u8 board_name[BOARD_NAME_LEN];
u8 year;
u8 week;
u8 revision_board;
u8 revision_schema;
u8 revision_bom;
u8 checksum_l;
u8 checksum_h;
}__attribute__ ((packed));
static int at91sama5d3xek_read_w1(const char *file, struct one_wire_info *info)
{
int fd;
int ret;
fd = open(file, O_RDONLY);
if (fd < 0) {
ret = fd;
goto err;
}
ret = read_full(fd, info, sizeof(*info));
if (ret < 0)
goto err_open;
if (ret < sizeof(*info)) {
ret = -EINVAL;
goto err_open;
}
pr_debug("total_bytes = %d\n", info->total_bytes);
pr_debug("vendor_name = %s\n", info->vendor_name);
pr_debug("vendor_country = %.2s\n", info->vendor_country);
pr_debug("board_name = %s\n", info->board_name);
pr_debug("year = %d\n", info->year);
pr_debug("week = %d\n", info->week);
pr_debug("revision_board = %x\n", info->revision_board);
pr_debug("revision_schema = %x\n", info->revision_schema);
pr_debug("revision_bom = %x\n", info->revision_bom);
pr_debug("checksum_l = %x\n", info->checksum_l);
pr_debug("checksum_h = %x\n", info->checksum_h);
ret = 0;
err_open:
close(fd);
err:
if (ret)
pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret));
return ret;
}
static u32 sn = 0;
static u32 rev = 0;
bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid)
{
return ((sn >> 5) & 0x1f) == vid;
}
bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid)
{
return ((sn >> 25) & 0x1f) == vid;
}
bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid)
{
return ((sn >> 15) & 0x1f) == vid;
}
static void at91sama5d3xek_devices_detect_one(const char *name)
{
struct one_wire_info info;
struct board_info* binfo;
struct vendor_info* vinfo;
struct device_d *dev = NULL;
char str[16];
char *bname, *vname;
u8 vendor_id = 0;
if (at91sama5d3xek_read_w1(name, &info))
return;
binfo = get_board_info_by_name(info.board_name);
if (!binfo) {
pr_err("board %s no supported\n", info.board_name);
return;
}
bname = binfo->name;
vinfo = get_vendor_info_by_name(info.vendor_name);
vname = info.vendor_name;
if (vinfo) {
vendor_id = vinfo->id;
vname = vinfo->name;
}
switch (binfo->type) {
case BOARD_TYPE_CPU:
dev = add_generic_device_res("sama5d3xcm", DEVICE_ID_SINGLE, NULL, 0, NULL);
if (!dev)
return;
sn |= (binfo->id & 0x1f);
sn |= ((vendor_id & 0x1f) << 5);
rev |= (info.revision_board - 'A');
rev |= (((info.revision_schema - '0') & 0x3) << 15);
pr_info("CM");
break;
case BOARD_TYPE_MB:
dev = add_generic_device_res("sama5d3xmb", DEVICE_ID_SINGLE, NULL, 0, NULL);
if (!dev)
return;
sn |= ((binfo->id & 0x1f) << 20);
sn |= ((vendor_id & 0x1f) << 25);
rev |= ((info.revision_board - 'A') << 10);
rev |= (((info.revision_schema - '0') & 0x3) << 21);
pr_info("MB");
break;
case BOARD_TYPE_DM:
dev = add_generic_device_res("sama5d3xdm", DEVICE_ID_SINGLE, NULL, 0, NULL);
if (!dev)
return;
sn |= ((binfo->id & 0x1f) << 10);
sn |= ((vendor_id & 0x1f) << 15);
rev |= ((info.revision_board - 'A') << 5);
rev |= (((info.revision_schema - '0') & 0x3) << 18);
pr_info("DM");
break;
}
pr_info(": %s [%c%c] from %s\n",
bname, info.revision_board, info.revision_schema, vname);
dev_add_param_fixed(dev, "vendor", vname);
dev_add_param_fixed(dev, "board", bname);
sprintf(str, "%.2s", info.vendor_country);
dev_add_param_fixed(dev, "country", str);
sprintf(str, "%d", info.year);
dev_add_param_fixed(dev, "year", str);
sprintf(str, "%d", info.week);
dev_add_param_fixed(dev, "week", str);
sprintf(str, "%c", info.revision_board);
dev_add_param_fixed(dev, "revision_board", str);
sprintf(str, "%c", info.revision_schema);
dev_add_param_fixed(dev, "revision_schema", str);
sprintf(str, "%c", info.revision_bom);
dev_add_param_fixed(dev, "revision_bom", str);
}
void at91sama5d3xek_devices_detect_hw(void)
{
at91sama5d3xek_devices_detect_one("/dev/ds24310");
at91sama5d3xek_devices_detect_one("/dev/ds28ec200");
at91sama5d3xek_devices_detect_one("/dev/ds24330");
pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev);
armlinux_set_revision(rev);
armlinux_set_serial(sn);
}

53
arch/arm/boards/sama5d3xek/hw_version.h Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#ifndef __HW_REVISION_H__
#define __HW_REVISION_H__
enum vendor_id {
VENDOR_UNKNOWN = 0,
VENDOR_EMBEST = 1,
VENDOR_FLEX = 2,
VENDOR_RONETIX = 3,
VENDOR_COGENT = 4,
VENDOR_PDA = 5,
};
#ifdef CONFIG_W1
bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid);
bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid);
bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid);
void at91sama5d3xek_devices_detect_hw(void);
#else
bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid)
{
return false;
}
bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid)
{
return false;
}
bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid)
{
return false;
}
void at91sama5d3xek_devices_detect_hw(void) {}
#endif
#endif /* __HW_REVISION_H__ */

403
arch/arm/boards/sama5d3xek/init.c Normal file
View File

@ -0,0 +1,403 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#include <common.h>
#include <net.h>
#include <init.h>
#include <environment.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
#include <io.h>
#include <asm/hardware.h>
#include <nand.h>
#include <sizes.h>
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91sam9x5_matrix.h>
#include <input/qt1070.h>
#include <readkey.h>
#include <poller.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
#include <spi/spi.h>
#include <linux/clk.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include "hw_version.h"
struct w1_gpio_platform_data w1_pdata = {
.pin = AT91_PIN_PE25,
.ext_pullup_enable_pin = -EINVAL,
.is_open_drain = 0,
};
#if defined(CONFIG_NAND_ATMEL)
static struct atmel_nand_data nand_pdata = {
.ale = 21,
.cle = 22,
.det_pin = -EINVAL,
.rdy_pin = -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#endif
.on_flash_bbt = 1,
};
static struct sam9_smc_config cm_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 1,
.ncs_write_setup = 0,
.nwe_setup = 1,
.ncs_read_pulse = 6,
.nrd_pulse = 4,
.ncs_write_pulse = 5,
.nwe_pulse = 3,
.read_cycle = 6,
.write_cycle = 5,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
.tdf_cycles = 1,
};
static void ek_add_device_nand(void)
{
struct clk *clk = clk_get(NULL, "smc_clk");
clk_enable(clk);
/* setup bus-width (8 or 16) */
if (nand_pdata.bus_width_16)
cm_nand_smc_config.mode |= AT91_SMC_DBW_16;
else
cm_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &cm_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
#else
static void ek_add_device_nand(void) {}
#endif
#if defined(CONFIG_DRIVER_NET_MACB)
static struct at91_ether_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
static bool used_23 = false;
static bool used_43 = false;
static int ek_register_mac_address_23(int id)
{
if (used_23)
return -EBUSY;
used_23 = true;
return w1_local_mac_address_register(id, "tml", "w1-23-0");
}
static int ek_register_mac_address_43(int id)
{
if (used_43)
return -EBUSY;
used_43 = true;
return w1_local_mac_address_register(id, "tml", "w1-43-0");
}
static void ek_add_device_eth(void)
{
if (w1_local_mac_address_register(0, "tml", "w1-2d-0"))
if (ek_register_mac_address_23(0))
ek_register_mac_address_43(0);
if (ek_register_mac_address_23(1))
ek_register_mac_address_43(1);
at91_add_device_eth(1, &macb_pdata);
}
#else
static void ek_add_device_eth(void) {}
#endif
#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD)
/*
* LCD Controller
*/
static struct fb_videomode at91_tft_vga_modes[] = {
{
.name = "LG",
.refresh = 60,
.xres = 800, .yres = 480,
.pixclock = KHZ2PICOS(33260),
.left_margin = 88, .right_margin = 168,
.upper_margin = 8, .lower_margin = 37,
.hsync_len = 128, .vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
},
};
/* Default output mode is TFT 24 bit */
#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP)
/* Driver datas */
static struct atmel_lcdfb_platform_data ek_lcdc_data = {
.lcdcon_is_backlight = true,
.default_bpp = 16,
.default_dmacon = ATMEL_LCDC_DMAEN,
.default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5,
.guard_time = 9,
.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB,
.mode_list = at91_tft_vga_modes,
.num_modes = ARRAY_SIZE(at91_tft_vga_modes),
};
static void ek_add_device_lcdc(void)
{
at91_add_device_lcdc(&ek_lcdc_data);
}
#else
static void ek_add_device_lcdc(void) {}
#endif
#if defined(CONFIG_MCI_ATMEL)
/*
* MCI (SD/MMC)
*/
static struct atmel_mci_platform_data mci0_data = {
.bus_width = 4,
.detect_pin = AT91_PIN_PD17,
.wp_pin = -EINVAL,
};
static struct atmel_mci_platform_data mci1_data = {
.bus_width = 4,
.detect_pin = AT91_PIN_PD18,
.wp_pin = -EINVAL,
};
static void ek_add_device_mci(void)
{
/* MMC0 */
at91_add_device_mci(0, &mci0_data);
/* MMC1 */
at91_add_device_mci(1, &mci1_data);
}
#else
static void ek_add_device_mci(void) {}
#endif
#if defined(CONFIG_I2C_GPIO)
struct qt1070_platform_data qt1070_pdata = {
.irq_pin = AT91_PIN_PE31,
};
static struct i2c_board_info i2c_devices[] = {
{
.platform_data = &qt1070_pdata,
I2C_BOARD_INFO("qt1070", 0x1b),
},
};
static void ek_add_device_i2c(void)
{
at91_set_gpio_input(qt1070_pdata.irq_pin, 0);
at91_set_deglitch(qt1070_pdata.irq_pin, 1);
at91_add_device_i2c(1, i2c_devices, ARRAY_SIZE(i2c_devices));
at91_add_device_i2c(0, NULL, 0);
}
#else
static void ek_add_device_i2c(void) {}
#endif
#if defined(CONFIG_DRIVER_SPI_ATMEL)
static const struct spi_board_info ek_spi_devices[] = {
{
.name = "m25p80",
.chip_select = 0,
.max_speed_hz = 30 * 1000 * 1000,
.bus_num = 0,
}
};
static unsigned spi0_standard_cs[] = { AT91_PIN_PD13 };
static struct at91_spi_platform_data spi_pdata = {
.chipselect = spi0_standard_cs,
.num_chipselect = ARRAY_SIZE(spi0_standard_cs),
};
static void ek_add_device_spi(void)
{
spi_register_board_info(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
at91_add_device_spi(0, &spi_pdata);
}
#else
static void ek_add_device_spi(void) {}
#endif
#ifdef CONFIG_LED_GPIO
struct gpio_led leds[] = {
{
.gpio = AT91_PIN_PE24,
.active_low = 1,
.led = {
.name = "d1",
},
}, {
.gpio = AT91_PIN_PE25,
.active_low = 1,
.led = {
.name = "d2",
},
},
};
static void ek_add_led(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(leds); i++) {
at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
led_gpio_register(&leds[i]);
}
led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led);
}
#else
static void ek_add_led(void) {}
#endif
static int at91sama5d3xek_mem_init(void)
{
at91_add_device_sdram(0);
return 0;
}
mem_initcall(at91sama5d3xek_mem_init);
static void ek_add_device_w1(void)
{
at91_set_gpio_input(w1_pdata.pin, 0);
at91_set_multi_drive(w1_pdata.pin, 1);
add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata);
at91sama5d3xek_devices_detect_hw();
}
#ifdef CONFIG_POLLER
/*
* The SiI9022A (HDMI) and QT1070 share the same irq
* but if the SiI9022A is not reset the irq is pull down
* So do it. As the SiI9022A need 1s to reset (500ms up then 500ms down then up)
* do it poller to do not slow down the boot
*/
static int hdmi_reset_pin = AT91_PIN_PC31;
static uint64_t hdmi_reset_start;
struct poller_struct hdmi_poller;
static void hdmi_on_poller(struct poller_struct *poller)
{
if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND))
return;
gpio_set_value(hdmi_reset_pin, 1);
poller_unregister(poller);
ek_add_device_i2c();
}
static void hdmi_off_poller(struct poller_struct *poller)
{
if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND))
return;
gpio_set_value(hdmi_reset_pin, 0);
hdmi_reset_start = get_time_ns();
poller->func = hdmi_on_poller;
}
static void ek_add_device_hdmi(void)
{
at91_set_gpio_output(hdmi_reset_pin, 1);
hdmi_reset_start = get_time_ns();
hdmi_poller.func = hdmi_off_poller;
poller_register(&hdmi_poller);
}
#else
static void ek_add_device_hdmi(void)
{
ek_add_device_i2c();
}
#endif
static int at91sama5d3xek_devices_init(void)
{
ek_add_device_w1();
ek_add_device_hdmi();
ek_add_device_nand();
ek_add_led();
ek_add_device_eth();
ek_add_device_spi();
ek_add_device_mci();
ek_add_device_lcdc();
armlinux_set_bootparams((void *)(SAMA5_DDRCS + 0x100));
devfs_add_partition("nand0", 0x00000, SZ_256K, DEVFS_PARTITION_FIXED, "at91bootstrap_raw");
dev_add_bb_dev("at91bootstrap_raw", "at91bootstrap");
devfs_add_partition("nand0", SZ_256K, SZ_256K + SZ_128K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K + SZ_256K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", SZ_1M, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
}
device_initcall(at91sama5d3xek_devices_init);
static int at91sama5d3xek_console_init(void)
{
at91_register_uart(0, 0);
at91_register_uart(2, 0);
return 0;
}
console_initcall(at91sama5d3xek_console_init);

1
arch/arm/boards/telit-evk-pro3/Makefile Normal file
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@ -0,0 +1 @@
obj-y += init.o

6
arch/arm/boards/telit-evk-pro3/config.h Normal file
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@ -0,0 +1,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MAIN_CLOCK 6000000 /* 6.000 MHz crystal */
#endif /* __CONFIG_H */

10
arch/arm/boards/telit-evk-pro3/env/boot/nand-ubi vendored Normal file
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@ -0,0 +1,10 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "nand (UBI)"
exit
fi
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
global.linux.bootargs.dyn.root="root=ubi0:rootfs ubi.mtd=nand0.rootfs rootfstype=ubifs"

8
arch/arm/boards/telit-evk-pro3/env/init/config-board vendored Normal file
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@ -0,0 +1,8 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=evk-pro3
global.linux.bootargs.base="console=ttyS0,115200"
global.boot.default=nand-ubi

11
arch/arm/boards/telit-evk-pro3/env/init/mtdparts-nand vendored Normal file
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@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "NAND partitions"
exit
fi
mtdparts="0xC0000(nand0.bootstrap),256k(nand0.barebox)ro,128k(nand0.bareboxenv),3M(nand0.kernel),-(nand0.rootfs)"
kernelname="atmel_nand"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}

40
arch/arm/boards/telit-evk-pro3/env/init/usb vendored Normal file
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@ -0,0 +1,40 @@
#!/bin/sh
# Connect PC31 to GND to enable DFU
gpio_dfu=95
gpio_name="PC31"
gpio_wait=5
product_id=0x1234
vendor_id=0x4321
dfu_config="/dev/nand0.bootstrap.bb(bootstrap)sr,/dev/nand0.barebox.bb(barebox)sr,/dev/nand0.kernel.bb(kernel)r,/dev/nand0.rootfs.bb(rootfs)r"
echo
if [ $at91_udc0.vbus != 1 ]; then
echo "No USB Device cable plugged, normal boot"
exit
fi
gpio_get_value ${gpio_dfu}
if [ $? = 0 ]; then
echo "${gpio_name} low value detected wait ${gpio_wait}s"
timeout -s -a ${gpio_wait}
if [ $at91_udc0.vbus != 1 ]; then
echo "No USB Device cable plugged, normal boot"
exit
fi
gpio_get_value ${gpio_dfu}
if [ $? = 0 ]; then
echo "Start DFU Mode"
dfu ${dfu_config} -P ${product_id} -V ${vendor_id}
exit
fi
fi
global.autoboot_timeout=16
echo "enable tty over USB Device, increase the boot delay to ${global.autoboot_timeout}s"
usbserial

176
arch/arm/boards/telit-evk-pro3/init.c Normal file
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@ -0,0 +1,176 @@
/*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* Copyright (C) 2013 Fabio Porcedda <fabio.porcedda@gmail.com>, Telit
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/armlinux.h>
#include <common.h>
#include <gpio.h>
#include <init.h>
#include <linux/clk.h>
#include <mach/at91_rstc.h>
#include <mach/at91sam9_smc.h>
#include <mach/board.h>
#include <mach/io.h>
#include <nand.h>
#define BOOTSTRAP_SIZE 0xC0000
static struct atmel_nand_data nand_pdata = {
.ale = 21,
.cle = 22,
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.on_flash_bbt = 1,
};
static struct sam9_smc_config evk_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 1,
.ncs_write_setup = 0,
.nwe_setup = 1,
.ncs_read_pulse = 3,
.nrd_pulse = 3,
.ncs_write_pulse = 3,
.nwe_pulse = 3,
.read_cycle = 5,
.write_cycle = 5,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
.tdf_cycles = 2,
};
static void evk_add_device_nand(void)
{
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &evk_nand_smc_config);
at91_add_device_nand(&nand_pdata);
}
static struct at91_ether_platform_data macb_pdata = {
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = 0,
};
static void evk_phy_reset(void)
{
unsigned long rstc;
struct clk *clk = clk_get(NULL, "macb_clk");
clk_enable(clk);
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
at91_set_gpio_input(AT91_PIN_PA25, 0);
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
(AT91_RSTC_ERSTL & (0x0d << 8)) |
AT91_RSTC_URSTEN);
at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
;
/* Restore NRST value */
at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
}
/*
* MCI (SD/MMC)
*/
#if defined(CONFIG_MCI_ATMEL)
static struct atmel_mci_platform_data __initdata evk_mci_data = {
.bus_width = 4,
.detect_pin = AT91_PIN_PA27,
.wp_pin = AT91_PIN_PA25,
};
static void evk_usb_add_device_mci(void)
{
at91_add_device_mci(0, &evk_mci_data);
}
#else
static void evk_usb_add_device_mci(void) {}
#endif
/*
* USB Host port
*/
static struct at91_usbh_data __initdata evk_usbh_data = {
.ports = 2,
.vbus_pin = { -EINVAL, -EINVAL },
};
/*
* USB Device port
*/
static struct at91_udc_data __initdata evk_udc_data = {
.vbus_pin = AT91_PIN_PC4,
.pullup_pin = -EINVAL, /* pull-up driven by UDC */
};
static int evk_mem_init(void)
{
at91_add_device_sdram(0);
return 0;
}
mem_initcall(evk_mem_init);
static int evk_devices_init(void)
{
evk_add_device_nand();
evk_phy_reset();
at91_add_device_eth(0, &macb_pdata);
at91_add_device_usbh_ohci(&evk_usbh_data);
at91_add_device_udc(&evk_udc_data);
evk_usb_add_device_mci();
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
devfs_add_partition("nand0", 0x00000, BOOTSTRAP_SIZE,
DEVFS_PARTITION_FIXED, "bootstrap_raw");
dev_add_bb_dev("bootstrap_raw", "bootstrap");
devfs_add_partition("nand0", BOOTSTRAP_SIZE, SZ_256K,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", BOOTSTRAP_SIZE + SZ_256K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
devfs_add_partition("nand0", BOOTSTRAP_SIZE + SZ_256K + SZ_128K,
SZ_128K, DEVFS_PARTITION_FIXED, "env_raw1");
dev_add_bb_dev("env_raw1", "env1");
return 0;
}
device_initcall(evk_devices_init);
static int evk_console_init(void)
{
at91_register_uart(0, 0);
return 0;
}
console_initcall(evk_console_init);

9
arch/arm/boards/tny-a926x/Makefile
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@ -1 +1,10 @@
obj-y += init.o
bootstrap-$(CONFIG_MACH_TNY_A9263) = tny_a9263_bootstrap.o
obj-$(CONFIG_AT91_BOOTSTRAP) += $(bootstrap-y)
lowlevel_init-$(CONFIG_MACH_TNY_A9263) = tny_a9263_lowlevel_init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)

45
arch/arm/boards/tny-a926x/init.c
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@ -113,7 +113,7 @@ static void tny_a9260_add_device_nand(void)
#ifdef CONFIG_DRIVER_NET_MACB
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = -1,
};
@ -160,16 +160,31 @@ static struct spi_board_info tny_a9g20_lpw_spi_devices[] = {
},
};
static int spi0_standard_cs[] = { AT91_PIN_PC11 };
struct at91_spi_platform_data spi0_pdata = {
.chipselect = spi0_standard_cs,
.num_chipselect = ARRAY_SIZE(spi0_standard_cs),
static struct spi_board_info tny_a9263_spi_devices[] = {
{
.name = "mtd_dataflash",
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
.chip_select = 0,
},
};
static int spi1_standard_cs[] = { AT91_PIN_PC3 };
struct at91_spi_platform_data spi1_pdata = {
.chipselect = spi1_standard_cs,
.num_chipselect = ARRAY_SIZE(spi1_standard_cs),
static int tny_a9263_spi0_standard_cs[] = { AT91_PIN_PA5 };
struct at91_spi_platform_data tny_a9263_spi0_pdata = {
.chipselect = tny_a9263_spi0_standard_cs,
.num_chipselect = ARRAY_SIZE(tny_a9263_spi0_standard_cs),
};
static int tny_a9g20_spi0_standard_cs[] = { AT91_PIN_PC11 };
struct at91_spi_platform_data tny_a9g20_spi0_pdata = {
.chipselect = tny_a9g20_spi0_standard_cs,
.num_chipselect = ARRAY_SIZE(tny_a9g20_spi0_standard_cs),
};
static int tny_a9g20_spi1_standard_cs[] = { AT91_PIN_PC3 };
struct at91_spi_platform_data tny_a9g20_spi1_pdata = {
.chipselect = tny_a9g20_spi1_standard_cs,
.num_chipselect = ARRAY_SIZE(tny_a9g20_spi1_standard_cs),
};
static void __init ek_add_device_udc(void)
@ -182,17 +197,19 @@ static void __init ek_add_device_udc(void)
static void __init ek_add_device_spi(void)
{
if (machine_is_tny_a9263())
return;
if (machine_is_tny_a9263()) {
spi_register_board_info(tny_a9263_spi_devices,
ARRAY_SIZE(tny_a9263_spi_devices));
at91_add_device_spi(0, &tny_a9263_spi0_pdata);
if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) {
} else if (machine_is_tny_a9g20() && at91_is_low_power_sdram()) {
spi_register_board_info(tny_a9g20_lpw_spi_devices,
ARRAY_SIZE(tny_a9g20_lpw_spi_devices));
at91_add_device_spi(1, &spi1_pdata);
at91_add_device_spi(1, &tny_a9g20_spi1_pdata);
} else {
spi_register_board_info(tny_a9g20_spi_devices,
ARRAY_SIZE(tny_a9g20_spi_devices));
at91_add_device_spi(0, &spi0_pdata);
at91_add_device_spi(0, &tny_a9g20_spi0_pdata);
}
}

16
arch/arm/boards/tny-a926x/tny_a9263_bootstrap.c Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <bootstrap.h>
#include <mach/bootstrap.h>
#ifdef CONFIG_MTD_DATAFLASH
void * bootstrap_board_read_dataflash(void)
{
return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864);
}
#endif

107
arch/arm/boards/tny-a926x/tny_a9263_lowlevel_init.c Normal file
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@ -0,0 +1,107 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_CLOCK 180
#if MASTER_CLOCK == 200
#define MASTER_PLL_MUL 100
#else
#define MASTER_PLL_MUL 90
#endif
#define MASTER_PLL_DIV 6
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
AT91_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_8 |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_TDF_(2);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3);
cfg->smc_setup =
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0);
cfg->pmc_mor = AT91_PMC_OSCBYPASS;
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_PLLCOUNT | /* PLL Counter */
(0 << 28) | /* PLL Clock Frequency Range */
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x13C;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NC_9 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_2 |
AT91_SDRAMC_DBW_32 |
(2 << 8) | /* Write Recovery Delay */
(7 << 12) | /* Row Cycle Delay */
(2 << 16) | /* Row Precharge Delay */
(2 << 20) | /* Row to Column Delay */
(5 << 24) | /* Active to Precharge Delay */
(8 << 28); /* Exit Self Refresh to Active Delay */
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = (MASTER_CLOCK * 7);
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

9
arch/arm/boards/usb-a926x/Makefile
View File

@ -1 +1,10 @@
obj-y += init.o
bootstrap-$(CONFIG_MACH_USB_A9263) = usb_a9263_bootstrap.o
obj-$(CONFIG_AT91_BOOTSTRAP) += $(bootstrap-y)
lowlevel_init-$(CONFIG_MACH_USB_A9263) = usb_a9263_lowlevel_init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
pbl-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)

44
arch/arm/boards/usb-a926x/init.c
View File

@ -51,6 +51,7 @@ static void usb_a9260_set_board_type(void)
armlinux_set_architecture(MACH_TYPE_USB_A9260);
}
#if defined(CONFIG_NAND_ATMEL)
static struct atmel_nand_data nand_pdata = {
.ale = 21,
.cle = 22,
@ -111,9 +112,13 @@ static void usb_a9260_add_device_nand(void)
at91_add_device_nand(&nand_pdata);
}
#else
static void usb_a9260_add_device_nand(void) {}
#endif
#if defined(CONFIG_DRIVER_NET_MACB)
static struct at91_ether_platform_data macb_pdata = {
.is_rmii = 1,
.phy_interface = PHY_INTERFACE_MODE_RMII,
.phy_addr = -1,
};
@ -149,6 +154,16 @@ static void usb_a9260_phy_reset(void)
AT91_RSTC_URSTEN);
}
static void usb_a9260_add_device_eth(void)
{
usb_a9260_phy_reset();
at91_add_device_eth(0, &macb_pdata);
}
#else
static void usb_a9260_add_device_eth(void) {}
#endif
#if defined(CONFIG_DRIVER_SPI_ATMEL)
static const struct spi_board_info usb_a9263_spi_devices[] = {
{
.name = "mtd_dataflash",
@ -191,6 +206,9 @@ static void usb_a9260_add_spi(void)
at91_add_device_spi(1, &spi_a9g20_pdata);
}
}
#else
static void usb_a9260_add_spi(void) {}
#endif
#if defined(CONFIG_MCI_ATMEL)
static struct atmel_mci_platform_data __initdata usb_a9260_mci_data = {
@ -205,11 +223,21 @@ static void usb_a9260_add_device_mci(void)
static void usb_a9260_add_device_mci(void) {}
#endif
#if defined(CONFIG_USB_OHCI)
static struct at91_usbh_data ek_usbh_data = {
.ports = 2,
.vbus_pin = { -EINVAL, -EINVAL },
};
static void usb_a9260_add_device_usb(void)
{
at91_add_device_usbh_ohci(&ek_usbh_data);
}
#else
static void usb_a9260_add_device_usb(void) {}
#endif
#ifdef CONFIG_USB_GADGET_DRIVER_AT91
/*
* USB Device port
*/
@ -225,7 +253,11 @@ static void __init ek_add_device_udc(void)
at91_add_device_udc(&ek_udc_data);
}
#else
static void __init ek_add_device_udc(void) {}
#endif
#ifdef CONFIG_LED_GPIO
struct gpio_led led = {
.gpio = AT91_PIN_PB21,
.led = {
@ -241,6 +273,9 @@ static void __init ek_add_led(void)
at91_set_gpio_output(led.gpio, led.active_low);
led_gpio_register(&led);
}
#else
static void ek_add_led(void) {}
#endif
static int usb_a9260_mem_init(void)
{
@ -356,11 +391,10 @@ static void usb_a9260_device_dab_mmx(void) {}
static int usb_a9260_devices_init(void)
{
usb_a9260_add_device_nand();
usb_a9260_phy_reset();
at91_add_device_eth(0, &macb_pdata);
usb_a9260_add_device_mci();
usb_a9260_add_device_eth();
usb_a9260_add_spi();
at91_add_device_usbh_ohci(&ek_usbh_data);
usb_a9260_add_device_usb();
ek_add_device_udc();
ek_add_led();
ek_add_device_button();
@ -382,6 +416,7 @@ static int usb_a9260_devices_init(void)
}
device_initcall(usb_a9260_devices_init);
#ifndef CONFIG_CONSOLE_NONE
static int usb_a9260_console_init(void)
{
struct device_d *dev;
@ -398,3 +433,4 @@ static int usb_a9260_console_init(void)
return 0;
}
console_initcall(usb_a9260_console_init);
#endif

16
arch/arm/boards/usb-a926x/usb_a9263_bootstrap.c Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <bootstrap.h>
#include <mach/bootstrap.h>
#ifdef CONFIG_MTD_DATAFLASH
void * bootstrap_board_read_dataflash(void)
{
return bootstrap_read_devfs("dataflash0", false, 0xffc0, 204864, 204864);
}
#endif

111
arch/arm/boards/usb-a926x/usb_a9263_lowlevel_init.c Normal file
View File

@ -0,0 +1,111 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91_lowlevel_init.h>
#define MASTER_CLOCK 180
#if MASTER_CLOCK == 200
#define MASTER_PLL_MUL 100
#else
#define MASTER_PLL_MUL 90
#endif
#define MASTER_PLL_DIV 6
void __bare_init at91sam926x_lowlevel_board_config(struct at91sam926x_lowlevel_cfg *cfg)
{
/* Disable Watchdog */
cfg->wdt_mr =
AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT |
AT91_WDT_WDV |
AT91_WDT_WDDIS |
AT91_WDT_WDD;
/* define PDC[31:16] as DATA[31:16] */
cfg->ebi_pio_pdr = 0xFFFF0000;
/* no pull-up for D[31:16] */
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
AT91_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_DBW_8 |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_TDF_(2);
cfg->smc_cycle =
AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5);
cfg->smc_pulse =
AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3);
cfg->smc_setup =
AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0);
cfg->pmc_mor = AT91_PMC_OSCBYPASS;
cfg->pmc_pllar =
AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */
AT91_PMC_PLLCOUNT | /* PLL Counter */
(0 << 28) | /* PLL Clock Frequency Range */
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV);
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr1 =
AT91_PMC_CSS_SLOW |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* PCK/2 = MCK Master Clock from PLLA */
cfg->pmc_mckr2 =
AT91_PMC_CSS_PLLA |
AT91_PMC_PRES_1 |
AT91SAM9_PMC_MDIV_2 |
AT91_PMC_PDIV_1;
/* SDRAM */
/* SDRAMC_TR - Refresh Timer register */
cfg->sdrc_tr1 = 0x13C;
/* SDRAMC_CR - Configuration register*/
cfg->sdrc_cr =
AT91_SDRAMC_NR_13 |
AT91_SDRAMC_NB_4 |
AT91_SDRAMC_CAS_2 |
AT91_SDRAMC_DBW_32 |
(2 << 8) | /* Write Recovery Delay */
(7 << 12) | /* Row Cycle Delay */
(2 << 16) | /* Row Precharge Delay */
(2 << 20) | /* Row to Column Delay */
(5 << 24) | /* Active to Precharge Delay */
(8 << 28); /* Exit Self Refresh to Active Delay */
if (IS_ENABLED(CONFIG_AT91_HAVE_SRAM_128M))
cfg->sdrc_cr |= AT91_SDRAMC_NC_10;
else
cfg->sdrc_cr |= AT91_SDRAMC_NC_9;
/* Memory Device Register -> SDRAM */
cfg->sdrc_mdr = AT91_SDRAMC_MD_SDRAM;
/* SDRAM_TR */
cfg->sdrc_tr2 = (MASTER_CLOCK * 7);
/* user reset enable */
cfg->rstc_rmr =
AT91_RSTC_KEY |
AT91_RSTC_PROCRST |
AT91_RSTC_RSTTYP_WAKEUP |
AT91_RSTC_RSTTYP_WATCHDOG;
}

79
arch/arm/configs/animeo_ip_defconfig Normal file
View File

@ -0,0 +1,79 @@
CONFIG_ARCH_AT91SAM9260=y
CONFIG_MACH_ANIMEO_IP=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_EXPERIMENTAL=y
CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="Animeo-IP:"
CONFIG_BAUDRATE=38400
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="y"
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/animeo_ip/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_WD=y
CONFIG_CMD_WD_DEFAULT_TIMOUT=16
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_MICREL_PHY=y
CONFIG_DRIVER_NET_MACB=y
# CONFIG_SPI is not set
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_BICOLOR=y
CONFIG_LED_TRIGGERS=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_AT91SAM9X=y
CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y

1
arch/arm/configs/at91sam9260ek_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARCH_AT91SAM9260=y
CONFIG_MACH_AT91SAM9260EK=y
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y

25
arch/arm/configs/at91sam9261ek_bootstrap_defconfig Normal file
View File

@ -0,0 +1,25 @@
CONFIG_ARCH_AT91SAM9261=y
CONFIG_AT91_BOOTSTRAP=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_DUMMY=y
CONFIG_PROMPT="9261-EK:"
CONFIG_SHELL_NONE=y
# CONFIG_TIMESTAMP is not set
CONFIG_CONSOLE_SIMPLE=y
# CONFIG_DEFAULT_ENVIRONMENT is not set
# CONFIG_SPI is not set
CONFIG_MTD=y
# CONFIG_MTD_WRITE is not set
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
# CONFIG_FS_RAMFS is not set
CONFIG_BOOTSTRAP_DEVFS=y

7
arch/arm/configs/at91sam9261ek_defconfig
View File

@ -38,6 +38,7 @@ CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
@ -51,9 +52,10 @@ CONFIG_CMD_TFTP=y
CONFIG_FS_TFTP=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_DM9K=y
# CONFIG_SPI is not set
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_DATAFLASH=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
@ -63,7 +65,10 @@ CONFIG_UBI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DFU=y
CONFIG_USB_GADGET_SERIAL=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_ATMEL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_PNG=y

71
arch/arm/configs/at91sam9261ek_first_stage_defconfig Normal file
View File

@ -0,0 +1,71 @@
CONFIG_ARCH_AT91SAM9261=y
CONFIG_CMD_AT91_BOOT_TEST=y
CONFIG_AT91_LOAD_BAREBOX_SRAM=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x27000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_EXPERIMENTAL=y
CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="9261-EK:"
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_PASSWD=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_DM9K=y
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_DATAFLASH=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DFU=y
CONFIG_USB_GADGET_SERIAL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_FS_TFTP=y

4
arch/arm/configs/at91sam9263ek_defconfig
View File

@ -36,6 +36,7 @@ CONFIG_CMD_UIMAGE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
@ -63,6 +64,8 @@ CONFIG_UBI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DFU=y
CONFIG_USB_GADGET_SERIAL=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_ATMEL=y
CONFIG_MCI=y
CONFIG_MCI_ATMEL=y
CONFIG_LED=y
@ -70,3 +73,4 @@ CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y
CONFIG_PNG=y

18
arch/arm/configs/at91sam9m10g45ek_defconfig
View File

@ -1,10 +1,12 @@
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_AT91SAM9M10G45EK=y
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_MALLOC_SIZE=0x800000
CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="9M10G45-EK:"
CONFIG_LONGHELP=y
@ -29,8 +31,6 @@ CONFIG_CMD_PASSWD=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
@ -38,13 +38,17 @@ CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_LED=y
@ -58,6 +62,8 @@ CONFIG_FS_TFTP=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_MACB=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
# CONFIG_SPI is not set
CONFIG_MTD=y
CONFIG_NAND=y
@ -66,6 +72,12 @@ CONFIG_NAND=y
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_EHCI_ATMEL=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_ATMEL=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
@ -75,4 +87,4 @@ CONFIG_LED_TRIGGERS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_PNG=y

99
arch/arm/configs/at91sam9m10ihd_defconfig Normal file
View File

@ -0,0 +1,99 @@
CONFIG_ARCH_AT91SAM9G45=y
CONFIG_MACH_AT91SAM9M10IHD=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0xa00000
CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="9M10IHD:"
CONFIG_LONGHELP=y
CONFIG_PROMPT_HUSH_PS2=">"
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_PASSWD_SUM_SHA1=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9m10ihd/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_PASSWD=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_BOOTM_AIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_MACB=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_M25P80=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_EHCI_ATMEL=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_ATMEL=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
CONFIG_EEPROM_AT24=y
CONFIG_KEYBOARD_QT1070=y
CONFIG_W1=y
CONFIG_W1_MASTER_GPIO=y
CONFIG_W1_SLAVE_DS2431=y
CONFIG_W1_SLAVE_DS2433=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_PNG=y

7
arch/arm/configs/at91sam9n12ek_defconfig
View File

@ -6,6 +6,8 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x26f00000
CONFIG_MALLOC_SIZE=0xa00000
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_EXPERIMENTAL=y
CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="9G20-EK:"
@ -40,6 +42,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
@ -70,6 +73,8 @@ CONFIG_UBI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DFU=y
CONFIG_USB_GADGET_SERIAL=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
@ -83,4 +88,4 @@ CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_PNG=y

10
arch/arm/configs/at91sam9x5ek_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0xa00000
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_EXPERIMENTAL=y
CONFIG_MALLOC_TLSF=y
@ -40,6 +41,7 @@ CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
@ -52,6 +54,8 @@ CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_MACB=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_MTD_M25P80=y
CONFIG_I2C=y
@ -66,6 +70,10 @@ CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_NAND_ATMEL_PMECC=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_EHCI_ATMEL=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
@ -83,4 +91,4 @@ CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_PNG=y

95
arch/arm/configs/sama5d3xek_defconfig Normal file
View File

@ -0,0 +1,95 @@
CONFIG_ARCH_SAMA5D3=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x60000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x26f00000
CONFIG_MALLOC_SIZE=0xA00000
CONFIG_EXPERIMENTAL=y
CONFIG_MALLOC_TLSF=y
CONFIG_PROMPT="A5D3X-EK:"
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="y"
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/sama5d3xek/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_CMD_MIITOOL=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_MICREL_PHY=y
CONFIG_DRIVER_NET_MACB=y
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_I2C=y
CONFIG_I2C_GPIO=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_M25P80=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_NAND_ATMEL_PMECC=y
CONFIG_UBI=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_ATMEL_HLCD=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_QT1070=y
CONFIG_W1=y
CONFIG_W1_MASTER_GPIO=y
CONFIG_W1_SLAVE_DS2431=y
CONFIG_W1_SLAVE_DS2433=y
CONFIG_W1_DUAL_SEARCH=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_PNG=y

73
arch/arm/configs/telit_evk_pro3_defconfig Normal file
View File

@ -0,0 +1,73 @@
CONFIG_ARCH_AT91SAM9260=y
CONFIG_MACH_GE863=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_EXPERIMENTAL=y
CONFIG_PROMPT="EVK-PRO3:"
CONFIG_LONGHELP=y
CONFIG_PROMPT_HUSH_PS2="y"
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_CONSOLE_ACTIVATE_ALL=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/telit-evk-pro3/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_LED=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_DRIVER_NET_MACB=y
# CONFIG_SPI is not set
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
CONFIG_UBI=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DFU=y
CONFIG_USB_GADGET_SERIAL=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_ATMEL=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_TRIGGERS=y
CONFIG_FS_TFTP=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y

26
arch/arm/configs/tny_a9263_bootstrap_defconfig Normal file
View File

@ -0,0 +1,26 @@
CONFIG_ARCH_AT91SAM9263=y
CONFIG_MACH_TNY_A9263=y
CONFIG_AT91_BOOTSTRAP=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_DUMMY=y
CONFIG_PROMPT="USB-9263:"
CONFIG_SHELL_NONE=y
CONFIG_CONSOLE_SIMPLE=y
# CONFIG_DEFAULT_ENVIRONMENT is not set
# CONFIG_SPI is not set
CONFIG_MTD=y
# CONFIG_MTD_WRITE is not set
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
# CONFIG_FS_RAMFS is not set
CONFIG_BOOTSTRAP_DEVFS=y

1
arch/arm/configs/tny_a9263_defconfig
View File

@ -62,6 +62,7 @@ CONFIG_DRIVER_NET_MACB=y
CONFIG_DRIVER_SPI_ATMEL=y
CONFIG_MTD=y
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_MTD_DATAFLASH=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set

27
arch/arm/configs/usb_a9263_128mib_bootstrap_defconfig Normal file
View File

@ -0,0 +1,27 @@
CONFIG_ARCH_AT91SAM9263=y
CONFIG_MACH_USB_A9263=y
CONFIG_AT91_HAVE_SRAM_128M=y
CONFIG_AT91_BOOTSTRAP=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_DUMMY=y
CONFIG_PROMPT="USB-9263:"
CONFIG_SHELL_NONE=y
# CONFIG_CONSOLE_FULL is not set
# CONFIG_DEFAULT_ENVIRONMENT is not set
# CONFIG_SPI is not set
CONFIG_MTD=y
# CONFIG_MTD_WRITE is not set
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
# CONFIG_FS_RAMFS is not set
CONFIG_BOOTSTRAP_DEVFS=y

26
arch/arm/configs/usb_a9263_bootstrap_defconfig Normal file
View File

@ -0,0 +1,26 @@
CONFIG_ARCH_AT91SAM9263=y
CONFIG_MACH_USB_A9263=y
CONFIG_AT91_BOOTSTRAP=y
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x12000
CONFIG_AEABI=y
# CONFIG_CMD_ARM_CPUINFO is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_PBL_IMAGE=y
CONFIG_MMU=y
CONFIG_MALLOC_DUMMY=y
CONFIG_PROMPT="USB-9263:"
CONFIG_SHELL_NONE=y
# CONFIG_CONSOLE_FULL is not set
# CONFIG_DEFAULT_ENVIRONMENT is not set
# CONFIG_SPI is not set
CONFIG_MTD=y
# CONFIG_MTD_WRITE is not set
# CONFIG_MTD_OOB_DEVICE is not set
CONFIG_NAND=y
# CONFIG_NAND_ECC_HW is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
# CONFIG_NAND_ECC_HW_NONE is not set
CONFIG_NAND_ATMEL=y
# CONFIG_FS_RAMFS is not set
CONFIG_BOOTSTRAP_DEVFS=y

90
arch/arm/mach-at91/Kconfig
View File

@ -18,11 +18,18 @@ config SOC_AT91SAM9
select AT91SAM9_SMC
select AT91SAM9_TIMER
config SOC_SAMA5
bool
select CPU_V7
select AT91SAM9_SMC
select AT91SAM9_TIMER
config ARCH_TEXT_BASE
hex
default 0x73f00000 if ARCH_AT91SAM9G45
default 0x26f00000 if ARCH_AT91SAM9X5
default 0x20f00000 if ARCH_AT91RM9200
default 0x21f00000 if MACH_ANIMEO_IP
default 0x23f00000
config BOARDINFO
@ -32,9 +39,11 @@ config BOARDINFO
default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK
default "Atmel at91sam9g10-ek" if MACH_AT91SAM9G10EK
default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK
default "Atmel at91sam9m10ihd" if MACH_AT91SAM9M10IHD
default "Atmel at91sam9m10g45-ek" if MACH_AT91SAM9M10G45EK
default "Atmel at91sam9n12-ek" if MACH_AT91SAM9N12EK
default "Atmel at91sam9x5-ek" if MACH_AT91SAM9X5EK
default "Atmel sama5d3x-ek" if MACH_SAMA5D3XEK
default "Bucyrus MMC-CPU" if MACH_MMCCPU
default "Calao USB-A9260" if MACH_USB_A9260
default "Calao USB-A9263" if MACH_USB_A9263
@ -47,6 +56,8 @@ config BOARDINFO
default "Calao TNY-A9263" if MACH_TNY_A9263
default "Calao TNY-A9G20" if MACH_TNY_A9G20
default "Calao QIL-A9260" if MACH_QIL_A9260
default "Somfy Animeo IP" if MACH_ANIMEO_IP
default "Telit EVK-PRO3" if MACH_GE863
config HAVE_NAND_ATMEL_BUSWIDTH_16
bool
@ -60,6 +71,12 @@ config AT91SAM9_RESET
config AT91SAM9G45_RESET
bool
config HAVE_AT91_LOAD_BAREBOX_SRAM
bool
config AT91SAM9_LOWLEVEL_INIT
bool
comment "Atmel AT91 System-on-Chip"
config SOC_AT91RM9200
@ -75,6 +92,7 @@ config SOC_AT91SAM9260
select HAVE_AT91_DBGU0
select HAS_MACB
select AT91SAM9_RESET
select AT91SAM9_LOWLEVEL_INIT
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
@ -84,6 +102,7 @@ config SOC_AT91SAM9261
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select AT91SAM9_RESET
select AT91SAM9_LOWLEVEL_INIT
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@ -93,6 +112,8 @@ config SOC_AT91SAM9263
select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9_RESET
select AT91SAM9_LOWLEVEL_INIT
select HAVE_AT91_LOAD_BAREBOX_SRAM
config SOC_AT91SAM9G45
bool
@ -140,6 +161,7 @@ config ARCH_AT91SAM9260
config ARCH_AT91SAM9261
bool "AT91SAM9261"
select SOC_AT91SAM9261
select HAVE_AT91_LOAD_BAREBOX_SRAM
config ARCH_AT91SAM9263
bool "AT91SAM9263"
@ -165,6 +187,13 @@ config ARCH_AT91SAM9N12
bool "AT91SAM9N12"
select SOC_AT91SAM9N12
config ARCH_SAMA5D3
bool "SAMA5D3x"
select SOC_SAMA5
select HAVE_AT91_DBGU1
select HAS_MACB
select AT91SAM9G45_RESET
endchoice
config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
@ -177,6 +206,7 @@ config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
default 0xF000 if ARCH_AT91SAM9G45
default 0x6000 if ARCH_AT91SAM9X5
default 0x6000 if ARCH_AT91SAM9N12
default 0x6000 if ARCH_SAMA5D3
default 0xffffffff
config SUPPORT_CALAO_DAB_MMX
@ -210,6 +240,9 @@ if ARCH_AT91SAM9260
choice
prompt "AT91SAM9260 Board Type"
config MACH_ANIMEO_IP
bool "Somfy Animeo IP"
config MACH_AT91SAM9260EK
bool "Atmel AT91SAM9260-EK"
select HAVE_NAND_ATMEL_BUSWIDTH_16
@ -236,6 +269,13 @@ config MACH_USB_A9260
Select this if you are using a Calao Systems USB-A9260.
<http://www.calao-systems.com>
config MACH_GE863
bool "Telit EVK-PRO3"
select HAVE_DEFAULT_ENVIRONMENT_NEW
help
Say y here if you are using Telit EVK-PRO3 with GE863-PRO3
<http://www.telit.com>
endchoice
endif
@ -250,6 +290,8 @@ choice
config MACH_AT91SAM9261EK
bool "Atmel AT91SAM9261-EK Evaluation Kit"
select HAS_DM9000
select HAVE_AT91_DATAFLASH_CARD
select MACH_HAS_LOWLEVEL_INIT
select HAVE_NAND_ATMEL_BUSWIDTH_16
help
Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
@ -352,12 +394,14 @@ config MACH_PM9263
config MACH_TNY_A9263
bool "CALAO TNY-A9263"
select SUPPORT_CALAO_MOB_TNY_MD2
select MACH_HAS_LOWLEVEL_INIT
help
Select this if you are using a Calao Systems TNY-A9263.
<http://www.calao-systems.com>
config MACH_USB_A9263
bool "CALAO USB-A9263"
select MACH_HAS_LOWLEVEL_INIT
help
Select this if you are using a Calao Systems USB-A9263.
<http://www.calao-systems.com>
@ -371,6 +415,11 @@ if ARCH_AT91SAM9G45
choice
prompt "AT91SAM9G45 or AT91SAM9M10 Board Type"
config MACH_AT91SAM9M10IHD
bool "Atmel AT91SAM9M10IDH Tablet"
help
Select this if you are using Atmel's AT91SAM9M10IHD Tablet
config MACH_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK Evaluation Kit"
select HAVE_NAND_ATMEL_BUSWIDTH_16
@ -423,6 +472,22 @@ endif
# ----------------------------------------------------------
if ARCH_SAMA5D3
choice
prompt "SAMA5D3 Board Type"
config MACH_SAMA5D3XEK
bool "Atmel SAMA5D3X Evaluation Kit"
help
Select this if you are using Atmel's SAMA5D3X-EK Evaluation Kit.
endchoice
endif
# ----------------------------------------------------------
comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD
@ -480,8 +545,33 @@ config CALAO_MB_QIL_A9260
bool "MB-QIL A9260 Motherboard Board support"
depends on MACH_QIL_A9260
if COMMAND_SUPPORT
config CMD_AT91MUX
bool "at91mux dump command"
default y
config CMD_AT91CLK
bool "at91clk dump command"
default y
config CMD_AT91_BOOT_TEST
bool "at91_boot_test"
help
allow to upload a boot binary to sram and execute it
useful to test bootstrap or barebox lowlevel init
endif
config AT91_BOOTSTRAP
bool "at91 bootstrap"
depends on MACH_HAS_LOWLEVEL_INIT
select BOOTSTRAP
config AT91_LOAD_BAREBOX_SRAM
bool "at91 laad barebox in sram"
depends on MACH_HAS_LOWLEVEL_INIT
depends on SHELL_NONE || HAVE_AT91_LOAD_BAREBOX_SRAM
default y if SHELL_NONE
endif

8
arch/arm/mach-at91/Makefile
View File

@ -1,6 +1,11 @@
obj-y += setup.o clock.o gpio.o
obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
lowlevel_init-y = at91sam926x_lowlevel_init.o
obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o
lowlevel_init-$(CONFIG_AT91SAM9_LOWLEVEL_INIT) = at91sam926x_lowlevel_init.o
lowlevel_init-$(CONFIG_SOC_AT91SAM9260) += at91sam9260_lowlevel_init.o
lowlevel_init-$(CONFIG_SOC_AT91SAM9261) += at91sam9261_lowlevel_init.o
lowlevel_init-$(CONFIG_SOC_AT91SAM9263) += at91sam9263_lowlevel_init.o
lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
@ -22,3 +27,4 @@ obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o

14
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -25,6 +25,9 @@
void at91_add_device_sdram(u32 size)
{
if (!size)
size = at91rm9200_get_sdram_size();
arm_add_mem_device("ram0", AT91_CHIPSELECT_1, size);
add_mem_device("sram0", AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE,
IORESOURCE_MEM_WRITEABLE);
@ -37,9 +40,18 @@ void at91_add_device_sdram(u32 size)
#if defined(CONFIG_USB_OHCI)
void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
{
int i;
if (!data)
return;
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i],
data->vbus_pin_active_low[i]);
}
add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91RM9200_UHP_BASE,
1024 * 1024, IORESOURCE_MEM, data);
}
@ -91,7 +103,7 @@ void __init at91_add_device_eth(int id, struct at91_ether_platform_data *data)
at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
if (!data->is_rmii) {
if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */

11
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -42,9 +42,18 @@ void at91_add_device_sdram(u32 size)
#if defined(CONFIG_USB_OHCI)
void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
{
int i;
if (!data)
return;
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i],
data->vbus_pin_active_low[i]);
}
add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9260_UHP_BASE,
1024 * 1024, IORESOURCE_MEM, data);
}
@ -89,7 +98,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data)
at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
if (!data->is_rmii) {
if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */

34
arch/arm/mach-at91/at91sam9260_lowlevel_init.c Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#define __LOWLEVEL_INIT__
#include <common.h>
#include <asm/system.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/at91_pio.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91_lowlevel_init.h>
#include <mach/io.h>
#include <init.h>
#include <sizes.h>
void __naked __bare_init reset(void)
{
common_reset();
arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);
at91sam926x_lowlevel_init(IOMEM(AT91SAM9260_BASE_PIOC), false,
AT91_MATRIX_EBICSA);
}

62
arch/arm/mach-at91/at91sam9261_devices.c
View File

@ -45,9 +45,18 @@ void at91_add_device_sdram(u32 size)
#if defined(CONFIG_USB_OHCI)
void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
{
int i;
if (!data)
return;
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i],
data->vbus_pin_active_low[i]);
}
add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9261_UHP_BASE,
1024 * 1024, IORESOURCE_MEM, data);
}
@ -199,6 +208,59 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
#endif
/* --------------------------------------------------------------------
* LCD Controller
* -------------------------------------------------------------------- */
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data)
{
BUG_ON(!data);
data->have_intensity_bit = true;
#if defined(CONFIG_FB_ATMEL_STN)
at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
#else
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
#endif
add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9261_LCDC_BASE, SZ_4K,
IORESOURCE_MEM, data);
}
#else
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {}
#endif
resource_size_t __init at91_configure_dbgu(void)
{
at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */

34
arch/arm/mach-at91/at91sam9261_lowlevel_init.c Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#define __LOWLEVEL_INIT__
#include <common.h>
#include <asm/system.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/at91_pio.h>
#include <mach/at91_rstc.h>
#include <mach/at91_wdt.h>
#include <mach/at91sam9_matrix.h>
#include <mach/at91sam9_sdramc.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91_lowlevel_init.h>
#include <mach/io.h>
#include <init.h>
#include <sizes.h>
void __naked __bare_init reset(void)
{
common_reset();
arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);
at91sam926x_lowlevel_init(IOMEM(AT91SAM9261_BASE_PIOC), false,
AT91_MATRIX_EBICSA);
}

1
arch/arm/mach-at91/at91sam9263.c
View File

@ -175,6 +175,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio3", &pioCDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio4", &pioCDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {

47
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -50,7 +50,8 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
/* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) {
if (gpio_is_valid(data->vbus_pin[i]))
at91_set_gpio_output(data->vbus_pin[i], 0);
at91_set_gpio_output(data->vbus_pin[i],
data->vbus_pin_active_low[i]);
}
add_generic_device("at91_ohci", DEVICE_ID_DYNAMIC, NULL, AT91SAM9263_UHP_BASE,
@ -96,7 +97,7 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data)
at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
if (!data->is_rmii) {
if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
@ -249,6 +250,48 @@ void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata)
void __init at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) {}
#endif
/* --------------------------------------------------------------------
* LCD Controller
* -------------------------------------------------------------------- */
#if defined(CONFIG_DRIVER_VIDEO_ATMEL)
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data)
{
BUG_ON(!data);
data->have_intensity_bit = true;
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9263_LCDC_BASE, SZ_4K,
IORESOURCE_MEM, data);
}
#else
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {}
#endif
resource_size_t __init at91_configure_dbgu(void)
{
at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */

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