ARM i.MX27: give register base addresses a proper MX27_ prefix
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
5455ecea55
commit
1d609aceae
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@ -223,13 +223,13 @@ device_initcall(eukrea_cpuimx27_devices_init);
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static int eukrea_cpuimx27_console_init(void)
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{
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#ifdef CONFIG_DRIVER_SERIAL_IMX
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imx_add_uart((void *)IMX_UART1_BASE, DEVICE_ID_DYNAMIC);
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imx27_add_uart0();
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#endif
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/* configure 8 bit UART on cs3 */
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FMCR &= ~0x2;
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imx27_setup_weimcs(3, 0x0000D603, 0x0D1D0D01, 0x00D20000);
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#ifdef CONFIG_DRIVER_SERIAL_NS16550
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add_ns16550_device(DEVICE_ID_DYNAMIC, IMX_CS3_BASE + QUART_OFFSET, 0xf,
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add_ns16550_device(DEVICE_ID_DYNAMIC, MX27_CS3_BASE_ADDR + QUART_OFFSET, 0xf,
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IORESOURCE_MEM_16BIT, &quad_uart_serial_plat);
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#endif
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return 0;
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@ -111,8 +111,8 @@ reset:
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =STACK_BASE + STACK_SIZE - 12 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
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ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */
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ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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@ -115,21 +115,21 @@ static void neso_usbh_init(void)
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{
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uint32_t temp;
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temp = readl(IMX_OTG_BASE + 0x600);
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temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
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temp &= ~((3 << 21) | 1);
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temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11);
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writel(temp, IMX_OTG_BASE + 0x600);
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writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600);
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temp = readl(IMX_OTG_BASE + 0x584);
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temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
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temp &= ~(3 << 30);
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temp |= 2 << 30;
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writel(temp, IMX_OTG_BASE + 0x584);
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writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584);
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mdelay(10);
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gpio_set_value(USBH2_PHY_CS_GPIO, 0);
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mdelay(10);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
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ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
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}
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#endif
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@ -276,7 +276,7 @@ static int neso_devices_init(void)
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#ifdef CONFIG_USB
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neso_usbh_init();
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
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#endif
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imx27_add_fec(&fec_info);
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@ -101,10 +101,10 @@ void __bare_init __naked reset(void)
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#ifdef CONFIG_NAND_IMX_BOOT
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/* skip NAND boot if not running from NFC space */
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r = get_pc();
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if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
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if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800)
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board_init_lowlevel_return();
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src = (unsigned int *)IMX_NFC_BASE;
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src = (unsigned int *)MX27_NFC_BASE_ADDR;
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trg = (unsigned int *)_text;
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/* Move ourselves out of NFC SRAM */
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@ -54,10 +54,10 @@ static int imx27ads_timing_init(void)
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imx27_setup_weimcs(0, 0x23524E80, 0x10000D03, 0x00720900);
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/* Select FEC data through data path */
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writew(0x0020, IMX_CS4_BASE + 0x10);
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writew(0x0020, MX27_CS4_BASE_ADDR + 0x10);
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/* Enable CPLD FEC data path */
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writew(0x0010, IMX_CS4_BASE + 0x14);
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writew(0x0010, MX27_CS4_BASE_ADDR + 0x14);
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return 0;
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}
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@ -106,10 +106,10 @@ void __bare_init __naked reset(void)
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#ifdef CONFIG_NAND_IMX_BOOT
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/* skip NAND boot if not running from NFC space */
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r = get_pc();
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if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
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if (r < MX27_NFC_BASE_ADDR || r > MX27_NFC_BASE_ADDR + 0x800)
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board_init_lowlevel_return();
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src = (unsigned int *)IMX_NFC_BASE;
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src = (unsigned int *)MX27_NFC_BASE_ADDR;
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trg = (unsigned int *)_text;
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/* Move ourselves out of NFC SRAM */
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@ -31,28 +31,28 @@ static void pcm970_usbh2_init(void)
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{
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uint32_t temp;
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temp = readl(IMX_OTG_BASE + 0x600);
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temp = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
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temp &= ~((3 << 21) | 1);
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temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20);
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writel(temp, IMX_OTG_BASE + 0x600);
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writel(temp, MX27_USB_OTG_BASE_ADDR + 0x600);
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temp = readl(IMX_OTG_BASE + 0x584);
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temp = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
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temp &= ~(3 << 30);
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temp |= 2 << 30;
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writel(temp, IMX_OTG_BASE + 0x584);
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writel(temp, MX27_USB_OTG_BASE_ADDR + 0x584);
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mdelay(10);
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if (!ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1))
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
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if (!ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1))
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
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}
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#endif
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#ifdef CONFIG_DISK_INTF_PLATFORM_IDE
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static struct resource pcm970_ide_resources[] = {
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{
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.start = IMX_PCMCIA_MEM_BASE,
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.end = IMX_PCMCIA_MEM_BASE + SZ_1K - 1,
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.start = MX27_PCMCIA_MEM_BASE_ADDR,
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.end = MX27_PCMCIA_MEM_BASE_ADDR + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -96,8 +96,8 @@ reset:
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#ifdef CONFIG_NAND_IMX_BOOT
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ldr sp, =0xa0f00000 /* Setup a temporary stack in SDRAM */
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ldr r0, =IMX_NFC_BASE /* start of NFC SRAM */
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ldr r2, =IMX_NFC_BASE + 0x1000 /* end of NFC SRAM */
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ldr r0, =MX27_NFC_BASE_ADDR /* start of NFC SRAM */
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ldr r2, =MX27_NFC_BASE_ADDR + 0x1000 /* end of NFC SRAM */
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/* skip NAND boot if not running from NFC space */
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cmp pc, r0
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@ -136,10 +136,10 @@ static void pca100_usb_register(void)
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mdelay(10);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x170), 1);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE, NULL);
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ulpi_setup((void *)(IMX_OTG_BASE + 0x570), 1);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, IMX_OTG_BASE + 0x400, NULL);
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ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x170), 1);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR, NULL);
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ulpi_setup((void *)(MX27_USB_OTG_BASE_ADDR + 0x570), 1);
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add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
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}
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#endif
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@ -155,10 +155,10 @@ static void pca100_usb_init(void)
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{
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u32 reg;
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reg = readl(IMX_OTG_BASE + 0x600);
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reg = readl(MX27_USB_OTG_BASE_ADDR + 0x600);
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reg &= ~((3 << 21) | 1);
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reg |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 11) | (1 << 20);
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writel(reg, IMX_OTG_BASE + 0x600);
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writel(reg, MX27_USB_OTG_BASE_ADDR + 0x600);
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/*
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* switch usbotg and usbh2 to ulpi mode. Do this *before*
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@ -166,15 +166,15 @@ static void pca100_usb_init(void)
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* triggering. Also, do this even when USB support is
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* disabled to give Linux USB support a good start.
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*/
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reg = readl(IMX_OTG_BASE + 0x584);
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reg = readl(MX27_USB_OTG_BASE_ADDR + 0x584);
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reg &= ~(3 << 30);
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reg |= 2 << 30;
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writel(reg, IMX_OTG_BASE + 0x584);
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writel(reg, MX27_USB_OTG_BASE_ADDR + 0x584);
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reg = readl(IMX_OTG_BASE + 0x184);
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reg = readl(MX27_USB_OTG_BASE_ADDR + 0x184);
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reg &= ~(3 << 30);
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reg |= 2 << 30;
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writel(reg, IMX_OTG_BASE + 0x184);
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writel(reg, MX27_USB_OTG_BASE_ADDR + 0x184);
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/* disable the usb phys */
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imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN);
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@ -122,7 +122,7 @@ static int __maybe_unused is_pagesize_2k(void)
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return 0;
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#endif
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#ifdef CONFIG_ARCH_IMX27
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if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5))
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if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
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return 1;
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else
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return 0;
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@ -43,7 +43,7 @@ int imx_silicon_revision(void)
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static void imx27_init_max(void)
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{
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void __iomem *max_base = (void *)IMX_MAX_BASE;
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void __iomem *max_base = (void *)MX27_MAX_BASE_ADDR;
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u32 val;
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/* 0 is the highest priority */
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@ -64,18 +64,18 @@ static void imx27_init_max(void)
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static int imx27_init(void)
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{
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add_generic_device("imx_iim", 0, NULL, IMX_IIM_BASE, SZ_4K,
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add_generic_device("imx_iim", 0, NULL, MX27_IIM_BASE_ADDR, SZ_4K,
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IORESOURCE_MEM, NULL);
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imx27_init_max();
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add_generic_device("imx1-gpt", 0, NULL, 0x10003000, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 0, NULL, 0x10015000, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 1, NULL, 0x10015100, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 2, NULL, 0x10015200, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 3, NULL, 0x10015300, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 4, NULL, 0x10015400, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 5, NULL, 0x10015500, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpt", 0, NULL, MX27_GPT1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 0, NULL, MX27_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 1, NULL, MX27_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 2, NULL, MX27_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 3, NULL, MX27_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 4, NULL, MX27_GPIO5_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 5, NULL, MX27_GPIO6_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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return 0;
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}
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console_initcall(imx27_init);
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@ -3,70 +3,70 @@
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static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata);
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return imx_add_spi((void *)MX27_CSPI1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx27_add_spi1(struct spi_imx_master *pdata)
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{
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return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata);
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return imx_add_spi((void *)MX27_CSPI2_BASE_ADDR, 1, pdata);
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}
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static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata)
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{
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return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata);
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return imx_add_i2c((void *)MX27_I2C1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx27_add_i2c1(struct i2c_platform_data *pdata)
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{
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return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata);
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return imx_add_i2c((void *)MX27_I2C2_BASE_ADDR, 1, pdata);
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}
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static inline struct device_d *imx27_add_uart0(void)
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{
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return imx_add_uart((void *)IMX_UART1_BASE, 0);
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return imx_add_uart((void *)MX27_UART1_BASE_ADDR, 0);
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}
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static inline struct device_d *imx27_add_uart1(void)
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{
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return imx_add_uart((void *)IMX_UART2_BASE, 1);
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return imx_add_uart((void *)MX27_UART2_BASE_ADDR, 1);
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}
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static inline struct device_d *imx27_add_uart2(void)
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{
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return imx_add_uart((void *)IMX_UART3_BASE, 2);
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return imx_add_uart((void *)MX27_UART3_BASE_ADDR, 2);
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}
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static inline struct device_d *imx27_add_uart3(void)
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{
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return imx_add_uart((void *)IMX_UART4_BASE, 3);
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return imx_add_uart((void *)MX27_UART4_BASE_ADDR, 3);
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}
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static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata)
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{
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return imx_add_nand((void *)IMX_NFC_BASE, pdata);
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return imx_add_nand((void *)MX27_NFC_BASE_ADDR, pdata);
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}
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static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata)
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{
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return imx_add_fb((void *)IMX_FB_BASE, pdata);
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return imx_add_fb((void *)MX27_LCDC_BASE_ADDR, pdata);
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}
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static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata)
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{
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return imx_add_fec((void *)IMX_FEC_BASE, pdata);
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return imx_add_fec((void *)MX27_FEC_BASE_ADDR, pdata);
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}
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static inline struct device_d *imx27_add_mmc0(void *pdata)
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{
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return imx_add_mmc((void *)IMX_SDHC1_BASE, 0, pdata);
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return imx_add_mmc((void *)MX27_SDHC1_BASE_ADDR, 0, pdata);
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}
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static inline struct device_d *imx27_add_mmc1(void *pdata)
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{
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return imx_add_mmc((void *)IMX_SDHC2_BASE, 1, pdata);
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return imx_add_mmc((void *)MX27_SDHC2_BASE_ADDR, 1, pdata);
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}
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static inline struct device_d *imx27_add_mmc2(void *pdata)
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{
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return imx_add_mmc((void *)IMX_SDHC3_BASE, 2, pdata);
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return imx_add_mmc((void *)MX27_SDHC3_BASE_ADDR, 2, pdata);
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}
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@ -5,66 +5,133 @@
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#error "Please do not include directly"
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#endif
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#define IMX_IO_BASE 0x10000000
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#define MX27_AIPI_BASE_ADDR 0x10000000
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#define MX27_AIPI_SIZE SZ_1M
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#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
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#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
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#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
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#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
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#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
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#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
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#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
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#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
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#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
|
||||
#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
|
||||
#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
|
||||
#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
|
||||
#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
|
||||
#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
|
||||
#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
|
||||
#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
|
||||
#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
|
||||
#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
|
||||
#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
|
||||
#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
|
||||
#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
|
||||
#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
|
||||
#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
|
||||
#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
|
||||
#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
|
||||
#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
|
||||
#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
|
||||
#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
|
||||
#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
|
||||
#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
|
||||
#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
|
||||
#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
|
||||
#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
|
||||
#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
|
||||
#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
|
||||
#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
|
||||
#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
|
||||
#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
|
||||
#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
|
||||
#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
|
||||
#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
|
||||
#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
|
||||
#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
|
||||
#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
|
||||
#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
|
||||
#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
|
||||
#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
|
||||
#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
|
||||
#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
|
||||
#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
|
||||
#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
|
||||
#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
|
||||
#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
|
||||
#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
|
||||
#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
|
||||
#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
|
||||
#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
|
||||
|
||||
#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
|
||||
#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE)
|
||||
#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE)
|
||||
#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE)
|
||||
#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE)
|
||||
#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
|
||||
#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
|
||||
#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
|
||||
#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
|
||||
#define IMX_SPI1_BASE (0x0e000 + IMX_IO_BASE)
|
||||
#define IMX_SPI2_BASE (0x0f000 + IMX_IO_BASE)
|
||||
#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
|
||||
#define IMX_SDHC1_BASE (0x13000 + IMX_IO_BASE)
|
||||
#define IMX_SDHC2_BASE (0x14000 + IMX_IO_BASE)
|
||||
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
|
||||
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
|
||||
#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
|
||||
#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
|
||||
#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
|
||||
#define IMX_I2C2_BASE (0x1d000 + IMX_IO_BASE)
|
||||
#define IMX_SDHC3_BASE (0x1e000 + IMX_IO_BASE)
|
||||
#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
|
||||
#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
|
||||
#define IMX_FB_BASE (0x21000 + IMX_IO_BASE)
|
||||
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
|
||||
#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
|
||||
#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE)
|
||||
#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE)
|
||||
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
|
||||
#define IMX_MAX_BASE (0x3f000 + IMX_IO_BASE)
|
||||
#define MX27_AVIC_BASE_ADDR 0x10040000
|
||||
|
||||
#define IMX_NFC_BASE (0xd8000000)
|
||||
#define IMX_ESD_BASE (0xd8001000)
|
||||
#define IMX_WEIM_BASE (0xd8002000)
|
||||
#define IMX_M3IF_BASE (0xd8003000)
|
||||
#define IMX_PCMCIA_CTL_BASE (0xd8004000)
|
||||
/* ROM patch */
|
||||
#define MX27_ROMP_BASE_ADDR 0x10041000
|
||||
|
||||
#define PCMCIA_PIPR (IMX_PCMCIA_CTL_BASE + 0x00)
|
||||
#define PCMCIA_PSCR (IMX_PCMCIA_CTL_BASE + 0x04)
|
||||
#define PCMCIA_PER (IMX_PCMCIA_CTL_BASE + 0x08)
|
||||
#define PCMCIA_PBR(x) (IMX_PCMCIA_CTL_BASE + 0x0c + ((x) << 2))
|
||||
#define PCMCIA_POR(x) (IMX_PCMCIA_CTL_BASE + 0x28 + ((x) << 2))
|
||||
#define PCMCIA_POFR(x) (IMX_PCMCIA_CTL_BASE + 0x44 + ((x) << 2))
|
||||
#define PCMCIA_PGCR (IMX_PCMCIA_CTL_BASE + 0x60)
|
||||
#define PCMCIA_PGSR (IMX_PCMCIA_CTL_BASE + 0x64)
|
||||
#define MX27_SAHB1_BASE_ADDR 0x80000000
|
||||
#define MX27_SAHB1_SIZE SZ_1M
|
||||
#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
|
||||
#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
|
||||
|
||||
/* Memory regions and CS */
|
||||
#define MX27_CSD0_BASE_ADDR 0xa0000000
|
||||
#define MX27_CSD1_BASE_ADDR 0xb0000000
|
||||
|
||||
#define MX27_CS0_BASE_ADDR 0xc0000000
|
||||
#define MX27_CS1_BASE_ADDR 0xc8000000
|
||||
#define MX27_CS2_BASE_ADDR 0xd0000000
|
||||
#define MX27_CS3_BASE_ADDR 0xd2000000
|
||||
#define MX27_CS4_BASE_ADDR 0xd4000000
|
||||
#define MX27_CS5_BASE_ADDR 0xd6000000
|
||||
|
||||
/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
|
||||
#define MX27_X_MEMC_BASE_ADDR 0xd8000000
|
||||
#define MX27_X_MEMC_SIZE SZ_1M
|
||||
#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
|
||||
#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
|
||||
#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
|
||||
#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
|
||||
#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
|
||||
|
||||
#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
|
||||
#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
|
||||
#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
|
||||
#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
|
||||
|
||||
#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
|
||||
|
||||
/* IRAM */
|
||||
#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
|
||||
|
||||
/* FIXME: get rid of these */
|
||||
#define IMX_GPIO_BASE MX27_GPIO_BASE_ADDR
|
||||
#define IMX_NFC_BASE MX27_NFC_BASE_ADDR
|
||||
#define IMX_WDT_BASE MX27_WDOG_BASE_ADDR
|
||||
#define IMX_ESD_BASE MX27_SDRAMC_BASE_ADDR
|
||||
|
||||
#define PCMCIA_PIPR (MX27_PCMCIA_CTL_BASE_ADDR + 0x00)
|
||||
#define PCMCIA_PSCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x04)
|
||||
#define PCMCIA_PER (MX27_PCMCIA_CTL_BASE_ADDR + 0x08)
|
||||
#define PCMCIA_PBR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x0c + ((x) << 2))
|
||||
#define PCMCIA_POR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x28 + ((x) << 2))
|
||||
#define PCMCIA_POFR(x) (MX27_PCMCIA_CTL_BASE_ADDR + 0x44 + ((x) << 2))
|
||||
#define PCMCIA_PGCR (MX27_PCMCIA_CTL_BASE_ADDR + 0x60)
|
||||
#define PCMCIA_PGSR (MX27_PCMCIA_CTL_BASE_ADDR + 0x64)
|
||||
|
||||
/* AIPI */
|
||||
#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00)
|
||||
#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04)
|
||||
#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00)
|
||||
#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04)
|
||||
#define AIPI1_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x00)
|
||||
#define AIPI1_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x04)
|
||||
#define AIPI2_PSR0 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x00)
|
||||
#define AIPI2_PSR1 __REG(MX27_AIPI_BASE_ADDR + 0x20000 + 0x04)
|
||||
|
||||
/* System Control */
|
||||
#define CID __REG(IMX_SYSTEM_CTL_BASE + 0x0) /* Chip ID Register */
|
||||
#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14) /* Function Multeplexing Control Register */
|
||||
#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18) /* Global Peripheral Control Register */
|
||||
#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C) /* Well Bias Control Register */
|
||||
#define DSCR(x) __REG(IMX_SYSTEM_CTL_BASE + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
|
||||
#define CID __REG(MX27_SYSCTRL_BASE_ADDR + 0x0) /* Chip ID Register */
|
||||
#define FMCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x14) /* Function Multeplexing Control Register */
|
||||
#define GPCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x18) /* Global Peripheral Control Register */
|
||||
#define WBCR __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C) /* Well Bias Control Register */
|
||||
#define DSCR(x) __REG(MX27_SYSCTRL_BASE_ADDR + 0x1C + ((x) << 2)) /* Driving Strength Control Register 1 - 13 */
|
||||
|
||||
#define GPCR_BOOT_SHIFT 16
|
||||
#define GPCR_BOOT_MASK (0xf << GPCR_BOOT_SHIFT)
|
||||
|
|
@ -76,26 +143,20 @@
|
|||
#define GPCR_BOOT_32BIT_CS0 6
|
||||
#define GPCR_BOOT_8BIT_NAND_512 7
|
||||
|
||||
/* Chip Select Registers */
|
||||
#define CSxU(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x00) /* Chip Select x Upper Register */
|
||||
#define CSxL(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x04) /* Chip Select x Lower Register */
|
||||
#define CSxA(x) __REG(IMX_WEIM_BASE + (cs * 0x10) + 0x08) /* Chip Select x Addition Register */
|
||||
#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */
|
||||
|
||||
#include "esdctl.h"
|
||||
|
||||
/* PLL registers */
|
||||
#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
|
||||
#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
|
||||
#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */
|
||||
#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */
|
||||
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
|
||||
#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */
|
||||
#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */
|
||||
#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */
|
||||
#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */
|
||||
#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */
|
||||
#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */
|
||||
#define CSCR __REG(MX27_CCM_BASE_ADDR + 0x00) /* Clock Source Control Register */
|
||||
#define MPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x04) /* MCU PLL Control Register 0 */
|
||||
#define MPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x08) /* MCU PLL Control Register 1 */
|
||||
#define SPCTL0 __REG(MX27_CCM_BASE_ADDR + 0x0c) /* System PLL Control Register 0 */
|
||||
#define SPCTL1 __REG(MX27_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
|
||||
#define OSC26MCTL __REG(MX27_CCM_BASE_ADDR + 0x14) /* Oscillator 26M Register */
|
||||
#define PCDR0 __REG(MX27_CCM_BASE_ADDR + 0x18) /* Peripheral Clock Divider Register 0 */
|
||||
#define PCDR1 __REG(MX27_CCM_BASE_ADDR + 0x1c) /* Peripheral Clock Divider Register 1 */
|
||||
#define PCCR0 __REG(MX27_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Control Register 0 */
|
||||
#define PCCR1 __REG(MX27_CCM_BASE_ADDR + 0x24) /* Peripheral Clock Control Register 1 */
|
||||
#define CCSR __REG(MX27_CCM_BASE_ADDR + 0x28) /* Clock Control Status Register */
|
||||
|
||||
#define CSCR_MPEN (1 << 0)
|
||||
#define CSCR_SPEN (1 << 1)
|
||||
|
|
@ -221,21 +282,13 @@
|
|||
#define ESDCFG_TWTR (1 << 20)
|
||||
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
|
||||
|
||||
#define IMX_CS0_BASE 0xC0000000
|
||||
#define IMX_CS1_BASE 0xC8000000
|
||||
#define IMX_CS2_BASE 0xD0000000
|
||||
#define IMX_CS3_BASE 0xD2000000
|
||||
#define IMX_CS4_BASE 0xD4000000
|
||||
#define IMX_CS5_BASE 0xD6000000
|
||||
|
||||
#define IMX_PCMCIA_MEM_BASE (0xdc000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned addional)
|
||||
#include <io.h>
|
||||
static inline void imx27_setup_weimcs(size_t cs, unsigned upper, unsigned lower, unsigned additional)
|
||||
{
|
||||
CSxU(cs) = upper;
|
||||
CSxL(cs) = lower;
|
||||
CSxA(cs) = addional;
|
||||
writel(upper, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x0);
|
||||
writel(lower, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
|
||||
writel(additional, MX27_WEIM_BASE_ADDR + (cs * 0x10) + 0x4);
|
||||
}
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue