* Patches by Robert Whaley, 29 Nov 2004:
- update the pxa-regs.h file for PXA27x chips - add PXA27x based ADSVIX board - add support for MMC on PXA27x processors * Patch by Andrew E. Mileski, 28 Nov 2004: Fix PPC4xx SPD SDRAM detection bug * Patch by Hiroshi Ito, 26 Nov 2004: Fix logic of "test -z" and "test -n" commands
This commit is contained in:
wdenk
parent
3c2b3d454d
commit
20787e23b8
11
CHANGELOG
11
CHANGELOG
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@ -2,6 +2,17 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patches by Robert Whaley, 29 Nov 2004:
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- update the pxa-regs.h file for PXA27x chips
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- add PXA27x based ADSVIX board
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- add support for MMC on PXA27x processors
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* Patch by Andrew E. Mileski, 28 Nov 2004:
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Fix PPC4xx SPD SDRAM detection bug
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* Patch by Hiroshi Ito, 26 Nov 2004:
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Fix logic of "test -z" and "test -n" commands
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* Patch by Ladislav Michl, 05 Apr 2005:
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Add support for VoiceBlue board.
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|
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4
CREDITS
4
CREDITS
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@ -402,6 +402,10 @@ N: Christian Vejlbo
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E: christian.vejlbo@tellabs.com
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D: FADS860T ethernet support
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N: Robert Whaley
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E: rwhaley@applieddata.net
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D: Port to ARM PXA27x adsvix SBC
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N: Martin Winistoerfer
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E: martinwinistoerfer@gmx.ch
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D: Port to MPC555/556 microcontrollers and support for cmi board
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6
MAKEALL
6
MAKEALL
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@ -170,9 +170,9 @@ LIST_ARM11="omap2420h4"
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#########################################################################
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LIST_pxa=" \
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cerf250 cradle csb226 innokom \
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lubbock wepep250 xaeniax xm250 \
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xsengine \
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adsvix cerf250 cradle csb226 \
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innokom lubbock wepep250 xaeniax \
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xm250 xsengine \
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"
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LIST_ixp="ixdp425"
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3
Makefile
3
Makefile
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@ -1432,6 +1432,9 @@ cmc_pu2_config : unconfig
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## XScale Systems
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#########################################################################
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adsvix_config : unconfig
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@./mkconfig $(@:_config=) arm pxa adsvix
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cerf250_config : unconfig
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@./mkconfig $(@:_config=) arm pxa cerf250
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|
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@ -0,0 +1,48 @@
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#
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# (C) Copyright 2000
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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||||
# published by the Free Software Foundation; either version 2 of
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||||
# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
# GNU General Public License for more details.
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||||
#
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||||
# You should have received a copy of the GNU General Public License
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||||
# along with this program; if not, write to the Free Software
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||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := adsvix.o pcmcia.o
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SOBJS := memsetup.o pxavoltage.o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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@ -0,0 +1,77 @@
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/*
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* (C) Copyright 2004
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* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* arch number of ADSVIX-Board */
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gd->bd->bi_arch_number = 620;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa000003c;
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return 0;
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}
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int board_late_init(void)
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{
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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return 0;
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}
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int dram_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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return 0;
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}
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@ -0,0 +1 @@
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TEXT_BASE = 0xa1700000
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@ -0,0 +1,468 @@
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/*
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* This was originally from the Lubbock u-boot port.
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*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* NOTE: I haven't clean this up considerably, just enough to get it
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* running. See hal_platform_setup.h for the source. See
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* board/cradle/memsetup.S for another PXA250 setup that is
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* much cleaner.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
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||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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/*
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* Memory setup
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*/
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.globl memsetup
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memsetup:
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/* Set up GPIO pins first ----------------------------------------- */
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ldr r0, =GPSR0
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ldr r1, =CFG_GPSR0_VAL
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str r1, [r0]
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ldr r0, =GPSR1
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ldr r1, =CFG_GPSR1_VAL
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str r1, [r0]
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ldr r0, =GPSR2
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ldr r1, =CFG_GPSR2_VAL
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str r1, [r0]
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ldr r0, =GPSR3
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ldr r1, =CFG_GPSR3_VAL
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str r1, [r0]
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ldr r0, =GPCR0
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ldr r1, =CFG_GPCR0_VAL
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str r1, [r0]
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ldr r0, =GPCR1
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ldr r1, =CFG_GPCR1_VAL
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str r1, [r0]
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ldr r0, =GPCR2
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ldr r1, =CFG_GPCR2_VAL
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str r1, [r0]
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ldr r0, =GPCR3
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ldr r1, =CFG_GPCR3_VAL
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str r1, [r0]
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ldr r0, =GPDR0
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ldr r1, =CFG_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CFG_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CFG_GPDR2_VAL
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str r1, [r0]
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|
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ldr r0, =GPDR3
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ldr r1, =CFG_GPDR3_VAL
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str r1, [r0]
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|
||||
ldr r0, =GAFR0_L
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ldr r1, =CFG_GAFR0_L_VAL
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str r1, [r0]
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|
||||
ldr r0, =GAFR0_U
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ldr r1, =CFG_GAFR0_U_VAL
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str r1, [r0]
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|
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ldr r0, =GAFR1_L
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ldr r1, =CFG_GAFR1_L_VAL
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str r1, [r0]
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ldr r0, =GAFR1_U
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ldr r1, =CFG_GAFR1_U_VAL
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str r1, [r0]
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|
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ldr r0, =GAFR2_L
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ldr r1, =CFG_GAFR2_L_VAL
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str r1, [r0]
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||||
|
||||
ldr r0, =GAFR2_U
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||||
ldr r1, =CFG_GAFR2_U_VAL
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str r1, [r0]
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||||
|
||||
ldr r0, =GAFR3_L
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||||
ldr r1, =CFG_GAFR3_L_VAL
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||||
str r1, [r0]
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||||
|
||||
ldr r0, =GAFR3_U
|
||||
ldr r1, =CFG_GAFR3_U_VAL
|
||||
str r1, [r0]
|
||||
|
||||
ldr r0, =PSSR /* enable GPIO pins */
|
||||
ldr r1, =CFG_PSSR_VAL
|
||||
str r1, [r0]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Enable memory interface */
|
||||
/* */
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||||
/* The sequence below is based on the recommended init steps */
|
||||
/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
|
||||
/* Chapter 10. */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 1: Wait for at least 200 microsedonds to allow internal */
|
||||
/* clocks to settle. Only necessary after hard reset... */
|
||||
/* FIXME: can be optimized later */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
|
||||
/* so 0x300 should be plenty */
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
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||||
|
||||
mem_init:
|
||||
|
||||
ldr r1, =MEMC_BASE /* get memory controller base addr. */
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2a: Initialize Asynchronous static memory controller */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* MSC registers: timing, bus width, mem type */
|
||||
|
||||
/* MSC0: nCS(0,1) */
|
||||
ldr r2, =CFG_MSC0_VAL
|
||||
str r2, [r1, #MSC0_OFFSET]
|
||||
ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
|
||||
/* that data latches */
|
||||
/* MSC1: nCS(2,3) */
|
||||
ldr r2, =CFG_MSC1_VAL
|
||||
str r2, [r1, #MSC1_OFFSET]
|
||||
ldr r2, [r1, #MSC1_OFFSET]
|
||||
|
||||
/* MSC2: nCS(4,5) */
|
||||
ldr r2, =CFG_MSC2_VAL
|
||||
str r2, [r1, #MSC2_OFFSET]
|
||||
ldr r2, [r1, #MSC2_OFFSET]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2b: Initialize Card Interface */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* MECR: Memory Expansion Card Register */
|
||||
ldr r2, =CFG_MECR_VAL
|
||||
str r2, [r1, #MECR_OFFSET]
|
||||
ldr r2, [r1, #MECR_OFFSET]
|
||||
|
||||
/* MCMEM0: Card Interface slot 0 timing */
|
||||
ldr r2, =CFG_MCMEM0_VAL
|
||||
str r2, [r1, #MCMEM0_OFFSET]
|
||||
ldr r2, [r1, #MCMEM0_OFFSET]
|
||||
|
||||
/* MCMEM1: Card Interface slot 1 timing */
|
||||
ldr r2, =CFG_MCMEM1_VAL
|
||||
str r2, [r1, #MCMEM1_OFFSET]
|
||||
ldr r2, [r1, #MCMEM1_OFFSET]
|
||||
|
||||
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
|
||||
ldr r2, =CFG_MCATT0_VAL
|
||||
str r2, [r1, #MCATT0_OFFSET]
|
||||
ldr r2, [r1, #MCATT0_OFFSET]
|
||||
|
||||
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
|
||||
ldr r2, =CFG_MCATT1_VAL
|
||||
str r2, [r1, #MCATT1_OFFSET]
|
||||
ldr r2, [r1, #MCATT1_OFFSET]
|
||||
|
||||
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
|
||||
ldr r2, =CFG_MCIO0_VAL
|
||||
str r2, [r1, #MCIO0_OFFSET]
|
||||
ldr r2, [r1, #MCIO0_OFFSET]
|
||||
|
||||
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
|
||||
ldr r2, =CFG_MCIO1_VAL
|
||||
str r2, [r1, #MCIO1_OFFSET]
|
||||
ldr r2, [r1, #MCIO1_OFFSET]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2c: Write FLYCNFG FIXME: what's that??? */
|
||||
/* ---------------------------------------------------------------- */
|
||||
ldr r2, =CFG_FLYCNFG_VAL
|
||||
str r2, [r1, #FLYCNFG_OFFSET]
|
||||
str r2, [r1, #FLYCNFG_OFFSET]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* Before accessing MDREFR we need a valid DRI field, so we set */
|
||||
/* this to power on defaults + DRI field. */
|
||||
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r2, =0xFFF
|
||||
bic r4, r4, r2
|
||||
|
||||
ldr r3, =CFG_MDREFR_VAL
|
||||
and r3, r3, r2
|
||||
|
||||
orr r4, r4, r3
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
|
||||
|
||||
orr r4, r4, #MDREFR_K0RUN
|
||||
orr r4, r4, #MDREFR_K0DB4
|
||||
orr r4, r4, #MDREFR_K0FREE
|
||||
orr r4, r4, #MDREFR_K0DB2
|
||||
orr r4, r4, #MDREFR_K1DB2
|
||||
bic r4, r4, #MDREFR_K1FREE
|
||||
bic r4, r4, #MDREFR_K2FREE
|
||||
|
||||
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
/* Note: preserve the mdrefr value in r4 */
|
||||
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
/* Initialize SXCNFG register. Assert the enable bits */
|
||||
|
||||
/* Write SXMRS to cause an MRS command to all enabled banks of */
|
||||
/* synchronous static memory. Note that SXLCR need not be written */
|
||||
/* at this time. */
|
||||
|
||||
ldr r2, =CFG_SXCNFG_VAL
|
||||
str r2, [r1, #SXCNFG_OFFSET]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Step 4: Initialize SDRAM */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
|
||||
|
||||
orr r4, r4, #MDREFR_K1RUN
|
||||
bic r4, r4, #MDREFR_K2DB2
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
bic r4, r4, #MDREFR_SLFRSH
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
orr r4, r4, #MDREFR_E1PIN
|
||||
str r4, [r1, #MDREFR_OFFSET]
|
||||
ldr r4, [r1, #MDREFR_OFFSET]
|
||||
|
||||
nop
|
||||
nop
|
||||
|
||||
|
||||
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
|
||||
/* configure but not enable each SDRAM partition pair. */
|
||||
|
||||
ldr r4, =CFG_MDCNFG_VAL
|
||||
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
|
||||
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
|
||||
|
||||
str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
|
||||
ldr r4, [r1, #MDCNFG_OFFSET]
|
||||
|
||||
|
||||
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
|
||||
/* 100..200 µsec. */
|
||||
|
||||
ldr r3, =OSCR /* reset the OS Timer Count to zero */
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
|
||||
/* so 0x300 should be plenty */
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r4, r2
|
||||
bgt 1b
|
||||
|
||||
|
||||
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
|
||||
/* attempting non-burst read or write accesses to disabled */
|
||||
/* SDRAM, as commonly specified in the power up sequence */
|
||||
/* documented in SDRAM data sheets. The address(es) used */
|
||||
/* for this purpose must not be cacheable. */
|
||||
|
||||
ldr r3, =CFG_DRAM_BASE
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
str r2, [r3]
|
||||
|
||||
|
||||
/* Step 4g: Write MDCNFG with enable bits asserted */
|
||||
/* (MDCNFG:DEx set to 1). */
|
||||
|
||||
ldr r3, [r1, #MDCNFG_OFFSET]
|
||||
mov r4, r3
|
||||
orr r3, r3, #MDCNFG_DE0
|
||||
str r3, [r1, #MDCNFG_OFFSET]
|
||||
mov r0, r3
|
||||
|
||||
/* Step 4h: Write MDMRS. */
|
||||
|
||||
ldr r2, =CFG_MDMRS_VAL
|
||||
str r2, [r1, #MDMRS_OFFSET]
|
||||
|
||||
/* enable APD */
|
||||
ldr r3, [r1, #MDREFR_OFFSET]
|
||||
orr r3, r3, #MDREFR_APD
|
||||
str r3, [r1, #MDREFR_OFFSET]
|
||||
|
||||
/* We are finished with Intel's memory controller initialisation */
|
||||
|
||||
setvoltage:
|
||||
|
||||
mov r10, lr
|
||||
bl initPXAvoltage /* In case the board is rebooting with a */
|
||||
mov lr, r10 /* low voltage raise it up to a good one. */
|
||||
|
||||
wakeup:
|
||||
/* Are we waking from sleep? */
|
||||
ldr r0, =RCSR
|
||||
ldr r1, [r0]
|
||||
and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
|
||||
str r1, [r0]
|
||||
teq r1, #RCSR_SMR
|
||||
|
||||
bne initirqs
|
||||
|
||||
ldr r0, =PSSR
|
||||
mov r1, #PSSR_PH
|
||||
str r1, [r0]
|
||||
|
||||
/* if so, resume at PSPR */
|
||||
ldr r0, =PSPR
|
||||
ldr r1, [r0]
|
||||
mov pc, r1
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Disable (mask) all interrupts at interrupt controller */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
initirqs:
|
||||
|
||||
mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
|
||||
ldr r2, =ICLR
|
||||
str r1, [r2]
|
||||
|
||||
ldr r2, =ICMR /* mask all interrupts at the controller */
|
||||
str r1, [r2]
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* Clock initialisation */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
initclks:
|
||||
|
||||
/* Disable the peripheral clocks, and set the core clock frequency */
|
||||
|
||||
/* Turn Off on-chip peripheral clocks (except for memory) */
|
||||
/* for re-configuration. */
|
||||
ldr r1, =CKEN
|
||||
ldr r2, =CFG_CKEN
|
||||
str r2, [r1]
|
||||
|
||||
/* ... and write the core clock config register */
|
||||
ldr r2, =CFG_CCCR
|
||||
ldr r1, =CCCR
|
||||
str r2, [r1]
|
||||
|
||||
/* Turn on turbo mode */
|
||||
mrc p14, 0, r2, c6, c0, 0
|
||||
orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/
|
||||
mcr p14, 0, r2, c6, c0, 0
|
||||
|
||||
/* Re-write MDREFR */
|
||||
ldr r1, =MEMC_BASE
|
||||
ldr r2, [r1, #MDREFR_OFFSET]
|
||||
str r2, [r1, #MDREFR_OFFSET]
|
||||
#ifdef RTC
|
||||
/* enable the 32Khz oscillator for RTC and PowerManager */
|
||||
ldr r1, =OSCC
|
||||
mov r2, #OSCC_OON
|
||||
str r2, [r1]
|
||||
|
||||
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
|
||||
/* has settled. */
|
||||
60:
|
||||
ldr r2, [r1]
|
||||
ands r2, r2, #1
|
||||
beq 60b
|
||||
#else
|
||||
#error "RTC not defined"
|
||||
#endif
|
||||
|
||||
/* Interrupt init: Mask all interrupts */
|
||||
ldr r0, =ICMR /* enable no sources */
|
||||
mov r1, #0
|
||||
str r1, [r0]
|
||||
/* FIXME */
|
||||
|
||||
// #define NODEBUG
|
||||
#ifdef NODEBUG
|
||||
/*Disable software and data breakpoints */
|
||||
mov r0,#0
|
||||
mcr p15,0,r0,c14,c8,0 /* ibcr0 */
|
||||
mcr p15,0,r0,c14,c9,0 /* ibcr1 */
|
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */
|
||||
|
||||
/*Enable all debug functionality */
|
||||
mov r0,#0x80000000
|
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */
|
||||
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* End memsetup */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
endmemsetup:
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
void pcmcia_power_on(void)
|
||||
{
|
||||
#if 0
|
||||
if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
|
||||
GPCR(81) = GPIO_bit(81);
|
||||
GPSR(82) = GPIO_bit(82);
|
||||
}
|
||||
else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
|
||||
GPCR(81) = GPIO_bit(81);
|
||||
GPCR(82) = GPIO_bit(82);
|
||||
}
|
||||
#else
|
||||
#warning "Board will only supply 5V, wait for next HW spin for selectable power"
|
||||
/* 5.0V */
|
||||
GPCR(81) = GPIO_bit(81);
|
||||
GPCR(82) = GPIO_bit(82);
|
||||
#endif
|
||||
|
||||
udelay(300000);
|
||||
|
||||
/* reset the card */
|
||||
GPSR(52) = GPIO_bit(52);
|
||||
|
||||
/* enable PCMCIA */
|
||||
GPCR(83) = GPIO_bit(83);
|
||||
|
||||
/* clear reset */
|
||||
udelay(10);
|
||||
GPCR(52) = GPIO_bit(52);
|
||||
|
||||
udelay(20000);
|
||||
}
|
||||
|
||||
void pcmcia_power_off(void)
|
||||
{
|
||||
/* 0V */
|
||||
GPSR(81) = GPIO_bit(81);
|
||||
GPSR(82) = GPIO_bit(82);
|
||||
/* disable PCMCIA */
|
||||
GPSR(83) = GPIO_bit(83);
|
||||
}
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/arch/pxa-regs.h>
|
||||
|
||||
#define LTC1663_ADDR 0x20
|
||||
|
||||
#define LTC1663_SY 0x01 /* Sync ACK */
|
||||
#define LTC1663_SD 0x04 /* shutdown */
|
||||
#define LTC1663_BG 0x04 /* Internal Voltage Ref */
|
||||
|
||||
#define VOLT_1_55 18 /* DAC value for 1.55V */
|
||||
|
||||
.global initPXAvoltage
|
||||
|
||||
@ Set the voltage to 1.55V early in the boot process so we can run
|
||||
@ at a high clock speed and boot quickly. Note that this is necessary
|
||||
@ because the reset button does not reset the CPU voltage, so if the
|
||||
@ voltage was low (say 0.85V) then the CPU would crash without this
|
||||
@ routine
|
||||
|
||||
@ This routine clobbers r0-r4
|
||||
|
||||
initializei2c:
|
||||
|
||||
ldr r2, =CKEN
|
||||
ldr r3, [r2]
|
||||
orr r3, r3, #CKEN15_PWRI2C
|
||||
str r3, [r2]
|
||||
|
||||
ldr r2, =PCFR
|
||||
ldr r3, [r2]
|
||||
orr r3, r3, #PCFR_PI2C_EN
|
||||
str r3, [r2]
|
||||
|
||||
/* delay for about 250msec
|
||||
*/
|
||||
ldr r3, =OSCR
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r1, =0xC0000
|
||||
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r1, r2
|
||||
bgt 1b
|
||||
ldr r0, =PWRICR
|
||||
ldr r1, [r0]
|
||||
bic r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
|
||||
str r1, [r0]
|
||||
|
||||
orr r1, r1, #ICR_UR
|
||||
str r1, [r0]
|
||||
|
||||
ldr r2, =PWRISR
|
||||
ldr r3, =0x7ff
|
||||
str r3, [r2]
|
||||
|
||||
bic r1, r1, #ICR_UR
|
||||
str r1, [r0]
|
||||
|
||||
mov r1, #(ICR_GCD | ICR_SCLE)
|
||||
str r1, [r0]
|
||||
|
||||
orr r1, r1, #ICR_IUE
|
||||
str r1, [r0]
|
||||
|
||||
orr r1, r1, #ICR_FM
|
||||
str r1, [r0]
|
||||
|
||||
/* delay for about 1msec
|
||||
*/
|
||||
ldr r3, =OSCR
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r1, =0xC00
|
||||
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r1, r2
|
||||
bgt 1b
|
||||
mov pc, lr
|
||||
|
||||
sendbytei2c:
|
||||
ldr r3, =PWRIDBR
|
||||
str r0, [r3]
|
||||
ldr r3, =PWRICR
|
||||
ldr r0, [r3]
|
||||
orr r0, r0, r1
|
||||
bic r0, r0, r2
|
||||
str r0, [r3]
|
||||
orr r0, r0, #ICR_TB
|
||||
str r0, [r3]
|
||||
|
||||
mov r2, #0x100000
|
||||
|
||||
waitfortxemptyi2c:
|
||||
|
||||
ldr r0, =PWRISR
|
||||
ldr r1, [r0]
|
||||
|
||||
/* take it from the top if we don't get empty after a while */
|
||||
subs r2, r2, #1
|
||||
moveq lr, r4
|
||||
beq initPXAvoltage
|
||||
|
||||
tst r1, #ISR_ITE
|
||||
|
||||
beq waitfortxemptyi2c
|
||||
|
||||
orr r1, r1, #ISR_ITE
|
||||
str r1, [r0]
|
||||
|
||||
mov pc, lr
|
||||
|
||||
initPXAvoltage:
|
||||
|
||||
mov r4, lr
|
||||
|
||||
bl setleds
|
||||
|
||||
bl initializei2c
|
||||
|
||||
bl setleds
|
||||
|
||||
/* now send the real message to set the correct voltage */
|
||||
ldr r0, =LTC1663_ADDR
|
||||
mov r0, r0, LSL #1
|
||||
mov r1, #ICR_START
|
||||
ldr r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
|
||||
bl sendbytei2c
|
||||
|
||||
bl setleds
|
||||
|
||||
mov r0, #LTC1663_BG
|
||||
mov r1, #0
|
||||
mov r2, #(ICR_STOP | ICR_START)
|
||||
bl sendbytei2c
|
||||
|
||||
bl setleds
|
||||
|
||||
ldr r0, =VOLT_1_55
|
||||
and r0, r0, #0xff
|
||||
mov r1, #0
|
||||
mov r2, #(ICR_STOP | ICR_START)
|
||||
bl sendbytei2c
|
||||
|
||||
bl setleds
|
||||
|
||||
ldr r0, =VOLT_1_55
|
||||
mov r0, r0, ASR #8
|
||||
and r0, r0, #0xff
|
||||
mov r1, #ICR_STOP
|
||||
mov r2, #ICR_START
|
||||
bl sendbytei2c
|
||||
|
||||
bl setleds
|
||||
|
||||
@ delay a little for the volatage to stablize
|
||||
ldr r3, =OSCR
|
||||
mov r2, #0
|
||||
str r2, [r3]
|
||||
ldr r1, =0xC0
|
||||
|
||||
1:
|
||||
ldr r2, [r3]
|
||||
cmp r1, r2
|
||||
bgt 1b
|
||||
mov pc, r4
|
||||
|
||||
setleds:
|
||||
mov pc, lr
|
||||
|
||||
ldr r5, =0x40e00058
|
||||
ldr r3, [r5]
|
||||
bic r3, r3, #0x3
|
||||
str r3, [r5]
|
||||
ldr r5, =0x40e0000c
|
||||
ldr r3, [r5]
|
||||
orr r3, r3, #0x00010000
|
||||
str r3, [r5]
|
||||
|
||||
@ inner loop
|
||||
mov r0, #0x2
|
||||
1:
|
||||
|
||||
ldr r5, =0x40e00018
|
||||
mov r3, #0x00010000
|
||||
str r3, [r5]
|
||||
|
||||
@ outer loop
|
||||
mov r3, #0x00F00000
|
||||
2:
|
||||
subs r3, r3, #1
|
||||
bne 2b
|
||||
|
||||
ldr r5, =0x40e00024
|
||||
mov r3, #0x00010000
|
||||
str r3, [r5]
|
||||
|
||||
@ outer loop
|
||||
mov r3, #0x00F00000
|
||||
3:
|
||||
subs r3, r3, #1
|
||||
bne 3b
|
||||
|
||||
subs r0, r0, #1
|
||||
bne 1b
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/pxa/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
||||
|
|
@ -136,9 +136,9 @@ do_test (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
|
||||
if (adv == 2) {
|
||||
if (strcmp(ap[0], "-z") == 0)
|
||||
expr = strlen(ap[1]) == 0 ? 0 : 1;
|
||||
else if (strcmp(ap[0], "-n") == 0)
|
||||
expr = strlen(ap[1]) == 0 ? 1 : 0;
|
||||
else if (strcmp(ap[0], "-n") == 0)
|
||||
expr = strlen(ap[1]) == 0 ? 0 : 1;
|
||||
else {
|
||||
expr = 1;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1082,7 +1082,7 @@ void program_rtr (unsigned long* dimm_populated,
|
|||
case 0x00:
|
||||
refresh_rate = 15625;
|
||||
break;
|
||||
case 0x011:
|
||||
case 0x01:
|
||||
refresh_rate = 15625/4;
|
||||
break;
|
||||
case 0x02:
|
||||
|
|
|
|||
141
cpu/pxa/mmc.c
141
cpu/pxa/mmc.c
|
|
@ -72,13 +72,11 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
|
|||
|
||||
status = MMC_STAT;
|
||||
debug("MMC status %x\n", status);
|
||||
if (status & MMC_STAT_TIME_OUT_RESPONSE)
|
||||
{
|
||||
if (status & MMC_STAT_TIME_OUT_RESPONSE) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (cmdat & 0x3)
|
||||
{
|
||||
switch (cmdat & 0x3) {
|
||||
case MMC_CMDAT_R1:
|
||||
case MMC_CMDAT_R3:
|
||||
words = 3;
|
||||
|
|
@ -91,8 +89,7 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
|
|||
default:
|
||||
return 0;
|
||||
}
|
||||
for (i = words-1; i >= 0; i--)
|
||||
{
|
||||
for (i = words-1; i >= 0; i--) {
|
||||
ulong res_fifo = MMC_RES;
|
||||
int offset = i << 1;
|
||||
|
||||
|
|
@ -100,8 +97,7 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
|
|||
resp[offset+1] = ((uchar *)&res_fifo)[1];
|
||||
}
|
||||
#ifdef MMC_DEBUG
|
||||
for (i=0; i<words*2; i += 2)
|
||||
{
|
||||
for (i=0; i<words*2; i += 2) {
|
||||
printf("MMC resp[%d] = %02x\n", i, resp[i]);
|
||||
printf("MMC resp[%d] = %02x\n", i+1, resp[i+1]);
|
||||
}
|
||||
|
|
@ -118,8 +114,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
|
|||
ushort argh, argl;
|
||||
ulong status;
|
||||
|
||||
if (len == 0)
|
||||
{
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -143,16 +138,21 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
|
|||
|
||||
|
||||
MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
|
||||
while (len)
|
||||
{
|
||||
if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ)
|
||||
{
|
||||
while (len) {
|
||||
if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) {
|
||||
#ifdef CONFIG_PXA27X
|
||||
int i;
|
||||
for (i=min(len,32); i; i--) {
|
||||
*dst++ = * ((volatile uchar *) &MMC_RXFIFO);
|
||||
len--;
|
||||
}
|
||||
#else
|
||||
*dst++ = MMC_RXFIFO;
|
||||
len--;
|
||||
#endif
|
||||
}
|
||||
status = MMC_STAT;
|
||||
if (status & MMC_STAT_ERRORS)
|
||||
{
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -160,8 +160,7 @@ mmc_block_read(uchar *dst, ulong src, ulong len)
|
|||
MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE;
|
||||
while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE));
|
||||
status = MMC_STAT;
|
||||
if (status & MMC_STAT_ERRORS)
|
||||
{
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -177,8 +176,7 @@ mmc_block_write(ulong dst, uchar *src, int len)
|
|||
ushort argh, argl;
|
||||
ulong status;
|
||||
|
||||
if (len == 0)
|
||||
{
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -200,25 +198,20 @@ mmc_block_write(ulong dst, uchar *src, int len)
|
|||
MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
|
||||
|
||||
MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
|
||||
while (len)
|
||||
{
|
||||
if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ)
|
||||
{
|
||||
while (len) {
|
||||
if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) {
|
||||
int i, bytes = min(32,len);
|
||||
|
||||
for (i=0; i<bytes; i++)
|
||||
{
|
||||
for (i=0; i<bytes; i++) {
|
||||
MMC_TXFIFO = *src++;
|
||||
}
|
||||
if (bytes < 32)
|
||||
{
|
||||
if (bytes < 32) {
|
||||
MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL;
|
||||
}
|
||||
len -= bytes;
|
||||
}
|
||||
status = MMC_STAT;
|
||||
if (status & MMC_STAT_ERRORS)
|
||||
{
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -228,8 +221,7 @@ mmc_block_write(ulong dst, uchar *src, int len)
|
|||
MMC_I_MASK = ~MMC_I_MASK_PRG_DONE;
|
||||
while (!(MMC_I_REG & MMC_I_REG_PRG_DONE));
|
||||
status = MMC_STAT;
|
||||
if (status & MMC_STAT_ERRORS)
|
||||
{
|
||||
if (status & MMC_STAT_ERRORS) {
|
||||
printf("MMC_STAT error %lx\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -245,13 +237,11 @@ mmc_read(ulong src, uchar *dst, int size)
|
|||
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
|
||||
ulong mmc_block_size, mmc_block_address;
|
||||
|
||||
if (size == 0)
|
||||
{
|
||||
if (size == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!mmc_ready)
|
||||
{
|
||||
if (!mmc_ready) {
|
||||
printf("Please initial the MMC first\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -269,13 +259,11 @@ mmc_read(ulong src, uchar *dst, int size)
|
|||
/* all block aligned accesses */
|
||||
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if (part_start)
|
||||
{
|
||||
if (part_start) {
|
||||
part_len = mmc_block_size - part_start;
|
||||
debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
memcpy(dst, mmc_buf+part_start, part_len);
|
||||
|
|
@ -284,23 +272,19 @@ mmc_read(ulong src, uchar *dst, int size)
|
|||
}
|
||||
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size)
|
||||
{
|
||||
for (; src < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
|
||||
debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_read((uchar *)(dst), src, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if (part_end && src < end)
|
||||
{
|
||||
if (part_end && src < end) {
|
||||
debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
memcpy(dst, mmc_buf, part_end);
|
||||
|
|
@ -316,13 +300,11 @@ mmc_write(uchar *src, ulong dst, int size)
|
|||
ulong end, part_start, part_end, part_len, aligned_start, aligned_end;
|
||||
ulong mmc_block_size, mmc_block_address;
|
||||
|
||||
if (size == 0)
|
||||
{
|
||||
if (size == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!mmc_ready)
|
||||
{
|
||||
if (!mmc_ready) {
|
||||
printf("Please initial the MMC first\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -340,18 +322,15 @@ mmc_write(uchar *src, ulong dst, int size)
|
|||
/* all block aligned accesses */
|
||||
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if (part_start)
|
||||
{
|
||||
if (part_start) {
|
||||
part_len = mmc_block_size - part_start;
|
||||
debug("ps src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
(ulong)src, dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_read(mmc_buf, aligned_start, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
memcpy(mmc_buf+part_start, src, part_len);
|
||||
if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_write(aligned_start, mmc_buf, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
dst += part_len;
|
||||
|
|
@ -359,28 +338,23 @@ mmc_write(uchar *src, ulong dst, int size)
|
|||
}
|
||||
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size)
|
||||
{
|
||||
for (; dst < aligned_end; src += mmc_block_size, dst += mmc_block_size) {
|
||||
debug("al src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_write(dst, (uchar *)src, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
debug("src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if (part_end && dst < end)
|
||||
{
|
||||
if (part_end && dst < end) {
|
||||
debug("pe src %lx dst %lx end %lx pstart %lx pend %lx astart %lx aend %lx\n",
|
||||
src, (ulong)dst, end, part_start, part_end, aligned_start, aligned_end);
|
||||
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_read(mmc_buf, aligned_end, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
memcpy(mmc_buf, src, part_end);
|
||||
if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0)
|
||||
{
|
||||
if ((mmc_block_write(aligned_end, mmc_buf, mmc_block_size)) < 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
|
@ -412,6 +386,11 @@ mmc_init(int verbose)
|
|||
set_GPIO_mode( GPIO8_MMCCS0_MD );
|
||||
#endif
|
||||
CKEN |= CKEN12_MMC; /* enable MMC unit clock */
|
||||
#if defined(CONFIG_ADSVIX)
|
||||
/* turn on the power */
|
||||
GPCR(114) = GPIO_bit(114);
|
||||
udelay(1000);
|
||||
#endif
|
||||
|
||||
mmc_csd.c_size = 0;
|
||||
|
||||
|
|
@ -423,21 +402,22 @@ mmc_init(int verbose)
|
|||
retries = 10;
|
||||
resp = mmc_cmd(0, 0, 0, 0);
|
||||
resp = mmc_cmd(1, 0x00ff, 0xc000, MMC_CMDAT_INIT|MMC_CMDAT_BUSY|MMC_CMDAT_R3);
|
||||
while (retries-- && resp && !(resp[4] & 0x80))
|
||||
{
|
||||
while (retries-- && resp && !(resp[4] & 0x80)) {
|
||||
debug("resp %x %x\n", resp[0], resp[1]);
|
||||
#ifdef CONFIG_PXA27X
|
||||
udelay(10000);
|
||||
#else
|
||||
udelay(50);
|
||||
#endif
|
||||
resp = mmc_cmd(1, 0x00ff, 0xff00, MMC_CMDAT_BUSY|MMC_CMDAT_R3);
|
||||
}
|
||||
|
||||
/* try to get card id */
|
||||
resp = mmc_cmd(2, 0, 0, MMC_CMDAT_R2);
|
||||
if (resp)
|
||||
{
|
||||
if (resp) {
|
||||
/* TODO configure mmc driver depending on card attributes */
|
||||
mmc_cid_t *cid = (mmc_cid_t *)resp;
|
||||
if (verbose)
|
||||
{
|
||||
if (verbose) {
|
||||
printf("MMC found. Card desciption is:\n");
|
||||
printf("Manufacturer ID = %02x%02x%02x\n",
|
||||
cid->id[0], cid->id[1], cid->id[2]);
|
||||
|
|
@ -451,6 +431,7 @@ mmc_init(int verbose)
|
|||
}
|
||||
/* fill in device description */
|
||||
mmc_dev.if_type = IF_TYPE_MMC;
|
||||
mmc_dev.part_type = PART_TYPE_DOS;
|
||||
mmc_dev.dev = 0;
|
||||
mmc_dev.lun = 0;
|
||||
mmc_dev.type = 0;
|
||||
|
|
@ -468,8 +449,7 @@ mmc_init(int verbose)
|
|||
/* MMC exists, get CSD too */
|
||||
resp = mmc_cmd(MMC_CMD_SET_RCA, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
|
||||
resp = mmc_cmd(MMC_CMD_SEND_CSD, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R2);
|
||||
if (resp)
|
||||
{
|
||||
if (resp) {
|
||||
mmc_csd_t *csd = (mmc_csd_t *)resp;
|
||||
memcpy(&mmc_csd, csd, sizeof(csd));
|
||||
rc = 0;
|
||||
|
|
@ -478,7 +458,11 @@ mmc_init(int verbose)
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PXA27X
|
||||
MMC_CLKRT = 1; /* 10 MHz - see Intel errata */
|
||||
#else
|
||||
MMC_CLKRT = 0; /* 20 MHz */
|
||||
#endif
|
||||
resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
|
||||
|
||||
fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
|
||||
|
|
@ -496,11 +480,10 @@ int
|
|||
mmc2info(ulong addr)
|
||||
{
|
||||
/* FIXME hard codes to 32 MB device */
|
||||
if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000)
|
||||
{
|
||||
if (addr >= CFG_MMC_BASE && addr < CFG_MMC_BASE + 0x02000000) {
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* CONFIG_MMC */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,352 @@
|
|||
/*
|
||||
* (C) Copyright 2004
|
||||
* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* Configuation settings for the LUBBOCK board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
#define RTC
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
|
||||
#define CONFIG_ADSVIX 1 /* on a Adsvix Board */
|
||||
#define CONFIG_MMC 1
|
||||
#define BOARD_LATE_INIT 1
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_FFUART 1 /* we use FFUART on ADSVIX */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_SERVERIP 192.168.1.99
|
||||
#define CONFIG_BOOTCOMMAND "run boot_flash"
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
|
||||
" rw root=/dev/ram initrd=0xa0800000,5m"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"program_boot_cf=" \
|
||||
"mw.b 0xa0010000 0xff 0x20000; " \
|
||||
"if pinit on && " \
|
||||
"ide reset && " \
|
||||
"fatload ide 0 0xa0010000 u-boot.bin; " \
|
||||
"then " \
|
||||
"protect off 0x0 0x1ffff; " \
|
||||
"erase 0x0 0x1ffff; " \
|
||||
"cp.b 0xa0010000 0x0 0x20000; " \
|
||||
"fi\0" \
|
||||
"program_uzImage_cf=" \
|
||||
"mw.b 0xa0010000 0xff 0x180000; " \
|
||||
"if pinit on && " \
|
||||
"ide reset && " \
|
||||
"fatload ide 0 0xa0010000 uzImage; " \
|
||||
"then " \
|
||||
"protect off 0x40000 0x1bffff; " \
|
||||
"erase 0x40000 0x1bffff; " \
|
||||
"cp.b 0xa0010000 0x40000 0x180000; " \
|
||||
"fi\0" \
|
||||
"program_ramdisk_cf=" \
|
||||
"mw.b 0xa0010000 0xff 0x500000; " \
|
||||
"if pinit on && " \
|
||||
"ide reset && " \
|
||||
"fatload ide 0 0xa0010000 ramdisk.gz; " \
|
||||
"then " \
|
||||
"protect off 0x1c0000 0x6bffff; " \
|
||||
"erase 0x1c0000 0x6bffff; " \
|
||||
"cp.b 0xa0010000 0x1c0000 0x500000; " \
|
||||
"fi\0" \
|
||||
"boot_cf=" \
|
||||
"if pinit on && " \
|
||||
"ide reset && " \
|
||||
"fatload ide 0 0xa0030000 uzImage && " \
|
||||
"fatload ide 0 0xa0800000 ramdisk.gz; " \
|
||||
"then " \
|
||||
"bootm 0xa0030000; " \
|
||||
"fi\0" \
|
||||
"program_boot_mmc=" \
|
||||
"mw.b 0xa0010000 0xff 0x20000; " \
|
||||
"if mmcinit && " \
|
||||
"fatload mmc 0 0xa0010000 u-boot.bin; " \
|
||||
"then " \
|
||||
"protect off 0x0 0x1ffff; " \
|
||||
"erase 0x0 0x1ffff; " \
|
||||
"cp.b 0xa0010000 0x0 0x20000; " \
|
||||
"fi\0" \
|
||||
"program_uzImage_mmc=" \
|
||||
"mw.b 0xa0010000 0xff 0x180000; " \
|
||||
"if mmcinit && " \
|
||||
"fatload mmc 0 0xa0010000 uzImage; " \
|
||||
"then " \
|
||||
"protect off 0x40000 0x1bffff; " \
|
||||
"erase 0x40000 0x1bffff; " \
|
||||
"cp.b 0xa0010000 0x40000 0x180000; " \
|
||||
"fi\0" \
|
||||
"program_ramdisk_mmc=" \
|
||||
"mw.b 0xa0010000 0xff 0x500000; " \
|
||||
"if mmcinit && " \
|
||||
"fatload mmc 0 0xa0010000 ramdisk.gz; " \
|
||||
"then " \
|
||||
"protect off 0x1c0000 0x6bffff; " \
|
||||
"erase 0x1c0000 0x6bffff; " \
|
||||
"cp.b 0xa0010000 0x1c0000 0x500000; " \
|
||||
"fi\0" \
|
||||
"boot_mmc=" \
|
||||
"if mmcinit && " \
|
||||
"fatload mmc 0 0xa0030000 uzImage && " \
|
||||
"fatload mmc 0 0xa0800000 ramdisk.gz; " \
|
||||
"then " \
|
||||
"bootm 0xa0030000; " \
|
||||
"fi\0" \
|
||||
"boot_flash=" \
|
||||
"cp.b 0x1c0000 0xa0800000 0x500000; " \
|
||||
"bootm 0x40000\0" \
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
/* #define CONFIG_INITRD_TAG 1 */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_HUSH_PARSER 1
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT "$ " /* Monitor Command Prompt */
|
||||
#else
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#endif
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_DEVICE_NULLDEV 1
|
||||
|
||||
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0xa1000000 /* default load address */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
#define CFG_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CFG_MMC_BASE 0xF0000000
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
|
||||
#define CFG_DRAM_BASE 0xa0000000
|
||||
#define CFG_DRAM_SIZE 0x04000000
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*
|
||||
* GPIO settings
|
||||
*/
|
||||
|
||||
#define CFG_GPSR0_VAL 0x00018004
|
||||
#define CFG_GPSR1_VAL 0x004F0080
|
||||
#define CFG_GPSR2_VAL 0x13EFC000
|
||||
#define CFG_GPSR3_VAL 0x0006E032
|
||||
#define CFG_GPCR0_VAL 0x084AFE1A
|
||||
#define CFG_GPCR1_VAL 0x003003F2
|
||||
#define CFG_GPCR2_VAL 0x0C014000
|
||||
#define CFG_GPCR3_VAL 0x00000C00
|
||||
#define CFG_GPDR0_VAL 0xCBC3BFFC
|
||||
#define CFG_GPDR1_VAL 0x00FFABF3
|
||||
#define CFG_GPDR2_VAL 0x1EEFFC00
|
||||
#define CFG_GPDR3_VAL 0x0187EC32
|
||||
#define CFG_GAFR0_L_VAL 0x84400000
|
||||
#define CFG_GAFR0_U_VAL 0xA51A8010
|
||||
#define CFG_GAFR1_L_VAL 0x699A955A
|
||||
#define CFG_GAFR1_U_VAL 0x0005A0AA
|
||||
#define CFG_GAFR2_L_VAL 0x40000000
|
||||
#define CFG_GAFR2_U_VAL 0x0109A400
|
||||
#define CFG_GAFR3_L_VAL 0x54000000
|
||||
#define CFG_GAFR3_U_VAL 0x00001409
|
||||
|
||||
#define CFG_PSSR_VAL 0x20
|
||||
|
||||
/*
|
||||
* Clock settings
|
||||
*/
|
||||
#define CFG_CKEN 0x00400200
|
||||
#define CFG_CCCR 0x02000290 /* 520Mhz */
|
||||
/* #define CFG_CCCR 0x02000210 416 Mhz */
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
|
||||
#define CFG_MSC0_VAL 0x23F2B3DB
|
||||
#define CFG_MSC1_VAL 0x0000CCD1
|
||||
#define CFG_MSC2_VAL 0x0000B884
|
||||
#define CFG_MDCNFG_VAL 0x08000AC8
|
||||
#define CFG_MDREFR_VAL 0x0000001E
|
||||
#define CFG_MDMRS_VAL 0x00000000
|
||||
|
||||
#define CFG_FLYCNFG_VAL 0x00010001
|
||||
#define CFG_SXCNFG_VAL 0x40044004
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
#define CFG_MECR_VAL 0x00000002
|
||||
#define CFG_MCMEM0_VAL 0x00004204
|
||||
#define CFG_MCMEM1_VAL 0x00000000
|
||||
#define CFG_MCATT0_VAL 0x00010504
|
||||
#define CFG_MCATT1_VAL 0x00000000
|
||||
#define CFG_MCIO0_VAL 0x00008407
|
||||
#define CFG_MCIO1_VAL 0x00000000
|
||||
|
||||
#define CONFIG_PXA_PCMCIA 1
|
||||
#define CONFIG_PXA_IDE 1
|
||||
|
||||
#define CONFIG_PCMCIA_SLOT_A 1
|
||||
/* just to keep build system happy */
|
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR 0x28000000
|
||||
#define CFG_PCMCIA_MEM_SIZE 0x04000000
|
||||
|
||||
|
||||
#define CFG_IDE_MAXBUS 1
|
||||
/* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1
|
||||
/* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR 0x20000000
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET 0x1f0
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET 0x1f0
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x3f0
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
|
||||
#define CFG_MONITOR_BASE 0
|
||||
#define CFG_MONITOR_LEN 0x20000
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
/* write flash less slowly */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1
|
||||
|
||||
/* Flash environment locations */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN) /* Addr of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue