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tegra: setup L2 cache on Tegra124 

Set SRAM latency to 3 clock cycles.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach 2014-06-03 22:35:05 +02:00 committed by Sascha Hauer
parent 08f5fcbad6
commit 22920598a5
1 changed files with 12 additions and 1 deletions
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13
arch/arm/mach-tegra/tegra_maincomplex_init.c
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@ -25,6 +25,8 @@
void tegra_maincomplex_entry(void)
{
uint32_t rambase, ramsize;
enum tegra_chiptype chiptype;
u32 reg = 0;
arm_cpu_lowlevel_init();
@ -36,7 +38,16 @@ void tegra_maincomplex_entry(void)
TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
switch (tegra_get_chiptype()) {
chiptype = tegra_get_chiptype();
if (chiptype >= TEGRA114) {
asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
reg &= ~7;
reg |= 2;
asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
}
switch (chiptype) {
case TEGRA20:
rambase = 0x0;
ramsize = tegra20_get_ramsize();