tegra: setup L2 cache on Tegra124
Set SRAM latency to 3 clock cycles. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -25,6 +25,8 @@
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void tegra_maincomplex_entry(void)
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void tegra_maincomplex_entry(void)
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{
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{
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uint32_t rambase, ramsize;
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uint32_t rambase, ramsize;
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enum tegra_chiptype chiptype;
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u32 reg = 0;
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arm_cpu_lowlevel_init();
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arm_cpu_lowlevel_init();
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@ -36,7 +38,16 @@ void tegra_maincomplex_entry(void)
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TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
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TEGRA_CLK_RESET_BASE + CRC_CCLK_BURST_POLICY);
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writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
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writel(CRC_SUPER_CDIV_ENB, TEGRA_CLK_RESET_BASE + CRC_SUPER_CCLK_DIV);
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switch (tegra_get_chiptype()) {
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chiptype = tegra_get_chiptype();
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if (chiptype >= TEGRA114) {
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asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
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reg &= ~7;
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reg |= 2;
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asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
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}
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switch (chiptype) {
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case TEGRA20:
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case TEGRA20:
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rambase = 0x0;
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rambase = 0x0;
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ramsize = tegra20_get_ramsize();
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ramsize = tegra20_get_ramsize();
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