dts: update to v4.9-rc2
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -0,0 +1,23 @@
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* Aspeed BT (Block Transfer) IPMI interface
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The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
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(BaseBoard Management Controllers) and the BT interface can be used to
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perform in-band IPMI communication with their host.
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Required properties:
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- compatible : should be "aspeed,ast2400-bt-bmc"
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- reg: physical address and size of the registers
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Optional properties:
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- interrupts: interrupt generated by the BT interface. without an
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interrupt, the driver will operate in poll mode.
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Example:
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ibt@1e789140 {
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compatible = "aspeed,ast2400-bt-bmc";
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reg = <0x1e789140 0x18>;
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interrupts = <8>;
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};
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@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
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GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
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GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
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I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
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I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
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RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
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RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
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TIMER7 TIMER8 VGABIOSROM
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Examples:
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Examples:
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@ -0,0 +1,24 @@
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J-Core Programmable Interval Timer and Clocksource
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Required properties:
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- compatible: Must be "jcore,pit".
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- reg: Memory region(s) for timer/clocksource registers. For SMP,
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there should be one region per cpu, indexed by the sequential,
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zero-based hardware cpu number.
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- interrupts: An interrupt to assign for the timer. The actual pit
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core is integrated with the aic and allows the timer interrupt
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assignment to be programmed by software, but this property is
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required in order to reserve an interrupt number that doesn't
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conflict with other devices.
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Example:
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timer@200 {
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compatible = "jcore,pit";
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reg = < 0x200 0x30 0x500 0x30 >;
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interrupts = < 0x48 >;
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};
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