dts: update to v3.15-rc5

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

dts/Bindings/net/arc_emac.txt

@@ -4,11 +4,15 @@ Required properties:
 - compatible: Should be "snps,arc-emac"
 - reg: Address and length of the register set for the device
 - interrupts: Should contain the EMAC interrupts
-- clock-frequency: CPU frequency. It is needed to calculate and set polling
-period of EMAC.
 - max-speed: see ethernet.txt file in the same directory.
 - phy: see ethernet.txt file in the same directory.
 
+Clock handling:
+The clock frequency is needed to calculate and set polling period of EMAC.
+It must be provided by one of:
+- clock-frequency: CPU frequency.
+- clocks: reference to the clock supplying the EMAC.
+
 Child nodes of the driver are the individual PHY devices connected to the
 MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
 
@@ -19,7 +23,11 @@ Examples:
 		reg = <0xc0fc2000 0x3c>;
 		interrupts = <6>;
 		mac-address = [ 00 11 22 33 44 55 ];
+
 		clock-frequency = <80000000>;
+		/* or */
+		clocks = <&emac_clock>;
+
 		max-speed = <100>;
 		phy = <&phy0>;
 

dts/src/xtensa/kc705.dts

@@ -0,0 +1,11 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-128m.dtsi"
+
+/ {
+	compatible = "cdns,xtensa-kc705";
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x08000000>;
+	};
+};

dts/src/xtensa/xtfpga-flash-128m.dtsi

@@ -0,0 +1,28 @@
+/ {
+	soc {
+		flash: flash@00000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "cfi-flash";
+			reg = <0x00000000 0x08000000>;
+			bank-width = <2>;
+			device-width = <2>;
+			partition@0x0 {
+				label = "data";
+				reg = <0x00000000 0x06000000>;
+			};
+			partition@0x6000000 {
+				label = "boot loader area";
+				reg = <0x06000000 0x00800000>;
+			};
+			partition@0x6800000 {
+				label = "kernel image";
+				reg = <0x06800000 0x017e0000>;
+			};
+			partition@0x7fe0000 {
+				label = "boot environment";
+				reg = <0x07fe0000 0x00020000>;
+			};
+		};
+        };
+};

dts/src/xtensa/xtfpga-flash-16m.dtsi

@@ -1,26 +1,28 @@
 / {
-	flash: flash@f8000000 {
+	soc {
-		#address-cells = <1>;
+		flash: flash@08000000 {
-		#size-cells = <1>;
+			#address-cells = <1>;
-		compatible = "cfi-flash";
+			#size-cells = <1>;
-		reg = <0xf8000000 0x01000000>;
+			compatible = "cfi-flash";
-		bank-width = <2>;
+			reg = <0x08000000 0x01000000>;
-		device-width = <2>;
+			bank-width = <2>;
-		partition@0x0 {
+			device-width = <2>;
-			label = "boot loader area";
+			partition@0x0 {
-			reg = <0x00000000 0x00400000>;
+				label = "boot loader area";
+				reg = <0x00000000 0x00400000>;
+			};
+			partition@0x400000 {
+				label = "kernel image";
+				reg = <0x00400000 0x00600000>;
+			};
+			partition@0xa00000 {
+				label = "data";
+				reg = <0x00a00000 0x005e0000>;
+			};
+			partition@0xfe0000 {
+				label = "boot environment";
+				reg = <0x00fe0000 0x00020000>;
+			};
 		};
-		partition@0x400000 {
+	};
-			label = "kernel image";
-			reg = <0x00400000 0x00600000>;
-		};
-		partition@0xa00000 {
-			label = "data";
-			reg = <0x00a00000 0x005e0000>;
-		};
-		partition@0xfe0000 {
-			label = "boot environment";
-			reg = <0x00fe0000 0x00020000>;
-		};
-        };
 };

dts/src/xtensa/xtfpga-flash-4m.dtsi

@@ -1,18 +1,20 @@
 / {
-	flash: flash@f8000000 {
+	soc {
-		#address-cells = <1>;
+		flash: flash@08000000 {
-		#size-cells = <1>;
+			#address-cells = <1>;
-		compatible = "cfi-flash";
+			#size-cells = <1>;
-		reg = <0xf8000000 0x00400000>;
+			compatible = "cfi-flash";
-		bank-width = <2>;
+			reg = <0x08000000 0x00400000>;
-		device-width = <2>;
+			bank-width = <2>;
-		partition@0x0 {
+			device-width = <2>;
-			label = "boot loader area";
+			partition@0x0 {
-			reg = <0x00000000 0x003f0000>;
+				label = "boot loader area";
+				reg = <0x00000000 0x003f0000>;
+			};
+			partition@0x3f0000 {
+				label = "boot environment";
+				reg = <0x003f0000 0x00010000>;
+			};
 		};
-		partition@0x3f0000 {
+	};
-			label = "boot environment";
-			reg = <0x003f0000 0x00010000>;
-		};
-        };
 };

dts/src/xtensa/xtfpga.dtsi

@@ -42,21 +42,28 @@
 		};
 	};
 
-	serial0: serial@fd050020 {
+	soc {
-		device_type = "serial";
+		#address-cells = <1>;
-		compatible = "ns16550a";
+		#size-cells = <1>;
-		no-loopback-test;
+		compatible = "simple-bus";
-		reg = <0xfd050020 0x20>;
+		ranges = <0x00000000 0xf0000000 0x10000000>;
-		reg-shift = <2>;
-		interrupts = <0 1>; /* external irq 0 */
-		clocks = <&osc>;
-	};
 
-	enet0: ethoc@fd030000 {
+		serial0: serial@0d050020 {
-		compatible = "opencores,ethoc";
+			device_type = "serial";
-		reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
+			compatible = "ns16550a";
-		interrupts = <1 1>; /* external irq 1 */
+			no-loopback-test;
-		local-mac-address = [00 50 c2 13 6f 00];
+			reg = <0x0d050020 0x20>;
-		clocks = <&osc>;
+			reg-shift = <2>;
+			interrupts = <0 1>; /* external irq 0 */
+			clocks = <&osc>;
+		};
+
+		enet0: ethoc@0d030000 {
+			compatible = "opencores,ethoc";
+			reg = <0x0d030000 0x4000 0x0d800000 0x4000>;
+			interrupts = <1 1>; /* external irq 1 */
+			local-mac-address = [00 50 c2 13 6f 00];
+			clocks = <&osc>;
+		};
 	};
 };