dma: add mxs-apbh-dma driver
Based on the U-Boot version. Changed to kernel style register layout, added MX23 support, made MMU aware and adapted to barebox. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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4a39f83320
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@ -0,0 +1,145 @@
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/*
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* Freescale i.MX28 APBH DMA
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __DMA_H__
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#define __DMA_H__
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#include <linux/list.h>
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#ifndef CONFIG_ARCH_DMA_PIO_WORDS
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#define DMA_PIO_WORDS 15
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#else
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#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
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#endif
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#define MXS_DMA_ALIGNMENT 32
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/*
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* MXS DMA channels
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*/
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
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MXS_DMA_CHANNEL_AHB_APBH_SSP1,
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MXS_DMA_CHANNEL_AHB_APBH_SSP2,
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MXS_DMA_CHANNEL_AHB_APBH_SSP3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
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MXS_DMA_CHANNEL_AHB_APBH_SSP,
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MXS_MAX_DMA_CHANNELS,
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};
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/*
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* MXS DMA hardware command.
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*
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* This structure describes the in-memory layout of an entire DMA command,
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* including space for the maximum number of PIO accesses. See the appropriate
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* reference manual for a detailed description of what these fields mean to the
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* DMA hardware.
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*/
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#define MXS_DMA_DESC_COMMAND_MASK 0x3
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#define MXS_DMA_DESC_COMMAND_OFFSET 0
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#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
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#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
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#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
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#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
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#define MXS_DMA_DESC_CHAIN (1 << 2)
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#define MXS_DMA_DESC_IRQ (1 << 3)
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#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
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#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
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#define MXS_DMA_DESC_DEC_SEM (1 << 6)
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#define MXS_DMA_DESC_WAIT4END (1 << 7)
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#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
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#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
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#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
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#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
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#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
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#define MXS_DMA_DESC_BYTES_OFFSET 16
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struct mxs_dma_cmd {
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unsigned long next;
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unsigned long data;
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union {
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dma_addr_t address;
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unsigned long alternate;
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};
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unsigned long pio_words[DMA_PIO_WORDS];
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};
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/*
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* MXS DMA command descriptor.
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*
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* This structure incorporates an MXS DMA hardware command structure, along
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* with metadata.
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*/
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#define MXS_DMA_DESC_FIRST (1 << 0)
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#define MXS_DMA_DESC_LAST (1 << 1)
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#define MXS_DMA_DESC_READY (1 << 31)
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struct mxs_dma_desc {
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struct mxs_dma_cmd cmd;
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unsigned int flags;
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dma_addr_t address;
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void *buffer;
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struct list_head node;
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};
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/**
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* MXS DMA channel
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*
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* This structure represents a single DMA channel. The MXS platform code
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* maintains an array of these structures to represent every DMA channel in the
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* system (see mxs_dma_channels).
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*/
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#define MXS_DMA_FLAGS_IDLE 0
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#define MXS_DMA_FLAGS_BUSY (1 << 0)
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#define MXS_DMA_FLAGS_FREE 0
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#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
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#define MXS_DMA_FLAGS_VALID (1 << 31)
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struct mxs_dma_chan {
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const char *name;
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unsigned long dev;
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struct mxs_dma_device *dma;
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unsigned int flags;
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unsigned int active_num;
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unsigned int pending_num;
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struct list_head active;
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struct list_head done;
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};
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struct mxs_dma_desc *mxs_dma_desc_alloc(void);
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void mxs_dma_desc_free(struct mxs_dma_desc *);
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int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
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int mxs_dma_go(int chan);
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int mxs_dma_init(void);
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#endif /* __DMA_H__ */
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@ -17,5 +17,6 @@ source "drivers/eeprom/Kconfig"
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source "drivers/input/Kconfig"
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source "drivers/input/Kconfig"
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source "drivers/pwm/Kconfig"
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source "drivers/pwm/Kconfig"
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source "drivers/dma/Kconfig"
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endmenu
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endmenu
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@ -15,3 +15,4 @@ obj-$(CONFIG_LED) += led/
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obj-y += eeprom/
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obj-y += eeprom/
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obj-$(CONFIG_PWM) += pwm/
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obj-$(CONFIG_PWM) += pwm/
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obj-y += input/
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obj-y += input/
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obj-y += dma/
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@ -0,0 +1,8 @@
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menu "DMA support"
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config MXS_APBH_DMA
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tristate "MXS APBH DMA ENGINE"
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depends on ARCH_IMX23 || ARCH_IMX28
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help
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Experimental!
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endmenu
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@ -0,0 +1 @@
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obj-$(CONFIG_MXS_APBH_DMA) += apbh_dma.o
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@ -0,0 +1,598 @@
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/*
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* Freescale i.MX28 APBH DMA driver
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*
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* Copyright (C) 2011 Wolfram Sang <w.sang@pengutronix.de>
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <asm/mmu.h>
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#include <asm/io.h>
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#include <mach/clock.h>
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#include <mach/imx-regs.h>
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#include <mach/dma.h>
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#include <mach/mxs.h>
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#define HW_APBHX_CTRL0 0x000
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
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#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
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#define BP_APBH_CTRL0_RESET_CHANNEL 16
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#define HW_APBHX_CTRL1 0x010
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#define BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN 16
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#define HW_APBHX_CTRL2 0x020
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#define HW_APBHX_CHANNEL_CTRL 0x030
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#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
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#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
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#define HW_APBX_VERSION 0x800
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#define BP_APBHX_VERSION_MAJOR 24
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#define HW_APBHX_CHn_NXTCMDAR(n) \
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((apbh_is_old ? 0x050 : 0x110) + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA(n) \
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((apbh_is_old ? 0x080 : 0x140) + (n) * 0x70)
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#define BM_APBHX_CHn_SEMA_PHORE (0xff << 16)
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#define BP_APBHX_CHn_SEMA_PHORE 16
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static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
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static bool apbh_is_old;
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/*
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* Test is the DMA channel is valid channel
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*/
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int mxs_dma_validate_chan(int channel)
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{
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struct mxs_dma_chan *pchan;
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if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
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return -EINVAL;
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pchan = mxs_dma_channels + channel;
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if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
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return -EINVAL;
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return 0;
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}
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/*
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* Return the address of the command within a descriptor.
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*/
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static unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
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{
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return desc->address + offsetof(struct mxs_dma_desc, cmd);
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}
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/*
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* Read a DMA channel's hardware semaphore.
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*
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* As used by the MXS platform's DMA software, the DMA channel's hardware
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* semaphore reflects the number of DMA commands the hardware will process, but
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* has not yet finished. This is a volatile value read directly from hardware,
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* so it must be be viewed as immediately stale.
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*
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* If the channel is not marked busy, or has finished processing all its
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* commands, this value should be zero.
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*
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* See mxs_dma_append() for details on how DMA command blocks must be configured
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* to maintain the expected behavior of the semaphore's value.
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*/
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static int mxs_dma_read_semaphore(int channel)
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{
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void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
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uint32_t tmp;
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int ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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tmp = readl(apbh_regs + HW_APBHX_CHn_SEMA(channel));
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tmp &= BM_APBHX_CHn_SEMA_PHORE;
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tmp >>= BP_APBHX_CHn_SEMA_PHORE;
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return tmp;
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}
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/*
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* Enable a DMA channel.
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*
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* If the given channel has any DMA descriptors on its active list, this
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* function causes the DMA hardware to begin processing them.
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*
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* This function marks the DMA channel as "busy," whether or not there are any
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* descriptors to process.
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*/
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static int mxs_dma_enable(int channel)
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{
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void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
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unsigned int sem;
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struct mxs_dma_chan *pchan;
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struct mxs_dma_desc *pdesc;
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int channel_bit, ret;
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ret = mxs_dma_validate_chan(channel);
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if (ret)
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return ret;
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pchan = mxs_dma_channels + channel;
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if (pchan->pending_num == 0) {
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
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if (pdesc == NULL)
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return -EFAULT;
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if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
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if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
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return 0;
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sem = mxs_dma_read_semaphore(channel);
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if (sem == 0)
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return 0;
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if (sem == 1) {
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pdesc = list_entry(pdesc->node.next,
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struct mxs_dma_desc, node);
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writel(mxs_dma_cmd_address(pdesc),
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apbh_regs + HW_APBHX_CHn_NXTCMDAR(channel));
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}
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writel(pchan->pending_num,
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apbh_regs + HW_APBHX_CHn_SEMA(channel));
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pchan->active_num += pchan->pending_num;
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pchan->pending_num = 0;
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} else {
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pchan->active_num += pchan->pending_num;
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pchan->pending_num = 0;
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writel(mxs_dma_cmd_address(pdesc),
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apbh_regs + HW_APBHX_CHn_NXTCMDAR(channel));
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writel(pchan->active_num,
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apbh_regs + HW_APBHX_CHn_SEMA(channel));
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channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
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writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_CLR);
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}
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pchan->flags |= MXS_DMA_FLAGS_BUSY;
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return 0;
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}
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/*
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* Disable a DMA channel.
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*
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* This function shuts down a DMA channel and marks it as "not busy." Any
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* descriptors on the active list are immediately moved to the head of the
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* "done" list, whether or not they have actually been processed by the
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* hardware. The "ready" flags of these descriptors are NOT cleared, so they
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* still appear to be active.
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*
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* This function immediately shuts down a DMA channel's hardware, aborting any
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* I/O that may be in progress, potentially leaving I/O hardware in an undefined
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* state. It is unwise to call this function if there is ANY chance the hardware
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* is still processing a command.
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*/
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static int mxs_dma_disable(int channel)
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{
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struct mxs_dma_chan *pchan;
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||||||
|
void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
|
||||||
|
int channel_bit, ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
pchan = mxs_dma_channels + channel;
|
||||||
|
|
||||||
|
if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
channel_bit = channel + (apbh_is_old ? BP_APBH_CTRL0_CLKGATE_CHANNEL : 0);
|
||||||
|
writel(1 << channel_bit, apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
|
||||||
|
|
||||||
|
pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
|
||||||
|
pchan->active_num = 0;
|
||||||
|
pchan->pending_num = 0;
|
||||||
|
list_splice_init(&pchan->active, &pchan->done);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Resets the DMA channel hardware.
|
||||||
|
*/
|
||||||
|
static int mxs_dma_reset(int channel)
|
||||||
|
{
|
||||||
|
void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (apbh_is_old)
|
||||||
|
writel(1 << (channel + BP_APBH_CTRL0_RESET_CHANNEL),
|
||||||
|
apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
|
||||||
|
else
|
||||||
|
writel(1 << (channel + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
|
||||||
|
apbh_regs + HW_APBHX_CHANNEL_CTRL + BIT_SET);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable or disable DMA interrupt.
|
||||||
|
*
|
||||||
|
* This function enables the given DMA channel to interrupt the CPU.
|
||||||
|
*/
|
||||||
|
static int mxs_dma_enable_irq(int channel, int enable)
|
||||||
|
{
|
||||||
|
void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (enable)
|
||||||
|
writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
|
||||||
|
apbh_regs + HW_APBHX_CTRL1 + BIT_SET);
|
||||||
|
else
|
||||||
|
writel(1 << (channel + BP_APBHX_CTRL1_CH_CMDCMPLT_IRQ_EN),
|
||||||
|
apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear DMA interrupt.
|
||||||
|
*
|
||||||
|
* The software that is using the DMA channel must register to receive its
|
||||||
|
* interrupts and, when they arrive, must call this function to clear them.
|
||||||
|
*/
|
||||||
|
static int mxs_dma_ack_irq(int channel)
|
||||||
|
{
|
||||||
|
void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
writel(1 << channel, apbh_regs + HW_APBHX_CTRL1 + BIT_CLR);
|
||||||
|
writel(1 << channel, apbh_regs + HW_APBHX_CTRL2 + BIT_CLR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Request to reserve a DMA channel
|
||||||
|
*/
|
||||||
|
static int mxs_dma_request(int channel)
|
||||||
|
{
|
||||||
|
struct mxs_dma_chan *pchan;
|
||||||
|
|
||||||
|
if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
pchan = mxs_dma_channels + channel;
|
||||||
|
if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
|
||||||
|
return -EBUSY;
|
||||||
|
|
||||||
|
pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
|
||||||
|
pchan->active_num = 0;
|
||||||
|
pchan->pending_num = 0;
|
||||||
|
|
||||||
|
INIT_LIST_HEAD(&pchan->active);
|
||||||
|
INIT_LIST_HEAD(&pchan->done);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Release a DMA channel.
|
||||||
|
*
|
||||||
|
* This function releases a DMA channel from its current owner.
|
||||||
|
*
|
||||||
|
* The channel will NOT be released if it's marked "busy" (see
|
||||||
|
* mxs_dma_enable()).
|
||||||
|
*/
|
||||||
|
static int mxs_dma_release(int channel)
|
||||||
|
{
|
||||||
|
struct mxs_dma_chan *pchan;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
pchan = mxs_dma_channels + channel;
|
||||||
|
|
||||||
|
if (pchan->flags & MXS_DMA_FLAGS_BUSY)
|
||||||
|
return -EBUSY;
|
||||||
|
|
||||||
|
pchan->dev = 0;
|
||||||
|
pchan->active_num = 0;
|
||||||
|
pchan->pending_num = 0;
|
||||||
|
pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Allocate DMA descriptor
|
||||||
|
*/
|
||||||
|
struct mxs_dma_desc *mxs_dma_desc_alloc(void)
|
||||||
|
{
|
||||||
|
struct mxs_dma_desc *pdesc;
|
||||||
|
|
||||||
|
pdesc = dma_alloc_coherent(sizeof(struct mxs_dma_desc));
|
||||||
|
|
||||||
|
if (pdesc == NULL)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
memset(pdesc, 0, sizeof(*pdesc));
|
||||||
|
pdesc->address = (dma_addr_t)pdesc;
|
||||||
|
|
||||||
|
return pdesc;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Free DMA descriptor
|
||||||
|
*/
|
||||||
|
void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
|
||||||
|
{
|
||||||
|
if (pdesc == NULL)
|
||||||
|
return;
|
||||||
|
|
||||||
|
free(pdesc);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Add a DMA descriptor to a channel.
|
||||||
|
*
|
||||||
|
* If the descriptor list for this channel is not empty, this function sets the
|
||||||
|
* CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
|
||||||
|
* it will chain to the new descriptor's command.
|
||||||
|
*
|
||||||
|
* Then, this function marks the new descriptor as "ready," adds it to the end
|
||||||
|
* of the active descriptor list, and increments the count of pending
|
||||||
|
* descriptors.
|
||||||
|
*
|
||||||
|
* The MXS platform DMA software imposes some rules on DMA commands to maintain
|
||||||
|
* important invariants. These rules are NOT checked, but they must be carefully
|
||||||
|
* applied by software that uses MXS DMA channels.
|
||||||
|
*
|
||||||
|
* Invariant:
|
||||||
|
* The DMA channel's hardware semaphore must reflect the number of DMA
|
||||||
|
* commands the hardware will process, but has not yet finished.
|
||||||
|
*
|
||||||
|
* Explanation:
|
||||||
|
* A DMA channel begins processing commands when its hardware semaphore is
|
||||||
|
* written with a value greater than zero, and it stops processing commands
|
||||||
|
* when the semaphore returns to zero.
|
||||||
|
*
|
||||||
|
* When a channel finishes a DMA command, it will decrement its semaphore if
|
||||||
|
* the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
|
||||||
|
*
|
||||||
|
* In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
|
||||||
|
* unless it suits the purposes of the software. For example, one could
|
||||||
|
* construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
|
||||||
|
* bit set only in the last one. Then, setting the DMA channel's hardware
|
||||||
|
* semaphore to one would cause the entire series of five commands to be
|
||||||
|
* processed. However, this example would violate the invariant given above.
|
||||||
|
*
|
||||||
|
* Rule:
|
||||||
|
* ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
|
||||||
|
* channel's hardware semaphore will be decremented EVERY time a command is
|
||||||
|
* processed.
|
||||||
|
*/
|
||||||
|
int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
|
||||||
|
{
|
||||||
|
struct mxs_dma_chan *pchan;
|
||||||
|
struct mxs_dma_desc *last;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
pchan = mxs_dma_channels + channel;
|
||||||
|
|
||||||
|
pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
|
||||||
|
pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
|
||||||
|
|
||||||
|
if (!list_empty(&pchan->active)) {
|
||||||
|
last = list_entry(pchan->active.prev, struct mxs_dma_desc,
|
||||||
|
node);
|
||||||
|
|
||||||
|
pdesc->flags &= ~MXS_DMA_DESC_FIRST;
|
||||||
|
last->flags &= ~MXS_DMA_DESC_LAST;
|
||||||
|
|
||||||
|
last->cmd.next = mxs_dma_cmd_address(pdesc);
|
||||||
|
last->cmd.data |= MXS_DMA_DESC_CHAIN;
|
||||||
|
}
|
||||||
|
pdesc->flags |= MXS_DMA_DESC_READY;
|
||||||
|
if (pdesc->flags & MXS_DMA_DESC_FIRST)
|
||||||
|
pchan->pending_num++;
|
||||||
|
list_add_tail(&pdesc->node, &pchan->active);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clean up processed DMA descriptors.
|
||||||
|
*
|
||||||
|
* This function removes processed DMA descriptors from the "active" list. Pass
|
||||||
|
* in a non-NULL list head to get the descriptors moved to your list. Pass NULL
|
||||||
|
* to get the descriptors moved to the channel's "done" list. Descriptors on
|
||||||
|
* the "done" list can be retrieved with mxs_dma_get_finished().
|
||||||
|
*
|
||||||
|
* This function marks the DMA channel as "not busy" if no unprocessed
|
||||||
|
* descriptors remain on the "active" list.
|
||||||
|
*/
|
||||||
|
static int mxs_dma_finish(int channel, struct list_head *head)
|
||||||
|
{
|
||||||
|
int sem;
|
||||||
|
struct mxs_dma_chan *pchan;
|
||||||
|
struct list_head *p, *q;
|
||||||
|
struct mxs_dma_desc *pdesc;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(channel);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
pchan = mxs_dma_channels + channel;
|
||||||
|
|
||||||
|
sem = mxs_dma_read_semaphore(channel);
|
||||||
|
if (sem < 0)
|
||||||
|
return sem;
|
||||||
|
|
||||||
|
if (sem == pchan->active_num)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
list_for_each_safe(p, q, &pchan->active) {
|
||||||
|
if ((pchan->active_num) <= sem)
|
||||||
|
break;
|
||||||
|
|
||||||
|
pdesc = list_entry(p, struct mxs_dma_desc, node);
|
||||||
|
pdesc->flags &= ~MXS_DMA_DESC_READY;
|
||||||
|
|
||||||
|
if (head)
|
||||||
|
list_move_tail(p, head);
|
||||||
|
else
|
||||||
|
list_move_tail(p, &pchan->done);
|
||||||
|
|
||||||
|
if (pdesc->flags & MXS_DMA_DESC_LAST)
|
||||||
|
pchan->active_num--;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (sem == 0)
|
||||||
|
pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Wait for DMA channel to complete
|
||||||
|
*/
|
||||||
|
static int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
|
||||||
|
{
|
||||||
|
void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = mxs_dma_validate_chan(chan);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
while (--timeout) {
|
||||||
|
if (readl(apbh_regs + HW_APBHX_CTRL1) & (1 << chan))
|
||||||
|
break;
|
||||||
|
udelay(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (timeout == 0) {
|
||||||
|
ret = -ETIMEDOUT;
|
||||||
|
mxs_dma_reset(chan);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Execute the DMA channel
|
||||||
|
*/
|
||||||
|
int mxs_dma_go(int chan)
|
||||||
|
{
|
||||||
|
uint32_t timeout = 10000;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
LIST_HEAD(tmp_desc_list);
|
||||||
|
|
||||||
|
mxs_dma_enable_irq(chan, 1);
|
||||||
|
mxs_dma_enable(chan);
|
||||||
|
|
||||||
|
/* Wait for DMA to finish. */
|
||||||
|
ret = mxs_dma_wait_complete(timeout, chan);
|
||||||
|
|
||||||
|
/* Clear out the descriptors we just ran. */
|
||||||
|
mxs_dma_finish(chan, &tmp_desc_list);
|
||||||
|
|
||||||
|
/* Shut the DMA channel down. */
|
||||||
|
mxs_dma_ack_irq(chan);
|
||||||
|
mxs_dma_reset(chan);
|
||||||
|
mxs_dma_enable_irq(chan, 0);
|
||||||
|
mxs_dma_disable(chan);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize the DMA hardware
|
||||||
|
*/
|
||||||
|
int mxs_dma_init(void)
|
||||||
|
{
|
||||||
|
void __iomem *apbh_regs = (void *)MXS_APBH_BASE;
|
||||||
|
struct mxs_dma_chan *pchan;
|
||||||
|
int ret, channel;
|
||||||
|
u32 val, reg;
|
||||||
|
|
||||||
|
mxs_reset_block(apbh_regs, 0);
|
||||||
|
|
||||||
|
/* HACK: Get CPUID and determine APBH version */
|
||||||
|
val = readl(0x8001c310) >> 16;
|
||||||
|
if (val == 0x2800)
|
||||||
|
reg = MXS_APBH_BASE + 0x0800;
|
||||||
|
else
|
||||||
|
reg = MXS_APBH_BASE + 0x03f0;
|
||||||
|
|
||||||
|
apbh_is_old = (readl((void *)reg) >> 24) < 3;
|
||||||
|
|
||||||
|
writel(BM_APBH_CTRL0_APB_BURST8_EN,
|
||||||
|
apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
|
||||||
|
|
||||||
|
writel(BM_APBH_CTRL0_APB_BURST_EN,
|
||||||
|
apbh_regs + HW_APBHX_CTRL0 + BIT_SET);
|
||||||
|
|
||||||
|
for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
|
||||||
|
pchan = mxs_dma_channels + channel;
|
||||||
|
pchan->flags = MXS_DMA_FLAGS_VALID;
|
||||||
|
|
||||||
|
ret = mxs_dma_request(channel);
|
||||||
|
|
||||||
|
if (ret) {
|
||||||
|
printf("MXS DMA: Can't acquire DMA channel %i\n",
|
||||||
|
channel);
|
||||||
|
|
||||||
|
goto err;
|
||||||
|
}
|
||||||
|
|
||||||
|
mxs_dma_reset(channel);
|
||||||
|
mxs_dma_ack_irq(channel);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err:
|
||||||
|
while (--channel >= 0)
|
||||||
|
mxs_dma_release(channel);
|
||||||
|
return ret;
|
||||||
|
}
|
Loading…
Reference in New Issue