mci s3c: pass around the right pointer
The s3c driver passes around a struct device_d * internally in which it is never interested in. Instead pass around a struct s3c_mci_host and get rid of all this ugly void * derefs. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
7c1e1e3ddf
commit
4f2cf36acb
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@ -160,13 +160,15 @@ struct s3c_mci_host {
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unsigned data_size; /* data transfer in bytes */
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};
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#define to_s3c_host(h) container_of(h, struct s3c_mci_host, host)
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/**
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* Finish a request
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* @param hw_dev Host interface instance
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*
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* Just a little bit paranoia.
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*/
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static void s3c_finish_request(struct device_d *hw_dev)
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static void s3c_finish_request(struct s3c_mci_host *host_data)
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{
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/* TODO ensure the engines are stopped */
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}
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@ -177,11 +179,10 @@ static void s3c_finish_request(struct device_d *hw_dev)
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* @param nc New clock value in Hz (can be 0)
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* @return New clock value (may differ from 'nc')
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*/
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static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
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static unsigned s3c_setup_clock_speed(struct s3c_mci_host *host_data, unsigned nc)
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{
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unsigned clock;
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uint32_t mci_psc;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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if (nc == 0)
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return 0;
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@ -206,10 +207,8 @@ static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc)
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*
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* This will reset everything in all registers of this unit!
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*/
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static void s3c_mci_reset(struct device_d *hw_dev)
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static void s3c_mci_reset(struct s3c_mci_host *host_data)
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{
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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/* reset the hardware */
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writel(SDICON_SDRESET, host_data->base + SDICON);
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/* wait until reset it finished */
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@ -222,14 +221,12 @@ static void s3c_mci_reset(struct device_d *hw_dev)
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* @param hw_dev Host interface instance
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* @param mci_dev MCI device instance (might be NULL)
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*/
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static int s3c_mci_initialize(struct device_d *hw_dev, struct device_d *mci_dev)
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static int s3c_mci_initialize(struct s3c_mci_host *host_data, struct device_d *mci_dev)
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{
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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s3c_mci_reset(hw_dev);
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s3c_mci_reset(host_data);
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/* restore last settings */
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host_data->clock = s3c_setup_clock_speed(hw_dev, host_data->clock);
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host_data->clock = s3c_setup_clock_speed(host_data, host_data->clock);
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writel(0x007FFFFF, host_data->base + SDITIMER);
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writel(SDICON_MMCCLOCK, host_data->base + SDICON);
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writel(512, host_data->base + SDIBSIZE);
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@ -276,9 +273,8 @@ static uint32_t s3c_prepare_command_setup(unsigned cmd_flags, unsigned data_flag
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* @param data_flags MCI's data flags
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* @return Register bits for this transfer
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*/
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static uint32_t s3c_prepare_data_setup(struct device_d *hw_dev, unsigned data_flags)
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static uint32_t s3c_prepare_data_setup(struct s3c_mci_host *host_data, unsigned data_flags)
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{
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struct s3c_mci_host *host_data = (struct s3c_mci_host*)GET_HOST_DATA(hw_dev);
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uint32_t reg = SDIDCON_BLOCKMODE; /* block mode only is supported */
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if (host_data->bus_width == 1)
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@ -305,16 +301,15 @@ static uint32_t s3c_prepare_data_setup(struct device_d *hw_dev, unsigned data_fl
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* Note: Try to stop a running transfer. This should not happen, as all
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* transfers must complete in this driver. But who knows... ;-)
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*/
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static int s3c_terminate_transfer(struct device_d *hw_dev)
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static int s3c_terminate_transfer(struct s3c_mci_host *host_data)
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{
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unsigned stoptries = 3;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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while (readl(host_data->base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) {
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pr_debug("Transfer still in progress.\n");
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writel(SDIDCON_STOP, host_data->base + SDIDCON);
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s3c_mci_initialize(hw_dev, NULL);
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s3c_mci_initialize(host_data, NULL);
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if ((stoptries--) == 0) {
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pr_warning("Cannot stop the engine!\n");
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@ -331,13 +326,12 @@ static int s3c_terminate_transfer(struct device_d *hw_dev)
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* @param data The data information (buffer, direction aso.)
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* @return 0 on success
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*/
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static int s3c_prepare_data_transfer(struct device_d *hw_dev, struct mci_data *data)
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static int s3c_prepare_data_transfer(struct s3c_mci_host *host_data, struct mci_data *data)
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{
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uint32_t reg;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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writel(data->blocksize, host_data->base + SDIBSIZE);
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reg = s3c_prepare_data_setup(hw_dev, data->flags);
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reg = s3c_prepare_data_setup(host_data, data->flags);
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reg |= data->blocks & SDIDCON_BLKNUM;
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writel(reg, host_data->base + SDIDCON);
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writel(0x007FFFFF, host_data->base + SDITIMER);
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@ -352,12 +346,11 @@ static int s3c_prepare_data_transfer(struct device_d *hw_dev, struct mci_data *d
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* @param data The data information (buffer, direction aso.)
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* @return 0 on success
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*/
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static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
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static int s3c_send_command(struct s3c_mci_host *host_data, struct mci_cmd *cmd,
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struct mci_data *data)
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{
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uint32_t reg, t1;
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int rc;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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writel(0x007FFFFF, host_data->base + SDITIMER);
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@ -416,12 +409,11 @@ static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd,
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*
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* FIFO clear is only necessary on 2440, but doesn't hurt on 2410
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*/
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static int s3c_prepare_engine(struct device_d *hw_dev)
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static int s3c_prepare_engine(struct s3c_mci_host *host_data)
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{
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int rc;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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rc = s3c_terminate_transfer(hw_dev);
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rc = s3c_terminate_transfer(host_data);
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if (rc != 0)
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return rc;
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@ -443,15 +435,15 @@ static int s3c_prepare_engine(struct device_d *hw_dev)
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* - "broadcast commands with response (BCR)"
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* - "addressed command (AC)" with response, but without data
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*/
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static int s3c_mci_std_cmds(struct device_d *hw_dev, struct mci_cmd *cmd)
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static int s3c_mci_std_cmds(struct s3c_mci_host *host_data, struct mci_cmd *cmd)
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{
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int rc;
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rc = s3c_prepare_engine(hw_dev);
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rc = s3c_prepare_engine(host_data);
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if (rc != 0)
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return 0;
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return s3c_send_command(hw_dev, cmd, NULL);
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return s3c_send_command(host_data, cmd, NULL);
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}
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/**
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@ -460,11 +452,10 @@ static int s3c_mci_std_cmds(struct device_d *hw_dev, struct mci_cmd *cmd)
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* @param data The data information (buffer, direction aso.)
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* @return 0 on success
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*/
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static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data)
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static int s3c_mci_read_block(struct s3c_mci_host *host_data, struct mci_data *data)
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{
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uint32_t *p;
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unsigned cnt, data_size;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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#define READ_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_RXCRCFAIL | SDIDSTA_DATATIMEOUT)
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@ -514,13 +505,12 @@ static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data)
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* We must ensure data in the FIFO when the command phase changes into the
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* data phase. To ensure this, the FIFO gets filled first, then the command.
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*/
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static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
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static int s3c_mci_write_block(struct s3c_mci_host *host_data, struct mci_cmd *cmd,
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struct mci_data *data)
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{
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const uint32_t *p = (const uint32_t*)data->src;
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unsigned cnt, data_size;
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uint32_t reg;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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#define WRITE_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_DATATIMEOUT)
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@ -543,7 +533,7 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
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}
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/* data is now in place and waits for transmitt. Start the command right now */
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s3c_send_command(hw_dev, cmd, data);
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s3c_send_command(host_data, cmd, data);
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if ((reg = readl(host_data->base + SDIFSTA)) & SDIFSTA_FIFOFAIL) {
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pr_err("Command fails immediatly due to FIFO underrun when writing %08X\n",
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@ -591,37 +581,36 @@ static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd,
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* @param data The data information (buffer, direction aso.)
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* @return 0 on success
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*/
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static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
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static int s3c_mci_adtc(struct s3c_mci_host *host_data, struct mci_cmd *cmd,
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struct mci_data *data)
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{
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int rc;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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rc = s3c_prepare_engine(hw_dev);
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rc = s3c_prepare_engine(host_data);
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if (rc != 0)
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return rc;
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rc = s3c_prepare_data_transfer(hw_dev, data);
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rc = s3c_prepare_data_transfer(host_data, data);
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if (rc != 0)
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return rc;
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if (data->flags & MMC_DATA_READ) {
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s3c_send_command(hw_dev, cmd, data);
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rc = s3c_mci_read_block(hw_dev, data);
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s3c_send_command(host_data, cmd, data);
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rc = s3c_mci_read_block(host_data, data);
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if (rc == 0) {
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while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
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;
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} else
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s3c_terminate_transfer(hw_dev);
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s3c_terminate_transfer(host_data);
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}
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if (data->flags & MMC_DATA_WRITE) {
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rc = s3c_mci_write_block(hw_dev, cmd, data);
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rc = s3c_mci_write_block(host_data, cmd, data);
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if (rc == 0) {
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while (!(readl(host_data->base + SDIDSTA) & SDIDSTA_XFERFINISH))
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;
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} else
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s3c_terminate_transfer(hw_dev);
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s3c_terminate_transfer(host_data);
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}
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writel(0, host_data->base + SDIDCON);
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@ -632,29 +621,28 @@ static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd,
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/**
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* Keep the attached MMC/SD unit in a well know state
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* @param mci_pdata MCI platform data
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* @param host MCI host
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* @param mci_dev MCI device instance
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* @return 0 on success, negative value else
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*/
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static int mci_reset(struct mci_host *mci_pdata, struct device_d *mci_dev)
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static int mci_reset(struct mci_host *host, struct device_d *mci_dev)
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{
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struct device_d *hw_dev = mci_pdata->hw_dev;
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struct s3c_mci_host *host_data = to_s3c_host(host);
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return s3c_mci_initialize(hw_dev, mci_dev);
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return s3c_mci_initialize(host_data, mci_dev);
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}
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/**
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* Process one command to the MCI card
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* @param mci_pdata MCI platform data
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* @param host MCI host
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* @param cmd The command to process
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* @param data The data to handle in the command (can be NULL)
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* @return 0 on success, negative value else
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*/
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static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
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static int mci_request(struct mci_host *host, struct mci_cmd *cmd,
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struct mci_data *data)
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{
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struct device_d *hw_dev = mci_pdata->hw_dev;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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struct s3c_mci_host *host_data = to_s3c_host(host);
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int rc;
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/* enable clock */
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@ -662,11 +650,11 @@ static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
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host_data->base + SDICON);
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if ((cmd->resp_type == 0) || (data == NULL))
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rc = s3c_mci_std_cmds(hw_dev, cmd);
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rc = s3c_mci_std_cmds(host_data, cmd);
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else
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rc = s3c_mci_adtc(hw_dev, cmd, data); /* with response and data */
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rc = s3c_mci_adtc(host_data, cmd, data); /* with response and data */
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s3c_finish_request(hw_dev);
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s3c_finish_request(host_data);
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/* disable clock */
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writel(readl(host_data->base + SDICON) & ~SDICON_CLKEN,
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@ -676,16 +664,15 @@ static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd,
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/**
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* Setup the bus width and IO speed
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* @param mci_pdata MCI platform data
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* @param host MCI host
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* @param mci_dev MCI device instance
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* @param bus_width New bus width value (1, 4 or 8)
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* @param clock New clock in Hz (can be '0' to disable the clock)
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*/
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static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev,
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static void mci_set_ios(struct mci_host *host, struct device_d *mci_dev,
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struct mci_ios *ios)
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{
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struct device_d *hw_dev = mci_pdata->hw_dev;
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struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev);
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struct s3c_mci_host *host_data = to_s3c_host(host);
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uint32_t reg;
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switch (ios->bus_width) {
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@ -702,7 +689,7 @@ static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev,
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reg = readl(host_data->base + SDICON);
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if (ios->clock) {
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/* setup the IO clock frequency and enable it */
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host_data->clock = s3c_setup_clock_speed(hw_dev, ios->clock);
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host_data->clock = s3c_setup_clock_speed(host_data, ios->clock);
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reg |= SDICON_CLKEN; /* enable the clock */
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} else {
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reg &= ~SDICON_CLKEN; /* disable the clock */
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@ -770,7 +757,7 @@ static int s3c_mci_probe(struct device_d *hw_dev)
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/*
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* Start the clock to let the engine and the card finishes its startup
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*/
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s3c_host->clock = s3c_setup_clock_speed(hw_dev, pd->f_min);
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s3c_host->clock = s3c_setup_clock_speed(s3c_host, pd->f_min);
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writel(SDICON_FIFORESET | SDICON_MMCCLOCK, s3c_host->base + SDICON);
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return mci_register(&s3c_host->host);
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