arm: add support for the i.MX53 loco board
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Marc Kleine-Budde
Sascha Hauer
parent
9eaaf1b1ca
commit
5ba0502901
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@ -18,6 +18,7 @@ ARM type:
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@li @subpage the3stack
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@li @subpage mx23_evk
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@li @subpage board_babage
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@li @subpage board_loco
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@li @subpage chumbyone
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@li @subpage scb9328
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@li @subpage netx
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@ -102,6 +102,7 @@ board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk
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board-$(CONFIG_MACH_CHUMBY) := chumby_falconwing
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board-$(CONFIG_MACH_TX28) := karo-tx28
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board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := freescale-mx51-pdk
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board-$(CONFIG_MACH_FREESCALE_MX53_LOCO) := freescale-mx53-loco
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board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid
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board-$(CONFIG_MACH_MINI2440) := mini2440
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board-$(CONFIG_MACH_VERSATILEPB) := versatile
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@ -0,0 +1,3 @@
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obj-y += lowlevel_init.o
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obj-y += board.o
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obj-y += flash_header.o
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@ -0,0 +1,152 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <environment.h>
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#include <fcntl.h>
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#include <fec.h>
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#include <fs.h>
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#include <init.h>
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#include <nand.h>
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#include <net.h>
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#include <partition.h>
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#include <sizes.h>
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#include <generated/mach-types.h>
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#include <mach/imx-regs.h>
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#include <mach/iomux-mx53.h>
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#include <mach/devices-imx53.h>
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#include <mach/generic.h>
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#include <mach/gpio.h>
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#include <mach/imx-nand.h>
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#include <mach/iim.h>
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#include <asm/armlinux.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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static struct fec_platform_data fec_info = {
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.xcv_type = RMII,
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};
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static struct pad_desc loco_pads[] = {
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/* UART1 */
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
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/* FEC */
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MX53_PAD_FEC_MDC__FEC_MDC,
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MX53_PAD_FEC_MDIO__FEC_MDIO,
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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MX53_PAD_FEC_TX_EN__FEC_TX_EN,
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MX53_PAD_FEC_TXD1__FEC_TDATA_1,
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MX53_PAD_FEC_TXD0__FEC_TDATA_0,
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/* FEC_nRST */
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MX53_PAD_PATA_DA_0__GPIO7_6,
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/* SD1 */
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MX53_PAD_SD1_CMD__ESDHC1_CMD,
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MX53_PAD_SD1_CLK__ESDHC1_CLK,
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
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/* SD1_CD */
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MX53_PAD_EIM_DA13__GPIO3_13,
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};
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#ifdef CONFIG_MMU
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static void loco_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0x70000000, 0x70000000, 512, PMD_SECT_DEF_CACHED);
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arm_create_section(0x90000000, 0x70000000, 512, PMD_SECT_DEF_UNCACHED);
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arm_create_section(0xb0000000, 0xb0000000, 512, PMD_SECT_DEF_CACHED);
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arm_create_section(0xd0000000, 0xb0000000, 512, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x20000000);
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mmu_enable();
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}
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#else
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static void loco_mmu_init(void)
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{
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}
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#endif
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#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
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static void loco_fec_reset(void)
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{
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gpio_direction_output(LOCO_FEC_PHY_RST, 0);
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mdelay(1);
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gpio_set_value(LOCO_FEC_PHY_RST, 1);
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}
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static int loco_devices_init(void)
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{
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struct device_d *sdram_dev;
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loco_mmu_init();
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sdram_dev = add_mem_device("ram0", 0x70000000, SZ_512M,
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IORESOURCE_MEM_WRITEABLE);
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armlinux_add_dram(sdram_dev);
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sdram_dev = add_mem_device("ram1", 0xb0000000, SZ_512M,
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IORESOURCE_MEM_WRITEABLE);
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armlinux_add_dram(sdram_dev);
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imx51_iim_register_fec_ethaddr();
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imx53_add_fec(&fec_info);
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imx53_add_mmc0(NULL);
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loco_fec_reset();
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armlinux_set_bootparams((void *)0x70000100);
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armlinux_set_architecture(MACH_TYPE_MX53_LOCO);
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loco_fec_reset();
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return 0;
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}
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device_initcall(loco_devices_init);
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static int loco_part_init(void)
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{
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devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
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devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
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return 0;
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}
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late_initcall(loco_part_init);
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static int loco_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(loco_pads, ARRAY_SIZE(loco_pads));
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imx53_add_uart0();
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return 0;
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}
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console_initcall(loco_console_init);
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@ -0,0 +1,24 @@
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/**
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* @file
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* @brief Global defintions for the ARM i.MX51 based babbage board
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#endif /* __CONFIG_H */
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@ -0,0 +1,51 @@
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#!/bin/sh
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machine=loco
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eth0.serverip=
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user=
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# use 'dhcp' to do dhcp in barebox and in kernel
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# use 'none' if you want to skip kernel ip autoconfiguration
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ip=dhcp
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# or set your networking parameters here
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#eth0.ipaddr=a.b.c.d
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#eth0.netmask=a.b.c.d
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#eth0.gateway=a.b.c.d
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#eth0.serverip=a.b.c.d
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# can be either 'nfs', 'tftp', 'nor' or 'nand'
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kernel_loc=tftp
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# can be either 'net', 'nor', 'nand' or 'initrd'
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rootfs_loc=net
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# can be either 'jffs2' or 'ubifs'
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rootfs_type=ubifs
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rootfsimage=root-$machine.$rootfs_type
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# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
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kernelimage_type=zimage
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kernelimage=zImage-$machine
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#kernelimage_type=uimage
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#kernelimage=uImage-$machine
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#kernelimage_type=raw
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#kernelimage=Image-$machine
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#kernelimage_type=raw_lzo
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#kernelimage=Image-$machine.lzo
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if [ -n $user ]; then
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kernelimage="$user"-"$kernelimage"
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nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
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rootfsimage="$user"-"$rootfsimage"
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else
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nfsroot="$eth0.serverip:/path/to/nfs/root"
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fi
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autoboot_timeout=3
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bootargs="console=ttymxc0,115200"
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disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)"
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# set a fancy prompt (if support is compiled in)
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PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2011 Marc Kleine-Budde <mkl@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <common.h>
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#include <asm/byteorder.h>
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#include <mach/imx-flash-header.h>
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void __naked __flash_header_start go(void)
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{
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__asm__ __volatile__("b exception_vectors\n");
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}
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struct imx_dcd_v2_entry __dcd_entry_section dcd_entry[] = {
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{ .addr = cpu_to_be32(0x53fa8554), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8558), .val = cpu_to_be32(0x00300040), },
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{ .addr = cpu_to_be32(0x53fa8560), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8564), .val = cpu_to_be32(0x00300040), },
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{ .addr = cpu_to_be32(0x53fa8568), .val = cpu_to_be32(0x00300040), },
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{ .addr = cpu_to_be32(0x53fa8570), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8574), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8578), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa857c), .val = cpu_to_be32(0x00300040), },
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{ .addr = cpu_to_be32(0x53fa8580), .val = cpu_to_be32(0x00300040), },
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{ .addr = cpu_to_be32(0x53fa8584), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8588), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8590), .val = cpu_to_be32(0x00300040), },
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{ .addr = cpu_to_be32(0x53fa8594), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa86f0), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa86f4), .val = cpu_to_be32(0x00000000), },
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{ .addr = cpu_to_be32(0x53fa86fc), .val = cpu_to_be32(0x00000000), },
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{ .addr = cpu_to_be32(0x53fa8714), .val = cpu_to_be32(0x00000000), },
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{ .addr = cpu_to_be32(0x53fa8718), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa871c), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8720), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa8724), .val = cpu_to_be32(0x04000000), },
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{ .addr = cpu_to_be32(0x53fa8728), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x53fa872c), .val = cpu_to_be32(0x00300000), },
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{ .addr = cpu_to_be32(0x63fd9088), .val = cpu_to_be32(0x35343535), },
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{ .addr = cpu_to_be32(0x63fd9090), .val = cpu_to_be32(0x4d444c44), },
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{ .addr = cpu_to_be32(0x63fd907c), .val = cpu_to_be32(0x01370138), },
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{ .addr = cpu_to_be32(0x63fd9080), .val = cpu_to_be32(0x013b013c), },
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{ .addr = cpu_to_be32(0x63fd9018), .val = cpu_to_be32(0x00011740), },
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{ .addr = cpu_to_be32(0x63fd9000), .val = cpu_to_be32(0xc3190000), },
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{ .addr = cpu_to_be32(0x63fd900c), .val = cpu_to_be32(0x9f5152e3), },
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{ .addr = cpu_to_be32(0x63fd9010), .val = cpu_to_be32(0xb68e8a63), },
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{ .addr = cpu_to_be32(0x63fd9014), .val = cpu_to_be32(0x01ff00db), },
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{ .addr = cpu_to_be32(0x63fd902c), .val = cpu_to_be32(0x000026d2), },
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{ .addr = cpu_to_be32(0x63fd9030), .val = cpu_to_be32(0x009f0e21), },
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{ .addr = cpu_to_be32(0x63fd9008), .val = cpu_to_be32(0x12273030), },
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{ .addr = cpu_to_be32(0x63fd9004), .val = cpu_to_be32(0x0002002d), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008032), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00008033), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028031), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x092080b0), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008040), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803a), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x0000803b), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00028039), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x09208138), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x04008048), },
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{ .addr = cpu_to_be32(0x63fd9020), .val = cpu_to_be32(0x00001800), },
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{ .addr = cpu_to_be32(0x63fd9040), .val = cpu_to_be32(0x04b80003), },
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{ .addr = cpu_to_be32(0x63fd9058), .val = cpu_to_be32(0x00022227), },
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{ .addr = cpu_to_be32(0x63fd901c), .val = cpu_to_be32(0x00000000), },
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};
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#define APP_DEST CONFIG_TEXT_BASE
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struct imx_flash_header_v2 __flash_header_section flash_header = {
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.header.tag = IVT_HEADER_TAG,
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.header.length = cpu_to_be16(32),
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.header.version = IVT_VERSION,
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.entry = APP_DEST + 0x1000,
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.dcd_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, dcd),
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.boot_data_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header_v2, boot_data),
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.self = APP_DEST + 0x400,
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.boot_data.start = APP_DEST,
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.boot_data.size = 0x40000,
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.dcd.header.tag = DCD_HEADER_TAG,
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.dcd.header.length = cpu_to_be16(sizeof(struct imx_dcd) + sizeof(dcd_entry)),
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.dcd.header.version = DCD_VERSION,
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.dcd.command.tag = DCD_COMMAND_WRITE_TAG,
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.dcd.command.length = cpu_to_be16(sizeof(struct imx_dcd_command) + sizeof(dcd_entry)),
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.dcd.command.param = DCD_COMMAND_WRITE_PARAM,
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};
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@ -0,0 +1,172 @@
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/*
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* Copyright (C) 2007 Guennadi Liakhovetski <lg@denx.de>
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* Copyright (C) 2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
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* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include <mach/clock-imx51_53.h>
|
||||
|
||||
/*
|
||||
* L2CC Cache setup/invalidation/disable
|
||||
*/
|
||||
.macro init_l2cc
|
||||
/* explicitly disable L2 cache */
|
||||
mrc 15, 0, r0, c1, c0, 1
|
||||
bic r0, r0, #0x2
|
||||
mcr 15, 0, r0, c1, c0, 1
|
||||
|
||||
/* reconfigure L2 cache aux control reg */
|
||||
mov r0, #0xC0 /* tag RAM */
|
||||
add r0, r0, #0x4 /* data RAM */
|
||||
orr r0, r0, #(1 << 24) /* disable write allocate delay */
|
||||
orr r0, r0, #(1 << 23) /* disable write allocate combine */
|
||||
orr r0, r0, #(1 << 22) /* disable write allocate */
|
||||
|
||||
cmp r3, #0x10 /* r3 contains the silicon rev */
|
||||
|
||||
/* disable write combine for TO 2 and lower revs */
|
||||
orrls r0, r0, #(1 << 25)
|
||||
|
||||
mcr 15, 1, r0, c9, c0, 2
|
||||
.endm /* init_l2cc */
|
||||
|
||||
/* AIPS setup - Only setup MPROTx registers.
|
||||
* The PACR default values are good.*/
|
||||
.macro init_aips
|
||||
/*
|
||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||
* not forced to user-mode.
|
||||
*/
|
||||
ldr r0, =MX53_AIPS1_BASE_ADDR
|
||||
ldr r1, =0x77777777
|
||||
str r1, [r0, #0x0]
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
ldr r0, =MX53_AIPS2_BASE_ADDR
|
||||
str r1, [r0, #0x0]
|
||||
str r1, [r0, #0x4]
|
||||
/*
|
||||
* Clear the on and off peripheral modules Supervisor Protect bit
|
||||
* for SDMA to access them. Did not change the AIPS control registers
|
||||
* (offset 0x20) access type
|
||||
*/
|
||||
.endm /* init_aips */
|
||||
|
||||
.macro setup_pll pll, freq
|
||||
ldr r0, =\pll
|
||||
ldr r1, =0x00001232
|
||||
str r1, [r0, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
|
||||
mov r1, #0x2
|
||||
str r1, [r0, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
|
||||
|
||||
ldr r1, W_DP_OP_\freq
|
||||
str r1, [r0, #MX5_PLL_DP_OP]
|
||||
str r1, [r0, #MX5_PLL_DP_HFS_OP]
|
||||
|
||||
ldr r1, W_DP_MFD_\freq
|
||||
str r1, [r0, #MX5_PLL_DP_MFD]
|
||||
str r1, [r0, #MX5_PLL_DP_HFS_MFD]
|
||||
|
||||
ldr r1, W_DP_MFN_\freq
|
||||
str r1, [r0, #MX5_PLL_DP_MFN]
|
||||
str r1, [r0, #MX5_PLL_DP_HFS_MFN]
|
||||
|
||||
ldr r1, =0x00001232
|
||||
str r1, [r0, #MX5_PLL_DP_CTL]
|
||||
1: ldr r1, [r0, #MX5_PLL_DP_CTL]
|
||||
ands r1, r1, #0x1
|
||||
beq 1b
|
||||
.endm
|
||||
|
||||
.macro init_clock
|
||||
ldr r0, =MX53_CCM_BASE_ADDR
|
||||
|
||||
|
||||
/* Switch ARM to step clock */
|
||||
mov r1, #0x4
|
||||
str r1, [r0, #MX5_CCM_CCSR]
|
||||
|
||||
setup_pll MX53_PLL1_BASE_ADDR, 1000
|
||||
setup_pll MX53_PLL3_BASE_ADDR, 216
|
||||
|
||||
/* Set the platform clock dividers */
|
||||
ldr r0, =MX53_ARM_BASE_ADDR
|
||||
ldr r1, =0x00000725
|
||||
str r1, [r0, #0x14]
|
||||
|
||||
ldr r0, =MX53_CCM_BASE_ADDR
|
||||
mov r1, #0
|
||||
str r1, [r0, #MX5_CCM_CACRR]
|
||||
|
||||
/* Switch ARM back to PLL 1 */
|
||||
mov r1, #0
|
||||
str r1, [r0, #MX5_CCM_CCSR]
|
||||
|
||||
|
||||
/* Restore the default values in the Gate registers */
|
||||
ldr r1, =0xFFFFFFFF
|
||||
str r1, [r0, #MX5_CCM_CCGR0]
|
||||
str r1, [r0, #MX5_CCM_CCGR1]
|
||||
str r1, [r0, #MX5_CCM_CCGR2]
|
||||
str r1, [r0, #MX5_CCM_CCGR3]
|
||||
str r1, [r0, #MX5_CCM_CCGR4]
|
||||
str r1, [r0, #MX5_CCM_CCGR5]
|
||||
str r1, [r0, #MX5_CCM_CCGR6]
|
||||
#if 0
|
||||
str r1, [r0, #MX5_CCM_CCGR7]
|
||||
#endif
|
||||
|
||||
ldr r1, [r0, #MX5_CCM_CSCDR1]
|
||||
orr r1, r1, #0x3f
|
||||
eor r1, r1, #0x3f
|
||||
orr r1, r1, #0x21
|
||||
str r1, [r0, #MX5_CCM_CSCDR1]
|
||||
/* make sure divider effective */
|
||||
1: ldr r1, [r0, #MX5_CCM_CDHIPR]
|
||||
cmp r1, #0x0
|
||||
bne 1b
|
||||
|
||||
mov r1, #0x0
|
||||
str r1, [r0, #MX5_CCM_CCDR]
|
||||
|
||||
/* for cko - for ARM div by 8 */
|
||||
mov r1, #0x000A0000
|
||||
add r1, r1, #0x00000F0
|
||||
str r1, [r0, #MX5_CCM_CCOSR]
|
||||
.endm
|
||||
|
||||
.globl board_init_lowlevel
|
||||
board_init_lowlevel:
|
||||
mov r10, lr
|
||||
|
||||
init_l2cc
|
||||
init_aips
|
||||
init_clock
|
||||
|
||||
mov pc, r10
|
||||
|
||||
/* Board level setting value */
|
||||
W_DP_OP_1000: .word MX5_PLL_DP_OP_1000
|
||||
W_DP_MFD_1000: .word MX5_PLL_DP_MFD_1000
|
||||
W_DP_MFN_1000: .word MX5_PLL_DP_MFN_1000
|
||||
W_DP_OP_800: .word MX5_PLL_DP_OP_800
|
||||
W_DP_MFD_800: .word MX5_PLL_DP_MFD_800
|
||||
W_DP_MFN_800: .word MX5_PLL_DP_MFN_800
|
||||
W_DP_OP_665: .word MX5_PLL_DP_OP_665
|
||||
W_DP_MFD_665: .word MX5_PLL_DP_MFD_665
|
||||
W_DP_MFN_665: .word MX5_PLL_DP_MFN_665
|
||||
W_DP_OP_216: .word MX5_PLL_DP_OP_216
|
||||
W_DP_MFD_216: .word MX5_PLL_DP_MFD_216
|
||||
W_DP_MFN_216: .word MX5_PLL_DP_MFN_216
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
/** @page board_loco Freescale i.MX53 PDK (Loco) Board
|
||||
|
||||
|
||||
*/
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
CONFIG_ARCH_IMX=y
|
||||
CONFIG_ARCH_IMX53=y
|
||||
CONFIG_IMX_IIM=y
|
||||
CONFIG_IMX_IIM_FUSE_BLOW=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||
CONFIG_ARM_UNWIND=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_TEXT_BASE=0x7ff00000
|
||||
CONFIG_MALLOC_SIZE=0x2000000
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_LONGHELP=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_HUSH_FANCY_PROMPT=y
|
||||
CONFIG_CMDLINE_EDITING=y
|
||||
CONFIG_AUTO_COMPLETE=y
|
||||
CONFIG_PARTITION=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
|
||||
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx53-loco/env/"
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_CMD_EDIT=y
|
||||
CONFIG_CMD_SLEEP=y
|
||||
CONFIG_CMD_SAVEENV=y
|
||||
CONFIG_CMD_LOADENV=y
|
||||
CONFIG_CMD_EXPORT=y
|
||||
CONFIG_CMD_PRINTENV=y
|
||||
CONFIG_CMD_READLINE=y
|
||||
CONFIG_CMD_ECHO_E=y
|
||||
CONFIG_CMD_MEMINFO=y
|
||||
CONFIG_CMD_FLASH=y
|
||||
CONFIG_CMD_RESET=y
|
||||
CONFIG_CMD_GO=y
|
||||
CONFIG_CMD_TIMEOUT=y
|
||||
CONFIG_CMD_PARTITION=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_UNLZO=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_NET_DHCP=y
|
||||
CONFIG_NET_NFS=y
|
||||
CONFIG_NET_PING=y
|
||||
CONFIG_NET_TFTP=y
|
||||
CONFIG_NET_TFTP_PUSH=y
|
||||
CONFIG_NET_NETCONSOLE=y
|
||||
CONFIG_DRIVER_NET_FEC_IMX=y
|
||||
# CONFIG_SPI is not set
|
||||
CONFIG_MCI=y
|
||||
CONFIG_MCI_STARTUP=y
|
||||
CONFIG_MCI_IMX_ESDHC=y
|
||||
CONFIG_FS_FAT=y
|
||||
CONFIG_FS_FAT_WRITE=y
|
||||
CONFIG_FS_FAT_LFN=y
|
||||
|
|
@ -19,6 +19,7 @@ config ARCH_TEXT_BASE
|
|||
default 0x08f80000 if MACH_SCB9328
|
||||
default 0xa7e00000 if MACH_NESO
|
||||
default 0x97f00000 if MACH_MX51_PDK
|
||||
default 0x7ff00000 if MACH_MX53_LOCO
|
||||
default 0x87f00000 if MACH_GUF_CUPID
|
||||
default 0x93d00000 if MACH_TX25
|
||||
|
||||
|
|
@ -38,6 +39,7 @@ config BOARDINFO
|
|||
default "Synertronixx scb9328" if MACH_SCB9328
|
||||
default "Garz+Fricke Neso" if MACH_NESO
|
||||
default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK
|
||||
default "Freescale i.MX53 LOCO" if MACH_FREESCALE_MX53_LOCO
|
||||
default "Garz+Fricke Cupid" if MACH_GUF_CUPID
|
||||
default "Ka-Ro tx25" if MACH_TX25
|
||||
|
||||
|
|
@ -410,6 +412,11 @@ choice
|
|||
|
||||
prompt "i.MX53 Board Type"
|
||||
|
||||
config MACH_FREESCALE_MX53_LOCO
|
||||
bool "Freescale i.MX53 LOCO"
|
||||
select HAVE_MMU
|
||||
select MACH_HAS_LOWLEVEL_INIT
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue