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ARM: AM33xx: Add i2c support for AM33xx 

Added device register functions and cpu_is_am33xx()
function.
Adapted the i2c-omap driver. AM335x has a lower
clock rate and the timeout of polling the isr function
had to be increased.

Based on a patch from Shravan Kumar <shravan.k@phytec.in>.

Signed-off-by: Teresa Gámez <t.gamez@phytec.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Teresa Gámez 2013-06-20 14:50:29 +02:00 committed by Sascha Hauer
parent 15f011138a
commit 5e7c87a269
4 changed files with 35 additions and 5 deletions
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15
arch/arm/mach-omap/include/mach/am33xx-devices.h
View File

@ -53,4 +53,19 @@ static inline struct device_d *am33xx_add_spi1(void)
return am33xx_add_spi(1, AM33XX_MCSPI1_BASE);
}
static inline struct device_d *am33xx_add_i2c0(void *pdata)
{
return omap_add_i2c(0, AM33XX_I2C0_BASE, pdata);
}
static inline struct device_d *am33xx_add_i2c1(void *pdata)
{
return omap_add_i2c(1, AM33XX_I2C1_BASE, pdata);
}
static inline struct device_d *am33xx_add_i2c2(void *pdata)
{
return omap_add_i2c(2, AM33XX_I2C2_BASE, pdata);
}
#endif /* __MACH_OMAP3_DEVICES_H */

5
arch/arm/mach-omap/include/mach/am33xx-silicon.h
View File

@ -41,6 +41,11 @@
#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000
#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000
/* I2C */
#define AM33XX_I2C0_BASE (AM33XX_L4_WKUP_BASE + 0x20B000)
#define AM33XX_I2C1_BASE (AM33XX_L4_PER_BASE + 0x02A000)
#define AM33XX_I2C2_BASE (AM33XX_L4_PER_BASE + 0x19C000)
/* GPMC */
#define AM33XX_GPMC_BASE 0x50000000

6
arch/arm/mach-omap/include/mach/generic.h
View File

@ -27,4 +27,10 @@
#define cpu_is_omap4xxx() (0)
#endif
#ifdef CONFIG_ARCH_AM33XX
#define cpu_is_am33xx() (1)
#else
#define cpu_is_am33xx() (0)
#endif
#endif

14
drivers/i2c/busses/i2c-omap.c
View File

@ -245,7 +245,7 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_struct *i2c_omap, int reg)
static void omap_i2c_unidle(struct omap_i2c_struct *i2c_omap)
{
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() || cpu_is_am33xx()) {
omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0);
omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, i2c_omap->pscstate);
omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLL_REG, i2c_omap->scllstate);
@ -353,7 +353,11 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap)
internal_clk = 9600;
else
internal_clk = 4000;
fclk_rate = 96000000 / 1000;
if (cpu_is_am33xx())
fclk_rate = 48000;
else
fclk_rate = 96000;
/* Compute prescaler divisor */
psc = fclk_rate / internal_clk;
@ -410,7 +414,7 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap)
OMAP_I2C_IE_AL) | ((i2c_omap->fifo_size) ?
(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, i2c_omap->iestate);
if (cpu_is_omap34xx()) {
if (cpu_is_omap34xx() || cpu_is_am33xx()) {
i2c_omap->pscstate = psc;
i2c_omap->scllstate = scll;
i2c_omap->sclhstate = sclh;
@ -665,7 +669,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adapter,
ret = omap_i2c_isr(i2c_omap);
while (ret){
ret = omap_i2c_isr(i2c_omap);
if (is_timeout(start, MSECOND)) {
if (is_timeout(start, 50 * MSECOND)) {
dev_err(&adapter->dev,
"timed out on polling for "
"open i2c message handling\n");
@ -743,7 +747,7 @@ i2c_omap_probe(struct device_d *pdev)
goto err_free_mem;
}
if (cpu_is_omap4xxx()) {
if (cpu_is_omap4xxx() || cpu_is_am33xx()) {
i2c_omap->regs = (u8 *)omap4_reg_map;
i2c_omap->reg_shift = 0;
} else {