ARM: AM33xx: Add i2c support for AM33xx
Added device register functions and cpu_is_am33xx() function. Adapted the i2c-omap driver. AM335x has a lower clock rate and the timeout of polling the isr function had to be increased. Based on a patch from Shravan Kumar <shravan.k@phytec.in>. Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -53,4 +53,19 @@ static inline struct device_d *am33xx_add_spi1(void)
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return am33xx_add_spi(1, AM33XX_MCSPI1_BASE);
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}
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static inline struct device_d *am33xx_add_i2c0(void *pdata)
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{
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return omap_add_i2c(0, AM33XX_I2C0_BASE, pdata);
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}
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static inline struct device_d *am33xx_add_i2c1(void *pdata)
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{
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return omap_add_i2c(1, AM33XX_I2C1_BASE, pdata);
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}
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static inline struct device_d *am33xx_add_i2c2(void *pdata)
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{
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return omap_add_i2c(2, AM33XX_I2C2_BASE, pdata);
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}
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#endif /* __MACH_OMAP3_DEVICES_H */
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@ -41,6 +41,11 @@
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#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000
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#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000
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/* I2C */
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#define AM33XX_I2C0_BASE (AM33XX_L4_WKUP_BASE + 0x20B000)
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#define AM33XX_I2C1_BASE (AM33XX_L4_PER_BASE + 0x02A000)
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#define AM33XX_I2C2_BASE (AM33XX_L4_PER_BASE + 0x19C000)
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/* GPMC */
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#define AM33XX_GPMC_BASE 0x50000000
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@ -27,4 +27,10 @@
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#define cpu_is_omap4xxx() (0)
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#endif
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#ifdef CONFIG_ARCH_AM33XX
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#define cpu_is_am33xx() (1)
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#else
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#define cpu_is_am33xx() (0)
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#endif
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#endif
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@ -245,7 +245,7 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_struct *i2c_omap, int reg)
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static void omap_i2c_unidle(struct omap_i2c_struct *i2c_omap)
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{
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if (cpu_is_omap34xx()) {
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if (cpu_is_omap34xx() || cpu_is_am33xx()) {
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omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0);
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omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, i2c_omap->pscstate);
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omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLL_REG, i2c_omap->scllstate);
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@ -353,7 +353,11 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap)
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internal_clk = 9600;
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else
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internal_clk = 4000;
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fclk_rate = 96000000 / 1000;
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if (cpu_is_am33xx())
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fclk_rate = 48000;
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else
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fclk_rate = 96000;
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/* Compute prescaler divisor */
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psc = fclk_rate / internal_clk;
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@ -410,7 +414,7 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap)
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OMAP_I2C_IE_AL) | ((i2c_omap->fifo_size) ?
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(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
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omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, i2c_omap->iestate);
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if (cpu_is_omap34xx()) {
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if (cpu_is_omap34xx() || cpu_is_am33xx()) {
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i2c_omap->pscstate = psc;
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i2c_omap->scllstate = scll;
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i2c_omap->sclhstate = sclh;
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@ -665,7 +669,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adapter,
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ret = omap_i2c_isr(i2c_omap);
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while (ret){
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ret = omap_i2c_isr(i2c_omap);
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if (is_timeout(start, MSECOND)) {
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if (is_timeout(start, 50 * MSECOND)) {
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dev_err(&adapter->dev,
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"timed out on polling for "
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"open i2c message handling\n");
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@ -743,7 +747,7 @@ i2c_omap_probe(struct device_d *pdev)
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goto err_free_mem;
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}
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if (cpu_is_omap4xxx()) {
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if (cpu_is_omap4xxx() || cpu_is_am33xx()) {
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i2c_omap->regs = (u8 *)omap4_reg_map;
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i2c_omap->reg_shift = 0;
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} else {
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