dts: update to v3.15-rc3
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
41ae766fb9
commit
6bef4dd595
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@ -29,7 +29,7 @@
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/* 10 (register bit affects spdif_in and spdif_out) */
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#define TEGRA124_CLK_I2S1 11
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#define TEGRA124_CLK_I2C1 12
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#define TEGRA124_CLK_NDFLASH 13
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/* 13 */
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#define TEGRA124_CLK_SDMMC1 14
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#define TEGRA124_CLK_SDMMC4 15
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/* 16 */
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@ -83,7 +83,7 @@
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/* 64 */
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#define TEGRA124_CLK_UARTD 65
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#define TEGRA124_CLK_UARTE 66
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/* 66 */
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#define TEGRA124_CLK_I2C3 67
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#define TEGRA124_CLK_SBC4 68
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#define TEGRA124_CLK_SDMMC3 69
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@ -97,7 +97,7 @@
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#define TEGRA124_CLK_TRACE 77
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#define TEGRA124_CLK_SOC_THERM 78
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#define TEGRA124_CLK_DTV 79
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#define TEGRA124_CLK_NDSPEED 80
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/* 80 */
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#define TEGRA124_CLK_I2CSLOW 81
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#define TEGRA124_CLK_DSIB 82
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#define TEGRA124_CLK_TSEC 83
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@ -183,7 +183,7 @@
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&usb {
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status = "okay";
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control@44e10000 {
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control@44e10620 {
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status = "okay";
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};
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@ -204,7 +204,7 @@
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dr_mode = "host";
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};
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dma-controller@07402000 {
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dma-controller@47402000 {
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status = "okay";
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};
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};
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@ -301,8 +301,8 @@
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am335x_evm_audio_pins: am335x_evm_audio_pins {
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pinctrl-single,pins = <
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
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0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
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0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
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0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
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0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
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>;
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@ -331,7 +331,7 @@
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&usb {
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status = "okay";
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control@44e10000 {
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control@44e10620 {
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status = "okay";
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};
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@ -352,7 +352,7 @@
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dr_mode = "host";
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};
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dma-controller@07402000 {
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dma-controller@47402000 {
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status = "okay";
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};
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};
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@ -364,7 +364,7 @@
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&usb {
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status = "okay";
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control@44e10000 {
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control@44e10620 {
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status = "okay";
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};
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@ -385,7 +385,7 @@
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dr_mode = "host";
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};
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dma-controller@07402000 {
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dma-controller@47402000 {
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status = "okay";
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};
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};
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@ -118,7 +118,6 @@
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reg = <0 0 0>; /* CS0, offset 0 */
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nand-bus-width = <8>;
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ti,nand-ecc-opt = "bch8";
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gpmc,device-nand = "true";
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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@ -202,7 +201,7 @@
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&usb {
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status = "okay";
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control@44e10000 {
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control@44e10620 {
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status = "okay";
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};
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@ -223,7 +222,7 @@
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dr_mode = "host";
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};
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dma-controller@07402000 {
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dma-controller@47402000 {
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status = "okay";
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};
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};
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@ -72,7 +72,7 @@
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};
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/*
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* The soc node represents the soc top level view. It is uses for IPs
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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@ -94,8 +94,8 @@
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/*
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* XXX: Use a flat representation of the AM33XX interconnect.
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* The real AM33XX interconnect network is quite complex.Since
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* that will not bring real advantage to represent that in DT
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* The real AM33XX interconnect network is quite complex. Since
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* it will not bring real advantage to represent that in DT
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* for the moment, just use a fake OCP bus entry to represent
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* the whole bus hierarchy.
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*/
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@ -230,6 +230,7 @@
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x72004 0x4>;
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clocks = <&gateclk 4>;
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};
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eth1: ethernet@74000 {
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@ -336,6 +336,7 @@
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x72004 0x4>;
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clocks = <&gateclk 4>;
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};
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coredivclk: clock@e4250 {
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@ -80,7 +80,7 @@
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};
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/*
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* The soc node represents the soc top level view. It is uses for IPs
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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/*
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* XXX: Use a flat representation of the SOC interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since that will not bring real advantage to represent that in DT for
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* Since it will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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@ -1640,7 +1640,7 @@
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
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ti,bit-shift = <28>;
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ti,bit-shift = <24>;
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reg = <0x1860>;
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};
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@ -56,6 +56,7 @@
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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@ -29,6 +29,7 @@
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osc26m {
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compatible = "fsl,imx-osc26m", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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};
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@ -48,6 +48,7 @@
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osc26m {
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compatible = "fsl,imx-osc26m", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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@ -53,21 +53,25 @@
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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compatible = "denx,imx53-m53evk", "fsl,imx53";
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memory {
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reg = <0x70000000 0x20000000>;
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reg = <0x70000000 0x20000000>,
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<0xb0000000 0x20000000>;
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};
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soc {
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irq-trigger = <0x1>;
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stmpe_touchscreen {
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compatible = "stmpe,ts";
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compatible = "st,stmpe-ts";
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reg = <0>;
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ts,sample-time = <4>;
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ts,mod-12b = <1>;
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ts,ref-sel = <0>;
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ts,adc-freq = <1>;
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ts,ave-ctrl = <3>;
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ts,touch-det-delay = <3>;
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ts,settling = <4>;
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ts,fraction-z = <7>;
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ts,i-drive = <1>;
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st,sample-time = <4>;
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st,mod-12b = <1>;
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st,ref-sel = <0>;
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st,adc-freq = <1>;
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st,ave-ctrl = <3>;
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st,touch-det-delay = <3>;
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st,settling = <4>;
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st,fraction-z = <7>;
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st,i-drive = <1>;
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};
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};
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/ {
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memory {
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reg = <0x70000000 0x40000000>;
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reg = <0x70000000 0x20000000>,
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<0xb0000000 0x20000000>;
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};
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display0: display@di0 {
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@ -25,12 +25,17 @@
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soc {
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display: display@di0 {
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compatible = "fsl,imx-parallel-display";
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crtcs = <&ipu 0>;
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interface-pix-fmt = "rgb24";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgb24_vga1>;
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status = "okay";
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port {
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display0_in: endpoint {
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remote-endpoint = <&ipu_di0_disp0>;
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};
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};
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display-timings {
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VGA {
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clock-frequency = <25200000>;
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@ -293,6 +298,10 @@
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};
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};
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&ipu_di0_disp0 {
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remote-endpoint = <&display0_in>;
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};
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&kpp {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_kpp>;
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@ -70,21 +70,25 @@
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ckil {
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compatible = "fsl,imx-ckil", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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ckih1 {
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compatible = "fsl,imx-ckih1", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <22579200>;
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};
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ckih2 {
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compatible = "fsl,imx-ckih2", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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osc {
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compatible = "fsl,imx-osc", "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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};
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@ -430,7 +434,7 @@
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port {
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lvds1_in: endpoint {
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remote-endpoint = <&ipu_di0_lvds0>;
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remote-endpoint = <&ipu_di1_lvds1>;
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};
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};
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};
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@ -19,7 +19,10 @@
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compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
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aliases {
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gpio7 = &stmpe_gpio;
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gpio7 = &stmpe_gpio1;
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gpio8 = &stmpe_gpio2;
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stmpe-i2c0 = &stmpe1;
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stmpe-i2c1 = &stmpe2;
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};
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memory {
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@ -40,13 +43,15 @@
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regulator-always-on;
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};
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reg_usb_otg_vbus: regulator@1 {
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reg_usb_otg_switch: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_otg_vbus";
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regulator-name = "usb_otg_switch";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio7 12 0>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_usb_host1: regulator@2 {
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@ -65,23 +70,23 @@
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led-blue {
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label = "blue";
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gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
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gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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led-green {
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label = "green";
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gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
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gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
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};
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led-pink {
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label = "pink";
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gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
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gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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led-red {
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label = "red";
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gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
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gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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@ -99,7 +104,8 @@
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2
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&pinctrl_stmpe>;
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&pinctrl_stmpe1
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&pinctrl_stmpe2>;
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status = "okay";
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pmic: pfuze100@08 {
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@ -205,13 +211,25 @@
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};
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};
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stmpe: stmpe1601@40 {
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stmpe1: stmpe1601@40 {
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compatible = "st,stmpe1601";
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reg = <0x40>;
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interrupts = <30 0>;
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interrupt-parent = <&gpio3>;
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stmpe_gpio: stmpe_gpio {
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stmpe_gpio1: stmpe_gpio {
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#gpio-cells = <2>;
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compatible = "st,stmpe-gpio";
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};
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};
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stmpe2: stmpe1601@44 {
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compatible = "st,stmpe1601";
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reg = <0x44>;
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interrupts = <2 0>;
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interrupt-parent = <&gpio5>;
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stmpe_gpio2: stmpe_gpio {
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#gpio-cells = <2>;
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compatible = "st,stmpe-gpio";
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};
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@ -273,10 +291,14 @@
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>;
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};
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pinctrl_stmpe: stmpegrp {
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pinctrl_stmpe1: stmpe1grp {
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fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
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};
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pinctrl_stmpe2: stmpe2grp {
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fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
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};
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pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
|
@ -293,7 +315,7 @@
|
|||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -344,11 +366,11 @@
|
|||
&usbh1 {
|
||||
vbus-supply = <®_usb_host1>;
|
||||
disable-over-current;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
|
|
|
@ -487,9 +487,6 @@
|
|||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
lvds-channel@0 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
|
|
|
@ -436,9 +436,6 @@
|
|||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
lvds-channel@0 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
|
|
|
@ -26,25 +26,25 @@
|
|||
/* GPIO16 -> AR8035 25MHz */
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
||||
/* AR8035 pin strapping: IO voltage: pull up */
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
|
||||
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
|
||||
/* AR8035 pin strapping: MODE#1: pull up */
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
/* AR8035 pin strapping: MODE#3: pull up */
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
/* AR8035 pin strapping: MODE#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
|
||||
|
||||
/*
|
||||
* As the RMII pins are also connected to RGMII
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -46,8 +48,6 @@
|
|||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
|
@ -59,16 +59,19 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
@ -138,6 +141,12 @@
|
|||
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
||||
num-lanes = <1>;
|
||||
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
|
||||
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||
status = "disabled";
|
||||
|
|
|
@ -282,6 +282,7 @@
|
|||
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
|
||||
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
|
||||
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
|
||||
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
@ -68,8 +68,6 @@
|
|||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
|
@ -81,11 +79,13 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -75,7 +75,7 @@
|
|||
m25p16@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p16";
|
||||
compatible = "st,m25p16";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l4005a";
|
||||
compatible = "mxicy,mx25l4005a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
m25p40@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l1606e";
|
||||
compatible = "mxicy,mx25l1606e";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -48,7 +48,7 @@
|
|||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at,24c04";
|
||||
compatible = "atmel,24c04";
|
||||
pagesize = <16>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
|
|
@ -56,7 +56,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l12805d";
|
||||
compatible = "mxicy,mx25l12805d";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -32,7 +32,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l4005a";
|
||||
compatible = "mxicy,mx25l4005a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
mode = <0>;
|
||||
|
@ -50,7 +50,7 @@
|
|||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at,24c04";
|
||||
compatible = "atmel,24c04";
|
||||
pagesize = <16>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
|
|
@ -104,7 +104,7 @@
|
|||
status = "okay";
|
||||
|
||||
adt7476: adt7476a@2e {
|
||||
compatible = "adt7476";
|
||||
compatible = "adi,adt7476";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -94,7 +94,7 @@
|
|||
status = "okay";
|
||||
|
||||
lm85: lm85@2e {
|
||||
compatible = "lm85";
|
||||
compatible = "national,lm85";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -40,7 +40,7 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "s35390a";
|
||||
compatible = "sii,s35390a";
|
||||
reg = <0x30>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -52,7 +52,7 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
s24c02: s24c02@50 {
|
||||
compatible = "24c02";
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-beagle-xm.dts"
|
||||
|
||||
/ {
|
||||
/* HS USB Port 2 Power enable was inverted with the xM C */
|
||||
hsusb2_power: hsusb2_power_reg {
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
|
@ -112,7 +112,6 @@
|
|||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <16>;
|
||||
|
||||
gpmc,device-nand;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
|
|
|
@ -368,7 +368,6 @@
|
|||
/* no elm on omap3 */
|
||||
|
||||
gpmc,mux-add-data = <0>;
|
||||
gpmc,device-nand;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
|
|
|
@ -74,7 +74,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
|
|
@ -72,7 +72,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
|
@ -96,7 +96,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
|
@ -107,7 +107,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
@ -813,6 +813,12 @@
|
|||
<0x4a084c00 0x40>;
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
ctrl-module = <&omap_control_usb3phy>;
|
||||
clocks = <&usb_phy_cm_clk32k>,
|
||||
<&sys_clkin>,
|
||||
<&usb_otg_ss_refclk960m>;
|
||||
clock-names = "wkupclk",
|
||||
"sysclk",
|
||||
"refclk";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
gic: interrupt-controller@c2800000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xc2800000 0x1000>,
|
||||
<0xc2000000 0x1000>;
|
||||
|
|
|
@ -141,12 +141,12 @@
|
|||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
};
|
||||
|
||||
|
|
|
@ -230,17 +230,17 @@
|
|||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,function = "sdhi1";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
};
|
||||
|
||||
|
|
|
@ -149,7 +149,7 @@
|
|||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
|
@ -164,7 +164,7 @@
|
|||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
|
@ -179,7 +179,7 @@
|
|||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
|
@ -187,7 +187,7 @@
|
|||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
gic: interrupt-controller@f0001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xf0001000 0x1000>,
|
||||
<0xf0000100 0x100>;
|
||||
|
|
|
@ -233,19 +233,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006400 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006400 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
|
||||
resets = <&tegra_car 66>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm@0,7000a000 {
|
||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||
|
|
|
@ -25,11 +25,13 @@
|
|||
clocks {
|
||||
audio_ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
enet_ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -45,11 +45,13 @@
|
|||
|
||||
sxosc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
fxosc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
@ -72,8 +74,6 @@
|
|||
intc: interrupt-controller@40002000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x40003000 0x1000>,
|
||||
<0x40002100 0x100>;
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&clkc 3>;
|
||||
clock-latency = <1000>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
666667 1000000
|
||||
|
@ -54,6 +55,28 @@
|
|||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
i2c0: zynq-i2c@e0004000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 38>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 25 4>;
|
||||
reg = <0xe0004000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: zynq-i2c@e0005000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 39>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0xe0005000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@f8f01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
@ -34,6 +34,82 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2cswitch@74 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
si570: clock-generator@5d {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x5d>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
eeprom@54 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
hwmon@52 {
|
||||
compatible = "ti,ucd9248";
|
||||
reg = <52>;
|
||||
};
|
||||
hwmon@53 {
|
||||
compatible = "ti,ucd9248";
|
||||
reg = <53>;
|
||||
};
|
||||
hwmon@54 {
|
||||
compatible = "ti,ucd9248";
|
||||
reg = <54>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -35,6 +35,74 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2cswitch@74 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
si570: clock-generator@5d {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x5d>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
eeprom@54 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
ucd90120@65 {
|
||||
compatible = "ti,ucd90120";
|
||||
reg = <0x65>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
Loading…
Reference in New Issue