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dts: update to v3.15-rc3 

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2014-05-05 10:03:29 +02:00
parent 41ae766fb9
commit 6bef4dd595
53 changed files with 339 additions and 112 deletions
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6
dts/include/dt-bindings/clock/tegra124-car.h
View File

@ -29,7 +29,7 @@
/* 10 (register bit affects spdif_in and spdif_out) */ /* 10 (register bit affects spdif_in and spdif_out) */
#define TEGRA124_CLK_I2S1 11 #define TEGRA124_CLK_I2S1 11
#define TEGRA124_CLK_I2C1 12 #define TEGRA124_CLK_I2C1 12
#define TEGRA124_CLK_NDFLASH 13 /* 13 */
#define TEGRA124_CLK_SDMMC1 14 #define TEGRA124_CLK_SDMMC1 14
#define TEGRA124_CLK_SDMMC4 15 #define TEGRA124_CLK_SDMMC4 15
/* 16 */ /* 16 */
@ -83,7 +83,7 @@
/* 64 */ /* 64 */
#define TEGRA124_CLK_UARTD 65 #define TEGRA124_CLK_UARTD 65
#define TEGRA124_CLK_UARTE 66 /* 66 */
#define TEGRA124_CLK_I2C3 67 #define TEGRA124_CLK_I2C3 67
#define TEGRA124_CLK_SBC4 68 #define TEGRA124_CLK_SBC4 68
#define TEGRA124_CLK_SDMMC3 69 #define TEGRA124_CLK_SDMMC3 69
@ -97,7 +97,7 @@
#define TEGRA124_CLK_TRACE 77 #define TEGRA124_CLK_TRACE 77
#define TEGRA124_CLK_SOC_THERM 78 #define TEGRA124_CLK_SOC_THERM 78
#define TEGRA124_CLK_DTV 79 #define TEGRA124_CLK_DTV 79
#define TEGRA124_CLK_NDSPEED 80 /* 80 */
#define TEGRA124_CLK_I2CSLOW 81 #define TEGRA124_CLK_I2CSLOW 81
#define TEGRA124_CLK_DSIB 82 #define TEGRA124_CLK_DSIB 82
#define TEGRA124_CLK_TSEC 83 #define TEGRA124_CLK_TSEC 83

4
dts/src/arm/am335x-bone-common.dtsi
View File

@ -183,7 +183,7 @@
&usb { &usb {
status = "okay"; status = "okay";
control@44e10000 { control@44e10620 {
status = "okay"; status = "okay";
}; };
@ -204,7 +204,7 @@
dr_mode = "host"; dr_mode = "host";
}; };
dma-controller@07402000 { dma-controller@47402000 {
status = "okay"; status = "okay";
}; };
}; };

8
dts/src/arm/am335x-evm.dts
View File

@ -301,8 +301,8 @@
am335x_evm_audio_pins: am335x_evm_audio_pins { am335x_evm_audio_pins: am335x_evm_audio_pins {
pinctrl-single,pins = < pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
>; >;
@ -331,7 +331,7 @@
&usb { &usb {
status = "okay"; status = "okay";
control@44e10000 { control@44e10620 {
status = "okay"; status = "okay";
}; };
@ -352,7 +352,7 @@
dr_mode = "host"; dr_mode = "host";
}; };
dma-controller@07402000 { dma-controller@47402000 {
status = "okay"; status = "okay";
}; };
}; };

4
dts/src/arm/am335x-evmsk.dts
View File

@ -364,7 +364,7 @@
&usb { &usb {
status = "okay"; status = "okay";
control@44e10000 { control@44e10620 {
status = "okay"; status = "okay";
}; };
@ -385,7 +385,7 @@
dr_mode = "host"; dr_mode = "host";
}; };
dma-controller@07402000 { dma-controller@47402000 {
status = "okay"; status = "okay";
}; };
}; };

5
dts/src/arm/am335x-igep0033.dtsi
View File

@ -118,7 +118,6 @@
reg = <0 0 0>; /* CS0, offset 0 */ reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <8>; nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8"; ti,nand-ecc-opt = "bch8";
gpmc,device-nand = "true";
gpmc,device-width = <1>; gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>; gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <0>;
@ -202,7 +201,7 @@
&usb { &usb {
status = "okay"; status = "okay";
control@44e10000 { control@44e10620 {
status = "okay"; status = "okay";
}; };
@ -223,7 +222,7 @@
dr_mode = "host"; dr_mode = "host";
}; };
dma-controller@07402000 { dma-controller@47402000 {
status = "okay"; status = "okay";
}; };
}; };

6
dts/src/arm/am33xx.dtsi
View File

@ -72,7 +72,7 @@
}; };
/* /*
* The soc node represents the soc top level view. It is uses for IPs * The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself. * that are not memory mapped in the MPU view or for the MPU itself.
*/ */
soc { soc {
@ -94,8 +94,8 @@
/* /*
* XXX: Use a flat representation of the AM33XX interconnect. * XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex.Since * The real AM33XX interconnect network is quite complex. Since
* that will not bring real advantage to represent that in DT * it will not bring real advantage to represent that in DT
* for the moment, just use a fake OCP bus entry to represent * for the moment, just use a fake OCP bus entry to represent
* the whole bus hierarchy. * the whole bus hierarchy.
*/ */

1
dts/src/arm/armada-370-xp.dtsi
View File

@ -230,6 +230,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "marvell,orion-mdio"; compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>; reg = <0x72004 0x4>;
clocks = <&gateclk 4>;
}; };
eth1: ethernet@74000 { eth1: ethernet@74000 {

1
dts/src/arm/armada-38x.dtsi
View File

@ -336,6 +336,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "marvell,orion-mdio"; compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>; reg = <0x72004 0x4>;
clocks = <&gateclk 4>;
}; };
coredivclk: clock@e4250 { coredivclk: clock@e4250 {

4
dts/src/arm/dra7.dtsi
View File

@ -80,7 +80,7 @@
}; };
/* /*
* The soc node represents the soc top level view. It is uses for IPs * The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself. * that are not memory mapped in the MPU view or for the MPU itself.
*/ */
soc { soc {
@ -94,7 +94,7 @@
/* /*
* XXX: Use a flat representation of the SOC interconnect. * XXX: Use a flat representation of the SOC interconnect.
* The real OMAP interconnect network is quite complex. * The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for * Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus * the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy. * hierarchy.
*/ */

2
dts/src/arm/dra7xx-clocks.dtsi
View File

@ -1640,7 +1640,7 @@
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,mux-clock"; compatible = "ti,mux-clock";
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <28>; ti,bit-shift = <24>;
reg = <0x1860>; reg = <0x1860>;
}; };

1
dts/src/arm/imx25.dtsi
View File

@ -56,6 +56,7 @@
osc { osc {
compatible = "fsl,imx-osc", "fixed-clock"; compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };

1
dts/src/arm/imx27-apf27.dts
View File

@ -29,6 +29,7 @@
osc26m { osc26m {
compatible = "fsl,imx-osc26m", "fixed-clock"; compatible = "fsl,imx-osc26m", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
}; };

1
dts/src/arm/imx27.dtsi
View File

@ -48,6 +48,7 @@
osc26m { osc26m {
compatible = "fsl,imx-osc26m", "fixed-clock"; compatible = "fsl,imx-osc26m", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>; clock-frequency = <26000000>;
}; };
}; };

4
dts/src/arm/imx50.dtsi
View File

@ -53,21 +53,25 @@
ckil { ckil {
compatible = "fsl,imx-ckil", "fixed-clock"; compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
ckih1 { ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock"; compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>; clock-frequency = <22579200>;
}; };
ckih2 { ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock"; compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
osc { osc {
compatible = "fsl,imx-osc", "fixed-clock"; compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };

4
dts/src/arm/imx51.dtsi
View File

@ -50,21 +50,25 @@
ckil { ckil {
compatible = "fsl,imx-ckil", "fixed-clock"; compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
ckih1 { ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock"; compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
ckih2 { ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock"; compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
osc { osc {
compatible = "fsl,imx-osc", "fixed-clock"; compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };

23
dts/src/arm/imx53-m53evk.dts
View File

@ -17,7 +17,8 @@
compatible = "denx,imx53-m53evk", "fsl,imx53"; compatible = "denx,imx53-m53evk", "fsl,imx53";
memory { memory {
reg = <0x70000000 0x20000000>; reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
}; };
soc { soc {
@ -193,17 +194,17 @@
irq-trigger = <0x1>; irq-trigger = <0x1>;
stmpe_touchscreen { stmpe_touchscreen {
compatible = "stmpe,ts"; compatible = "st,stmpe-ts";
reg = <0>; reg = <0>;
ts,sample-time = <4>; st,sample-time = <4>;
ts,mod-12b = <1>; st,mod-12b = <1>;
ts,ref-sel = <0>; st,ref-sel = <0>;
ts,adc-freq = <1>; st,adc-freq = <1>;
ts,ave-ctrl = <3>; st,ave-ctrl = <3>;
ts,touch-det-delay = <3>; st,touch-det-delay = <3>;
ts,settling = <4>; st,settling = <4>;
ts,fraction-z = <7>; st,fraction-z = <7>;
ts,i-drive = <1>; st,i-drive = <1>;
}; };
}; };

3
dts/src/arm/imx53-qsb-common.dtsi
View File

@ -14,7 +14,8 @@
/ { / {
memory { memory {
reg = <0x70000000 0x40000000>; reg = <0x70000000 0x20000000>,
<0xb0000000 0x20000000>;
}; };
display0: display@di0 { display0: display@di0 {

11
dts/src/arm/imx53-tx53-x03x.dts
View File

@ -25,12 +25,17 @@
soc { soc {
display: display@di0 { display: display@di0 {
compatible = "fsl,imx-parallel-display"; compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24"; interface-pix-fmt = "rgb24";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgb24_vga1>; pinctrl-0 = <&pinctrl_rgb24_vga1>;
status = "okay"; status = "okay";
port {
display0_in: endpoint {
remote-endpoint = <&ipu_di0_disp0>;
};
};
display-timings { display-timings {
VGA { VGA {
clock-frequency = <25200000>; clock-frequency = <25200000>;
@ -293,6 +298,10 @@
}; };
}; };
&ipu_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&kpp { &kpp {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_kpp>; pinctrl-0 = <&pinctrl_kpp>;

6
dts/src/arm/imx53.dtsi
View File

@ -70,21 +70,25 @@
ckil { ckil {
compatible = "fsl,imx-ckil", "fixed-clock"; compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
ckih1 { ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock"; compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <22579200>; clock-frequency = <22579200>;
}; };
ckih2 { ckih2 {
compatible = "fsl,imx-ckih2", "fixed-clock"; compatible = "fsl,imx-ckih2", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
osc { osc {
compatible = "fsl,imx-osc", "fixed-clock"; compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };
@ -430,7 +434,7 @@
port { port {
lvds1_in: endpoint { lvds1_in: endpoint {
remote-endpoint = <&ipu_di0_lvds0>; remote-endpoint = <&ipu_di1_lvds1>;
}; };
}; };
}; };

48
dts/src/arm/imx6q-dmo-edmqmx6.dts
View File

@ -19,7 +19,10 @@
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q"; compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
aliases { aliases {
gpio7 = &stmpe_gpio; gpio7 = &stmpe_gpio1;
gpio8 = &stmpe_gpio2;
stmpe-i2c0 = &stmpe1;
stmpe-i2c1 = &stmpe2;
}; };
memory { memory {
@ -40,13 +43,15 @@
regulator-always-on; regulator-always-on;
}; };
reg_usb_otg_vbus: regulator@1 { reg_usb_otg_switch: regulator@1 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
reg = <1>; reg = <1>;
regulator-name = "usb_otg_vbus"; regulator-name = "usb_otg_switch";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio7 12 0>; gpio = <&gpio7 12 0>;
regulator-boot-on;
regulator-always-on;
}; };
reg_usb_host1: regulator@2 { reg_usb_host1: regulator@2 {
@ -65,23 +70,23 @@
led-blue { led-blue {
label = "blue"; label = "blue";
gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>; gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat"; linux,default-trigger = "heartbeat";
}; };
led-green { led-green {
label = "green"; label = "green";
gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>; gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
}; };
led-pink { led-pink {
label = "pink"; label = "pink";
gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>; gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
}; };
led-red { led-red {
label = "red"; label = "red";
gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>; gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
}; };
}; };
}; };
@ -99,7 +104,8 @@
clock-frequency = <100000>; clock-frequency = <100000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2 pinctrl-0 = <&pinctrl_i2c2
&pinctrl_stmpe>; &pinctrl_stmpe1
&pinctrl_stmpe2>;
status = "okay"; status = "okay";
pmic: pfuze100@08 { pmic: pfuze100@08 {
@ -205,13 +211,25 @@
}; };
}; };
stmpe: stmpe1601@40 { stmpe1: stmpe1601@40 {
compatible = "st,stmpe1601"; compatible = "st,stmpe1601";
reg = <0x40>; reg = <0x40>;
interrupts = <30 0>; interrupts = <30 0>;
interrupt-parent = <&gpio3>; interrupt-parent = <&gpio3>;
stmpe_gpio: stmpe_gpio { stmpe_gpio1: stmpe_gpio {
#gpio-cells = <2>;
compatible = "st,stmpe-gpio";
};
};
stmpe2: stmpe1601@44 {
compatible = "st,stmpe1601";
reg = <0x44>;
interrupts = <2 0>;
interrupt-parent = <&gpio5>;
stmpe_gpio2: stmpe_gpio {
#gpio-cells = <2>; #gpio-cells = <2>;
compatible = "st,stmpe-gpio"; compatible = "st,stmpe-gpio";
}; };
@ -273,10 +291,14 @@
>; >;
}; };
pinctrl_stmpe: stmpegrp { pinctrl_stmpe1: stmpe1grp {
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>; fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
}; };
pinctrl_stmpe2: stmpe2grp {
fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
};
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
@ -293,7 +315,7 @@
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>; >;
}; };
@ -344,11 +366,11 @@
&usbh1 { &usbh1 {
vbus-supply = <&reg_usb_host1>; vbus-supply = <&reg_usb_host1>;
disable-over-current; disable-over-current;
dr_mode = "host";
status = "okay"; status = "okay";
}; };
&usbotg { &usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>; pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current; disable-over-current;

3
dts/src/arm/imx6q-gw5400-a.dts
View File

@ -487,9 +487,6 @@
&ldb { &ldb {
status = "okay"; status = "okay";
lvds-channel@0 {
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
};
}; };
&pcie { &pcie {

3
dts/src/arm/imx6qdl-gw52xx.dtsi
View File

@ -436,9 +436,6 @@
&ldb { &ldb {
status = "okay"; status = "okay";
lvds-channel@0 {
crtcs = <&ipu1 0>, <&ipu1 1>;
};
}; };
&pcie { &pcie {

22
dts/src/arm/imx6qdl-microsom-ar8035.dtsi
View File

@ -26,25 +26,25 @@
/* GPIO16 -> AR8035 25MHz */ /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
/* AR8035 pin strapping: IO voltage: pull up */ /* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
/* AR8035 pin strapping: PHYADDR#0: pull down */ /* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
/* AR8035 pin strapping: PHYADDR#1: pull down */ /* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
/* AR8035 pin strapping: MODE#1: pull up */ /* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
/* AR8035 pin strapping: MODE#3: pull up */ /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
/* AR8035 pin strapping: MODE#0: pull down */ /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
/* /*
* As the RMII pins are also connected to RGMII * As the RMII pins are also connected to RGMII

13
dts/src/arm/imx6qdl.dtsi
View File

@ -10,6 +10,8 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi" #include "skeleton.dtsi"
/ { / {
@ -46,8 +48,6 @@
intc: interrupt-controller@00a01000 { intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller; interrupt-controller;
reg = <0x00a01000 0x1000>, reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>; <0x00a00100 0x100>;
@ -59,16 +59,19 @@
ckil { ckil {
compatible = "fsl,imx-ckil", "fixed-clock"; compatible = "fsl,imx-ckil", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
ckih1 { ckih1 {
compatible = "fsl,imx-ckih1", "fixed-clock"; compatible = "fsl,imx-ckih1", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>; clock-frequency = <0>;
}; };
osc { osc {
compatible = "fsl,imx-osc", "fixed-clock"; compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };
@ -138,6 +141,12 @@
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>; num-lanes = <1>;
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
status = "disabled"; status = "disabled";

1
dts/src/arm/imx6sl-evk.dts
View File

@ -282,6 +282,7 @@
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
>; >;
}; };

4
dts/src/arm/imx6sl.dtsi
View File

@ -68,8 +68,6 @@
intc: interrupt-controller@00a01000 { intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller; interrupt-controller;
reg = <0x00a01000 0x1000>, reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>; <0x00a00100 0x100>;
@ -81,11 +79,13 @@
ckil { ckil {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
osc { osc {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };

2
dts/src/arm/kirkwood-b3.dts
View File

@ -75,7 +75,7 @@
m25p16@0 { m25p16@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "m25p16"; compatible = "st,m25p16";
reg = <0>; reg = <0>;
spi-max-frequency = <40000000>; spi-max-frequency = <40000000>;
mode = <0>; mode = <0>;

2
dts/src/arm/kirkwood-cloudbox.dts
View File

@ -46,7 +46,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "mx25l4005a"; compatible = "mxicy,mx25l4005a";
reg = <0>; reg = <0>;
spi-max-frequency = <20000000>; spi-max-frequency = <20000000>;
mode = <0>; mode = <0>;

2
dts/src/arm/kirkwood-dreamplug.dts
View File

@ -43,7 +43,7 @@
m25p40@0 { m25p40@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "mx25l1606e"; compatible = "mxicy,mx25l1606e";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
mode = <0>; mode = <0>;

2
dts/src/arm/kirkwood-laplug.dts
View File

@ -48,7 +48,7 @@
status = "okay"; status = "okay";
eeprom@50 { eeprom@50 {
compatible = "at,24c04"; compatible = "atmel,24c04";
pagesize = <16>; pagesize = <16>;
reg = <0x50>; reg = <0x50>;
}; };

2
dts/src/arm/kirkwood-mv88f6281gtw-ge.dts
View File

@ -56,7 +56,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "mx25l12805d"; compatible = "mxicy,mx25l12805d";
reg = <0>; reg = <0>;
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
mode = <0>; mode = <0>;

4
dts/src/arm/kirkwood-ns2-common.dtsi
View File

@ -32,7 +32,7 @@
flash@0 { flash@0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "mx25l4005a"; compatible = "mxicy,mx25l4005a";
reg = <0>; reg = <0>;
spi-max-frequency = <20000000>; spi-max-frequency = <20000000>;
mode = <0>; mode = <0>;
@ -50,7 +50,7 @@
status = "okay"; status = "okay";
eeprom@50 { eeprom@50 {
compatible = "at,24c04"; compatible = "atmel,24c04";
pagesize = <16>; pagesize = <16>;
reg = <0x50>; reg = <0x50>;
}; };

2
dts/src/arm/kirkwood-nsa310.dts
View File

@ -104,7 +104,7 @@
status = "okay"; status = "okay";
adt7476: adt7476a@2e { adt7476: adt7476a@2e {
compatible = "adt7476"; compatible = "adi,adt7476";
reg = <0x2e>; reg = <0x2e>;
}; };
}; };

2
dts/src/arm/kirkwood-nsa310a.dts
View File

@ -94,7 +94,7 @@
status = "okay"; status = "okay";
lm85: lm85@2e { lm85: lm85@2e {
compatible = "lm85"; compatible = "national,lm85";
reg = <0x2e>; reg = <0x2e>;
}; };
}; };

2
dts/src/arm/kirkwood-openblocks_a6.dts
View File

@ -40,7 +40,7 @@
pinctrl-names = "default"; pinctrl-names = "default";
s35390a: s35390a@30 { s35390a: s35390a@30 {
compatible = "s35390a"; compatible = "sii,s35390a";
reg = <0x30>; reg = <0x30>;
}; };
}; };

2
dts/src/arm/kirkwood-openblocks_a7.dts
View File

@ -52,7 +52,7 @@
pinctrl-names = "default"; pinctrl-names = "default";
s24c02: s24c02@50 { s24c02: s24c02@50 {
compatible = "24c02"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
}; };
}; };

16
dts/src/arm/omap3-beagle-xm-ab.dts Normal file
View File

@ -0,0 +1,16 @@
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "omap3-beagle-xm.dts"
/ {
/* HS USB Port 2 Power enable was inverted with the xM C */
hsusb2_power: hsusb2_power_reg {
enable-active-high;
};
};

1
dts/src/arm/omap3-devkit8000.dts
View File

@ -112,7 +112,6 @@
reg = <0 0 0>; /* CS0, offset 0 */ reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <16>; nand-bus-width = <16>;
gpmc,device-nand;
gpmc,sync-clk-ps = <0>; gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>; gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>; gpmc,cs-rd-off-ns = <44>;

1
dts/src/arm/omap3-lilly-a83x.dtsi
View File

@ -368,7 +368,6 @@
/* no elm on omap3 */ /* no elm on omap3 */
gpmc,mux-add-data = <0>; gpmc,mux-add-data = <0>;
gpmc,device-nand;
gpmc,device-width = <2>; gpmc,device-width = <2>;
gpmc,wait-pin = <0>; gpmc,wait-pin = <0>;
gpmc,wait-monitoring-ns = <0>; gpmc,wait-monitoring-ns = <0>;

2
dts/src/arm/omap3.dtsi
View File

@ -74,7 +74,7 @@
/* /*
* XXX: Use a flat representation of the OMAP3 interconnect. * XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex. * The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for * Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus * the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy. * hierarchy.
*/ */

4
dts/src/arm/omap4.dtsi
View File

@ -72,7 +72,7 @@
}; };
/* /*
* The soc node represents the soc top level view. It is uses for IPs * The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself. * that are not memory mapped in the MPU view or for the MPU itself.
*/ */
soc { soc {
@ -96,7 +96,7 @@
/* /*
* XXX: Use a flat representation of the OMAP4 interconnect. * XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex. * The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for * Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus * the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy. * hierarchy.
*/ */

10
dts/src/arm/omap5.dtsi
View File

@ -93,7 +93,7 @@
}; };
/* /*
* The soc node represents the soc top level view. It is uses for IPs * The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself. * that are not memory mapped in the MPU view or for the MPU itself.
*/ */
soc { soc {
@ -107,7 +107,7 @@
/* /*
* XXX: Use a flat representation of the OMAP3 interconnect. * XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex. * The real OMAP interconnect network is quite complex.
* Since that will not bring real advantage to represent that in DT for * Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus * the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy. * hierarchy.
*/ */
@ -813,6 +813,12 @@
<0x4a084c00 0x40>; <0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl"; reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_usb3phy>; ctrl-module = <&omap_control_usb3phy>;
clocks = <&usb_phy_cm_clk32k>,
<&sys_clkin>,
<&usb_otg_ss_refclk960m>;
clock-names = "wkupclk",
"sysclk",
"refclk";
#phy-cells = <0>; #phy-cells = <0>;
}; };
}; };

1
dts/src/arm/r8a7740.dtsi
View File

@ -28,7 +28,6 @@
gic: interrupt-controller@c2800000 { gic: interrupt-controller@c2800000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller; interrupt-controller;
reg = <0xc2800000 0x1000>, reg = <0xc2800000 0x1000>,
<0xc2000000 0x1000>; <0xc2000000 0x1000>;

4
dts/src/arm/r8a7790-lager.dts
View File

@ -141,12 +141,12 @@
}; };
sdhi0_pins: sd0 { sdhi0_pins: sd0 {
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl"; renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0"; renesas,function = "sdhi0";
}; };
sdhi2_pins: sd2 { sdhi2_pins: sd2 {
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl"; renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2"; renesas,function = "sdhi2";
}; };

6
dts/src/arm/r8a7791-koelsch.dts
View File

@ -230,17 +230,17 @@
}; };
sdhi0_pins: sd0 { sdhi0_pins: sd0 {
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl"; renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0"; renesas,function = "sdhi0";
}; };
sdhi1_pins: sd1 { sdhi1_pins: sd1 {
renesas,gpios = "sdhi1_data4", "sdhi1_ctrl"; renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1"; renesas,function = "sdhi1";
}; };
sdhi2_pins: sd2 { sdhi2_pins: sd2 {
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl"; renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2"; renesas,function = "sdhi2";
}; };

8
dts/src/arm/rk3188.dtsi
View File

@ -149,7 +149,7 @@
uart0 { uart0 {
uart0_xfer: uart0-xfer { uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>, rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
}; };
@ -164,7 +164,7 @@
uart1 { uart1 {
uart1_xfer: uart1-xfer { uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>, rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
}; };
@ -179,7 +179,7 @@
uart2 { uart2 {
uart2_xfer: uart2-xfer { uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>, rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
}; };
/* no rts / cts for uart2 */ /* no rts / cts for uart2 */
@ -187,7 +187,7 @@
uart3 { uart3 {
uart3_xfer: uart3-xfer { uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>, rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
}; };

1
dts/src/arm/sh73a0.dtsi
View File

@ -34,7 +34,6 @@
gic: interrupt-controller@f0001000 { gic: interrupt-controller@f0001000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller; interrupt-controller;
reg = <0xf0001000 0x1000>, reg = <0xf0001000 0x1000>,
<0xf0000100 0x100>; <0xf0000100 0x100>;

13
dts/src/arm/tegra124.dtsi
View File

@ -233,19 +233,6 @@
status = "disabled"; status = "disabled";
}; };
serial@0,70006400 {
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
reg = <0x0 0x70006400 0x0 0x40>;
reg-shift = <2>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
resets = <&tegra_car 66>;
reset-names = "serial";
dmas = <&apbdma 20>, <&apbdma 20>;
dma-names = "rx", "tx";
status = "disabled";
};
pwm@0,7000a000 { pwm@0,7000a000 {
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
reg = <0x0 0x7000a000 0x0 0x100>; reg = <0x0 0x7000a000 0x0 0x100>;

2
dts/src/arm/vf610-twr.dts
View File

@ -25,11 +25,13 @@
clocks { clocks {
audio_ext { audio_ext {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>; clock-frequency = <24576000>;
}; };
enet_ext { enet_ext {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>; clock-frequency = <50000000>;
}; };
}; };

4
dts/src/arm/vf610.dtsi
View File

@ -45,11 +45,13 @@
sxosc { sxosc {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>; clock-frequency = <32768>;
}; };
fxosc { fxosc {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>; clock-frequency = <24000000>;
}; };
}; };
@ -72,8 +74,6 @@
intc: interrupt-controller@40002000 { intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller; interrupt-controller;
reg = <0x40003000 0x1000>, reg = <0x40003000 0x1000>,
<0x40002100 0x100>; <0x40002100 0x100>;

23
dts/src/arm/zynq-7000.dtsi
View File

@ -24,6 +24,7 @@
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&clkc 3>; clocks = <&clkc 3>;
clock-latency = <1000>;
operating-points = < operating-points = <
/* kHz uV */ /* kHz uV */
666667 1000000 666667 1000000
@ -54,6 +55,28 @@
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
ranges; ranges;
i2c0: zynq-i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 38>;
interrupt-parent = <&intc>;
interrupts = <0 25 4>;
reg = <0xe0004000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: zynq-i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 39>;
interrupt-parent = <&intc>;
interrupts = <0 48 4>;
reg = <0xe0005000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
intc: interrupt-controller@f8f01000 { intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic"; compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>; #interrupt-cells = <3>;

76
dts/src/arm/zynq-zc702.dts
View File

@ -34,6 +34,82 @@
phy-mode = "rgmii"; phy-mode = "rgmii";
}; };
&i2c0 {
status = "okay";
clock-frequency = <400000>;
i2cswitch@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
si570: clock-generator@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
temperature-stability = <50>;
reg = <0x5d>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@54 {
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
hwmon@52 {
compatible = "ti,ucd9248";
reg = <52>;
};
hwmon@53 {
compatible = "ti,ucd9248";
reg = <53>;
};
hwmon@54 {
compatible = "ti,ucd9248";
reg = <54>;
};
};
};
};
&sdhci0 { &sdhci0 {
status = "okay"; status = "okay";
}; };

68
dts/src/arm/zynq-zc706.dts
View File

@ -35,6 +35,74 @@
phy-mode = "rgmii"; phy-mode = "rgmii";
}; };
&i2c0 {
status = "okay";
clock-frequency = <400000>;
i2cswitch@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
si570: clock-generator@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
temperature-stability = <50>;
reg = <0x5d>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@54 {
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
ucd90120@65 {
compatible = "ti,ucd90120";
reg = <0x65>;
};
};
};
};
&sdhci0 { &sdhci0 {
status = "okay"; status = "okay";
}; };