sysmo-bts
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barebox
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Merge branch 'next'

This commit is contained in:
Sascha Hauer 2010-07-03 10:26:21 +02:00
parent 0db4be97f2 7f5644fad1
commit 6d1d9e8d8b
135 changed files with 5055 additions and 3639 deletions
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1
Documentation/users_manual.dox
View File

@ -11,5 +11,6 @@ work easier.
@li @subpage command_reference
@li @subpage partitions
@li @subpage x86_bootloader
@li @subpage net_netconsole
*/

3
Doxyfile
View File

@ -485,7 +485,8 @@ INPUT = Documentation \
common \
board \
lib \
scripts/setupmbr
scripts/setupmbr \
net
# This tag can be used to specify the character encoding of the source files that
# doxygen parses. Internally doxygen uses the UTF-8 encoding, which is also the default

15
Makefile
View File

@ -1299,18 +1299,3 @@ Makefile: ;
# information in a variable se we can use it in if_changed and friends.
.PHONY: $(PHONY)
#
# sanity checks for check default environemnt
#
ifdef CONFIG_DEFAULT_ENVIRONMENT
ifeq ($(CONFIG_DEFAULT_ENVIRONMENT_PATH),"")
$(error default environment path empty))
endif
saved-env_path := $(CONFIG_DEFAULT_ENVIRONMENT_PATH)
CONFIG_DEFAULT_ENVIRONMENT_PATH := $(shell cd $(if $(filter /%,$(CONFIG_DEFAULT_ENVIRONMENT_PATH)),,$(srctree)/)$(CONFIG_DEFAULT_ENVIRONMENT_PATH) && /bin/pwd)
$(if $(CONFIG_DEFAULT_ENVIRONMENT_PATH),, \
$(error default environment path $(saved-env_path) does not exist))
endif # ifdef CONFIG_DEFAULT_ENVIRONMENT

2
arch/arm/Makefile
View File

@ -52,7 +52,6 @@ board-$(CONFIG_MACH_A9M2410) := a9m2410
board-$(CONFIG_MACH_A9M2440) := a9m2440
board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek
board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek
board-$(CONFIG_MACH_ECO920) := eco920
board-$(CONFIG_MACH_EDB9301) := edb93xx
board-$(CONFIG_MACH_EDB9302) := edb93xx
board-$(CONFIG_MACH_EDB9302A) := edb93xx
@ -63,6 +62,7 @@ board-$(CONFIG_MACH_EDB9315) := edb93xx
board-$(CONFIG_MACH_EDB9315A) := edb93xx
board-$(CONFIG_MACH_EUKREA_CPUIMX25) := eukrea_cpuimx25
board-$(CONFIG_MACH_EUKREA_CPUIMX27) := eukrea_cpuimx27
board-$(CONFIG_MACH_EUKREA_CPUIMX35) := eukrea_cpuimx35
board-$(CONFIG_MACH_FREESCALE_MX25_3STACK) := freescale-mx25-3-stack
board-$(CONFIG_MACH_FREESCALE_MX35_3STACK) := freescale-mx35-3-stack
board-$(CONFIG_MACH_IMX21ADS) := imx21ads

254
arch/arm/configs/eukrea_cpuimx35_defconfig Normal file
View File

@ -0,0 +1,254 @@
#
# Automatically generated make config: don't edit
# barebox version: 2010.06.0
# Mon Jun 7 18:25:47 2010
#
# CONFIG_BOARD_LINKER_SCRIPT is not set
CONFIG_GENERIC_LINKER_SCRIPT=y
CONFIG_ARM=y
#
# System Type
#
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_AT91RM9200 is not set
# CONFIG_ARCH_EP93XX is not set
CONFIG_ARCH_IMX=y
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_S3C24xx is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V6=y
CONFIG_CPU_32v6=y
#
# processor features
#
CONFIG_ARCH_HAS_L2X0=y
CONFIG_CACHE_L2X0=y
CONFIG_ARCH_TEXT_BASE=0x87f00000
CONFIG_BOARDINFO="Eukrea CPUIMX35"
CONFIG_ARCH_HAS_FEC_IMX=y
CONFIG_ARCH_IMX_INTERNAL_BOOT=y
#
# Freescale i.MX System-on-Chip
#
# CONFIG_ARCH_IMX1 is not set
# CONFIG_ARCH_IMX21 is not set
# CONFIG_ARCH_IMX25 is not set
# CONFIG_ARCH_IMX27 is not set
# CONFIG_ARCH_IMX31 is not set
CONFIG_ARCH_IMX35=y
CONFIG_MACH_EUKREA_CPUIMX35=y
# CONFIG_MACH_FREESCALE_MX35_3STACK is not set
# CONFIG_MACH_PCM043 is not set
#
# Board specific settings
#
#
# i.MX specific settings
#
# CONFIG_IMX_CLKO is not set
# CONFIG_AEABI is not set
#
# Arm specific settings
#
CONFIG_CMD_ARM_CPUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_GREGORIAN_CALENDER=y
CONFIG_HAS_KALLSYMS=y
CONFIG_HAS_MODULES=y
CONFIG_CMD_MEMORY=y
CONFIG_ENV_HANDLING=y
CONFIG_GENERIC_GPIO=y
#
# General Settings
#
CONFIG_LOCALVERSION_AUTO=y
#
# memory layout
#
CONFIG_HAVE_MMU=y
CONFIG_MMU=y
CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
CONFIG_TEXT_BASE=0x87f00000
CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
CONFIG_MEMORY_LAYOUT_DEFAULT=y
# CONFIG_MEMORY_LAYOUT_FIXED is not set
CONFIG_STACK_SIZE=0x8000
CONFIG_MALLOC_SIZE=0x800000
# CONFIG_BROKEN is not set
# CONFIG_EXPERIMENTAL is not set
CONFIG_MACH_HAS_LOWLEVEL_INIT=y
CONFIG_MACH_DO_LOWLEVEL_INIT=y
CONFIG_PROMPT="barebox:"
CONFIG_BAUDRATE=115200
CONFIG_LONGHELP=y
CONFIG_CBSIZE=1024
CONFIG_MAXARGS=16
CONFIG_SHELL_HUSH=y
# CONFIG_SHELL_SIMPLE is not set
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="> "
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_ERRNO_MESSAGES=y
CONFIG_TIMESTAMP=y
CONFIG_CONSOLE_FULL=y
CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
# CONFIG_PARTITION is not set
# CONFIG_DEFAULT_ENVIRONMENT is not set
#
# Debugging
#
# CONFIG_DEBUG_INFO is not set
# CONFIG_ENABLE_FLASH_NOISE is not set
# CONFIG_ENABLE_PARTITION_NOISE is not set
# CONFIG_ENABLE_DEVICE_NOISE is not set
#
# Commands
#
#
# scripting
#
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TRUE=y
CONFIG_CMD_FALSE=y
#
# file commands
#
CONFIG_CMD_LS=y
CONFIG_CMD_RM=y
CONFIG_CMD_CAT=y
CONFIG_CMD_MKDIR=y
CONFIG_CMD_RMDIR=y
CONFIG_CMD_CP=y
CONFIG_CMD_PWD=y
CONFIG_CMD_CD=y
CONFIG_CMD_MOUNT=y
CONFIG_CMD_UMOUNT=y
#
# console
#
CONFIG_CMD_CLEAR=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ECHO_E=y
#
# memory
#
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
# CONFIG_CMD_MTEST_ALTERNATIVE is not set
#
# flash
#
# CONFIG_CMD_FLASH is not set
#
# booting
#
CONFIG_CMD_BOOTM=y
# CONFIG_CMD_BOOTM_ZLIB is not set
# CONFIG_CMD_BOOTM_BZLIB is not set
# CONFIG_CMD_BOOTM_SHOW_TYPE is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTU=y
# CONFIG_CMD_LINUX16 is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_TEST=y
CONFIG_CMD_VERSION=y
CONFIG_CMD_HELP=y
CONFIG_CMD_DEVINFO=y
CONFIG_CMD_BMP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
# CONFIG_NET_RARP is not set
# CONFIG_NET_NFS is not set
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
#
# Drivers
#
#
# serial drivers
#
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
#
# Network drivers
#
# CONFIG_DRIVER_NET_SMC911X is not set
# CONFIG_DRIVER_NET_SMC91111 is not set
CONFIG_DRIVER_NET_FEC_IMX=y
#
# SPI drivers
#
# CONFIG_SPI is not set
# CONFIG_I2C is not set
#
# flash drivers
#
# CONFIG_DRIVER_CFI is not set
CONFIG_NAND=y
CONFIG_NAND_IMX=y
# CONFIG_NAND_IMX_BOOT is not set
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_ATA is not set
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX_IPU=y
#
# Filesystem support
#
# CONFIG_FS_CRAMFS is not set
CONFIG_FS_RAMFS=y
CONFIG_FS_DEVFS=y
CONFIG_CRC32=y
CONFIG_CRC16=y
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_PROCESS_ESCAPE_SEQUENCE=y
CONFIG_LZO_DECOMPRESS=y

2
arch/arm/configs/pca100_defconfig
View File

@ -110,7 +110,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="board/phycard-i.MX27/env/"
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/phycard-i.MX27/env"
#
# Debugging

2
arch/arm/configs/pcm037_defconfig
View File

@ -106,7 +106,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="board/pcm037/env"
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/pcm037/env"
#
# Debugging

2
arch/arm/configs/pcm038_defconfig
View File

@ -110,7 +110,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="board/pcm038/env"
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/pcm038/env"
#
# Debugging

2
arch/arm/configs/pcm043_defconfig
View File

@ -109,7 +109,7 @@ CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="board/pcm043/env/"
CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv board/pcm043/env"
#
# Debugging

61
arch/arm/lib/armlinux.c
View File

@ -142,6 +142,25 @@ static void setup_end_tag (void)
params->hdr.size = 0;
}
static void setup_tags(void)
{
const char *commandline = getenv("bootargs");
setup_start_tag();
setup_memory_tags();
setup_commandline_tag(commandline);
#if 0
if (initrd_start && initrd_end)
setup_initrd_tag (initrd_start, initrd_end);
#endif
setup_revision_tag();
setup_end_tag();
printf("commandline: %s\n"
"arch_number: %d\n", commandline, armlinux_architecture);
}
void armlinux_set_bootparams(void *params)
{
armlinux_bootparams = params;
@ -172,7 +191,6 @@ int do_bootm_linux(struct image_data *data)
{
void (*theKernel)(int zero, int arch, void *params);
image_header_t *os_header = &data->os->header;
const char *commandline = getenv("bootargs");
if (os_header->ih_type == IH_TYPE_MULTI) {
printf("Multifile images not handled at the moment\n");
@ -189,23 +207,12 @@ int do_bootm_linux(struct image_data *data)
return -1;
}
printf("commandline: %s\n"
"arch_number: %d\n", commandline, armlinux_architecture);
theKernel = (void *)ntohl(os_header->ih_ep);
debug("## Transferring control to Linux (at address 0x%p) ...\n",
theKernel);
setup_start_tag();
setup_memory_tags();
setup_commandline_tag(commandline);
#if 0
if (initrd_start && initrd_end)
setup_initrd_tag (initrd_start, initrd_end);
#endif
setup_revision_tag();
setup_end_tag();
setup_tags();
if (relocate_image(data->os, (void *)ntohl(os_header->ih_load)))
return -1;
@ -259,7 +266,6 @@ struct zimage_header {
static int do_bootz(struct command *cmdtp, int argc, char *argv[])
{
void (*theKernel)(int zero, int arch, void *params);
const char *commandline = getenv("bootargs");
int fd, ret;
struct zimage_header header;
void *zimage;
@ -295,15 +301,7 @@ static int do_bootz(struct command *cmdtp, int argc, char *argv[])
printf("loaded zImage from %s with size %d\n", argv[1], header.end);
setup_start_tag();
setup_memory_tags();
setup_commandline_tag(commandline);
#if 0
if (initrd_start && initrd_end)
setup_initrd_tag (initrd_start, initrd_end);
#endif
setup_revision_tag();
setup_end_tag();
setup_tags();
shutdown_barebox();
theKernel(0, armlinux_architecture, armlinux_bootparams);
@ -332,21 +330,22 @@ BAREBOX_CMD_END
#ifdef CONFIG_CMD_BOOTU
static int do_bootu(struct command *cmdtp, int argc, char *argv[])
{
void (*theKernel)(int zero, int arch, void *params);
const char *commandline = getenv("bootargs");
void (*theKernel)(int zero, int arch, void *params) = NULL;
int fd;
if (argc != 2) {
barebox_cmd_usage(cmdtp);
return 1;
}
theKernel = (void *)simple_strtoul(argv[1], NULL, 0);
fd = open(argv[1], O_RDONLY);
if (fd > 0)
theKernel = (void *)memmap(fd, PROT_READ);
setup_start_tag();
setup_memory_tags();
setup_commandline_tag(commandline);
setup_revision_tag();
setup_end_tag();
if (!theKernel)
theKernel = (void *)simple_strtoul(argv[1], NULL, 0);
setup_tags();
shutdown_barebox();
theKernel(0, armlinux_architecture, armlinux_bootparams);

8
arch/arm/mach-at91rm9200/Kconfig
View File

@ -2,7 +2,6 @@ if ARCH_AT91RM9200
config ARCH_TEXT_BASE
hex
default 0x21e00000 if MACH_ECO920
config BOARDINFO
@ -12,13 +11,6 @@ choice
prompt "AT91RM9200 Board Type"
config MACH_ECO920
bool "eco920"
select HAS_AT91_ETHER
select HAS_CFI
help
Say Y here if you are using the Motorola MX1ADS board
endchoice
endif

15
arch/arm/mach-imx/Kconfig
View File

@ -4,6 +4,7 @@ config ARCH_TEXT_BASE
hex
default 0x83f00000 if MACH_EUKREA_CPUIMX25
default 0xa0000000 if MACH_EUKREA_CPUIMX27
default 0x87f00000 if MACH_EUKREA_CPUIMX35
default 0x08f00000 if MACH_MX1ADS
default 0xc0000000 if MACH_IMX21ADS
default 0xa0000000 if MACH_IMX27ADS
@ -19,6 +20,7 @@ config ARCH_TEXT_BASE
config BOARDINFO
default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
default "Eukrea CPUIMX27" if MACH_EUKREA_CPUIMX27
default "Eukrea CPUIMX35" if MACH_EUKREA_CPUIMX35
default "Freescale i.MX21 ADS" if MACH_IMX21ADS
default "Freescale i.MX27 ADS" if MACH_IMX27ADS
default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
@ -138,6 +140,8 @@ config MACH_FREESCALE_MX25_3STACK
bool "Freescale MX25 3stack"
select HAS_CFI
select MACH_HAS_LOWLEVEL_INIT
select I2C
select DRIVER_I2C_MC34704
help
Say Y here if you are using the Freescale MX25 3stack board equipped
with a Freescale i.MX25 Processor
@ -206,7 +210,9 @@ choice
config MACH_PCM037
bool "phyCORE-i.MX31"
select MACH_HAS_LOWLEVEL_INIT
select HAVE_MMU
select USB_ISP1504 if USB
select ARCH_HAS_L2X0
help
Say Y here if you are using Phytec's phyCORE-i.MX31 (pcm037) equipped
with a Freescale i.MX31 Processor
@ -223,6 +229,15 @@ choice
prompt "i.MX35 Board Type"
config MACH_EUKREA_CPUIMX35
bool "EUKREA CPUIMX35"
select HAVE_MMU
select MACH_HAS_LOWLEVEL_INIT
select ARCH_HAS_L2X0
help
Say Y here if you are using Eukrea's CPUIMX35 equipped
with a Freescale i.MX35 Processor
config MACH_FREESCALE_MX35_3STACK
bool "Freescale MX35 3stack"
select HAS_CFI

18
arch/arm/mach-imx/clocksource.c
View File

@ -35,12 +35,14 @@
#include <notifier.h>
#include <mach/imx-regs.h>
#include <mach/clock.h>
#include <asm/io.h>
#define GPT(x) __REG(IMX_TIM1_BASE + (x))
#define timer_base (IMX_TIM1_BASE)
uint64_t imx_clocksource_read(void)
{
return GPT(GPT_TCN);
return readl(timer_base + GPT_TCN);
}
static struct clocksource cs = {
@ -62,8 +64,10 @@ static struct notifier_block imx_clock_notifier = {
static int clocksource_init (void)
{
int i;
uint32_t val;
/* setup GP Timer 1 */
GPT(GPT_TCTL) = TCTL_SWR;
writel(TCTL_SWR, timer_base + GPT_TCTL);
#ifdef CONFIG_ARCH_IMX21
PCCR1 |= PCCR1_GPT1_EN;
@ -74,12 +78,12 @@ static int clocksource_init (void)
#endif
for (i = 0; i < 100; i++)
GPT(GPT_TCTL) = 0; /* We have no udelay by now */
writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */
GPT(GPT_TPRER) = 0;
GPT(GPT_TCTL) |= TCTL_FRR | (1<<TCTL_CLKSOURCE); /* Freerun Mode, PERCLK1 input */
GPT(GPT_TCTL) &= ~TCTL_TEN;
GPT(GPT_TCTL) |= TCTL_TEN; /* Enable timer */
writel(0, timer_base + GPT_TPRER);
val = readl(timer_base + GPT_TCTL);
val |= TCTL_FRR | (1 << TCTL_CLKSOURCE) | TCTL_TEN; /* Freerun Mode, PERCLK1 input */
writel(val, timer_base + GPT_TCTL);
cs.mult = clocksource_hz2mult(imx_get_gptclk(), cs.shift);

2
arch/arm/mach-imx/include/mach/imx-ipu-fb.h
View File

@ -28,6 +28,8 @@ struct imx_ipu_fb_platform_data {
const struct fb_videomode *mode;
unsigned char bpp;
void __iomem *framebuffer;
/** hook to enable backlight and stuff */
void (*enable)(int enable);
};
#endif /* __MACH_IMX_IPU_FB_H__ */

33
arch/arm/mach-imx/include/mach/imx21-regs.h
View File

@ -115,39 +115,6 @@
#define CCSR_32K_SR (1 << 15)
#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
/*
* Definitions for the clocksource driver
*/

3
arch/arm/mach-imx/include/mach/imx25-regs.h
View File

@ -21,7 +21,7 @@
*/
#ifndef __ASM_ARCH_MX25_REGS_H
#define __ASM_ARCH_MX35_REGS_H
#define __ASM_ARCH_MX25_REGS_H
/*
* sanity check
@ -46,6 +46,7 @@
#define IMX_M3IF_BASE 0xB8003000
#define IMX_NFC_BASE 0xBB000000
#define IMX_FEC_BASE 0x50038000
#define IMX_I2C1_BASE 0x43F80000
/*
* Clock Controller Module (CCM)

96
arch/arm/mach-imx/include/mach/imx27-regs.h
View File

@ -16,6 +16,7 @@
#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
#define IMX_SPI1_BASE (0x0e000 + IMX_IO_BASE)
#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
@ -25,9 +26,11 @@
#define IMX_I2C2_BASE (0x1d000 + IMX_IO_BASE)
#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
#define IMX_FB_BASE (0x21000 + IMX_IO_BASE)
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE)
#define IMX_OTG_BASE (0x24000 + IMX_IO_BASE)
#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
#define IMX_NFC_BASE (0xd8000000)
#define IMX_ESD_BASE (0xd8001000)
@ -232,99 +235,6 @@
#define ESDMISC_MA10_SHARE (1 << 6)
#define ESDMISC_SDRAM_RDY (1 << 6)
#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5)
#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
/*
* Definitions for the clocksource driver
*/

2
arch/arm/mach-imx/include/mach/imxfb.h
View File

@ -74,6 +74,8 @@ struct imx_fb_platform_data {
void *framebuffer;
/** force a memory area to be used, else NULL for dynamic allocation */
void *framebuffer_ovl;
/** hook to enable backlight and stuff */
void (*enable)(int enable);
};
void set_imx_fb_info(struct imx_fb_platform_data *);

121
arch/arm/mach-imx/include/mach/iomux-mx21.h Normal file
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@ -0,0 +1,121 @@
/*
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_IOMUX_MX21_H__
#define __MACH_IOMUX_MX21_H__
#include <mach/iomux-mx2x.h>
/* Primary GPIO pin functions */
#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
/* Alternate GPIO pin functions */
#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
/* AIN GPIO pin functions */
#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
/* BIN GPIO pin functions */
#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
/* CIN GPIO pin functions */
#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
/* AOUT GPIO pin functions */
#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
#endif /* ifndef __MACH_IOMUX_MX21_H__ */

4
arch/arm/mach-imx/include/mach/iomux-mx25.h
View File

@ -417,10 +417,10 @@
#define MX25_PAD_HSYNC__GPIO22 IOMUX_PAD(0x300, 0x108, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_HSYNC__USBH2_DATA4 IOMUX_PAD(0x300, 0x108, 6, 0, 0, 0xe5)
#define MX25_PAD_HSYNC__BT_UART_SRC1 IOMUX_PAD(0x300, 0x108, 7, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__SCL IOMUX_PAD(0x348, 0x150, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__SCL IOMUX_PAD(0x348, 0x150, 0, 0, 0, (HYS | PKE | PUE | PUS_100K_UP))
#define MX25_PAD_I2C1_CLK__GPIO12 IOMUX_PAD(0x348, 0x150, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_CLK__SLCDC_DATA6 IOMUX_PAD(0x348, 0x150, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__SDA IOMUX_PAD(0x34c, 0x154, 0, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__SDA IOMUX_PAD(0x34c, 0x154, 0, 0, 0, (HYS | PKE | PUE | PUS_100K_UP))
#define MX25_PAD_I2C1_DAT__GPIO13 IOMUX_PAD(0x34c, 0x154, 5, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_I2C1_DAT__SLCDC_DATA7 IOMUX_PAD(0x34c, 0x154, 6, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_KPP_COL0__COL0 IOMUX_PAD(0x3b0, 0x1b8, 0, 0, 0, NO_PAD_CTRL)

204
arch/arm/mach-imx/include/mach/iomux-mx27.h Normal file
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@ -0,0 +1,204 @@
/*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_IOMUX_MX27_H__
#define __MACH_IOMUX_MX27_H__
#include <mach/iomux-mx2x.h>
/* Primary GPIO pin functions */
#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
/* Alternate GPIO pin functions */
#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
/* AIN GPIO pin functions */
#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
/* BIN GPIO pin functions */
#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
/* CIN GPIO pin functions */
#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
/* AOUT GPIO pin functions */
#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
/* BOUT GPIO pin functions */
#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
#endif /* __MACH_IOMUX_MX27_H__ */

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/*
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#ifndef __MACH_IOMUX_MX2x_H__
#define __MACH_IOMUX_MX2x_H__
/* Primary GPIO pin functions */
#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19)
#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20)
#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21)
#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22)
#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23)
#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24)
#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
/* Alternate GPIO pin functions */
#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
/* AIN GPIO pin functions */
#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
/* BIN GPIO pin functions */
#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
/* CIN GPIO pin functions */
#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
/* AOUT GPIO pin functions */
#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
#endif /* ifndef __MACH_IOMUX_MX2x_H__ */

5
arch/arm/mach-imx/speed-imx25.c
View File

@ -77,6 +77,11 @@ unsigned long imx_get_lcdclk(void)
return imx_get_perclk(7);
}
unsigned long imx_get_i2cclk(void)
{
return imx_get_perclk(6);
}
int imx_dump_clocks(void)
{
printf("mpll: %10d Hz\n", imx_get_mpllclk());

2
board/eco920/Makefile
View File

@ -1,2 +0,0 @@
obj-y += eco920.o

134
board/eco920/config.h
View File

@ -1,134 +0,0 @@
/*
* (C) Copyright 2007 Pengutronix
* Sascha Hauer, <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/* ARM asynchronous clock */
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define USE_920T_MMU 1
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CFG_USE_MAIN_OSCILLATOR 1
/* flash */
#define MC_PUIA_VAL 0x00000000
#define MC_PUP_VAL 0x00000000
#define MC_PUER_VAL 0x00000000
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
#define SMC2_CSR_VAL 0x00003287
/* clocks */
#define PLLAR_VAL 0x2026be04
#define PLLBR_VAL 0x10483e0e
#define MCKR_VAL 0x00000202
/* sdram */
#define PIOC_ASR_VAL 0xffff0000
#define PIOC_BSR_VAL 0x00000000
#define PIOC_PDR_VAL 0xffff0000
#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
#define SDRAM 0x20000000 /* address of the SDRAM */
#define SDRAM1 0x20000080 /* address of the SDRAM */
#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
#define SDRC_MR_VAL 0x00000002 /* Precharge All */
#define SDRC_MR_VAL1 0x00000004 /* refresh */
#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#define CONFIG_BAUDRATE 115200
/*
* Hardware drivers
*/
/* define one of CONFIG_DBGU, CONFIG_USART0 or CONFIG_USART1 to choose console */
#define CONFIG_DBGU
#define CONFIG_BOOTDELAY 3
#define CONFIG_CMDLINE_EDITING 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdids=nor0=physmap-flash.0\0" \
"mtdparts=mtdparts=physmap-flash.0:128k(barebox)ro,128k(env),1536k(kernel),-(jffs2)\0" \
"bootargs_base=setenv bootargs console=ttyAT0,115200\0" \
"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
"bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
"bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock3 rootfstype=jffs2\0" \
"bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x11040000\0" \
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x20000000 $(uimage); bootm\0" \
"autoload=n\0" \
"uimage=uImage-eco920\0" \
"jffs2=root-eco920.jffs2\0"
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x20000000
#define PHYS_SDRAM_SIZE 0x2000000
#define CFG_MEMTEST_START PHYS_SDRAM
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
#define CONFIG_DRIVER_ETHER
#define CONFIG_NET_RETRY_COUNT 20
#define CONFIG_AT91C_USE_RMII
#define CFG_LOAD_ADDR 0x21000000 /* default load address */
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "barebox> " /* Monitor Command Prompt */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_MAXARGS 32 /* max number of command args */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CLOCK_TICK_RATE AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
/* AT91C_TC_TIMER_DIV1_CLOCK */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
#define CFG_SPLASH 1
#define CFG_S1D13706FB 1
#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
#define CFG_USB_OHCI_SLOT_NAME "at91rm9200"
#define LITTLEENDIAN
#define CONFIG_AT91C_PQFP_UHPBUG
#endif

1
board/eco920/config.mk
View File

@ -1 +0,0 @@
TEXT_BASE = 0x21f00000

211
board/eco920/eco920.c
View File

@ -1,211 +0,0 @@
/*
* (C) Copyright 2007 Pengutronix
* Sascha Hauer, <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mach/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
#include <miiphy.h>
#include <splash.h>
#include <asm/armlinux.h>
#include <s1d13706fb.h>
#include <net.h>
#include <init.h>
/*
* Miscelaneous platform dependent initialisations
*/
static struct cfi_platform_data cfi_info = {
};
struct device_d cfi_dev = {
.name = "cfi_flash",
.map_base = 0x11000000,
.size = 16 * 1024 * 1024,
.platform_data = &cfi_info,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
struct device_d sdram_dev = {
.name = "mem",
.map_base = 0x20000000,
.size = 32 * 1024 * 1024,
.platform_data = &ram_pdata,
};
static struct device_d at91_ath_dev = {
.name = "at91_eth",
};
static int devices_init (void)
{
register_device(&cfi_dev);
register_device(&sdram_dev);
register_device(&at91_ath_dev);
armlinux_set_bootparams((void *)(PHYS_SDRAM + 0x100));
armlinux_set_architecture(MACH_TYPE_ECO920);
return 0;
}
device_initcall(devices_init);
static unsigned int phy_is_connected (AT91PS_EMAC p_mac)
{
return 1;
}
static unsigned char phy_init_bogus (AT91PS_EMAC p_mac)
{
unsigned short val;
int timeout, adr, speed, fullduplex;
at91rm9200_EmacEnableMDIO (p_mac);
/* Scan through phy addresses to find a phy */
for (adr = 0; adr < 16; adr++) {
at91rm9200_EmacReadPhy(p_mac, PHY_PHYIDR1 | (adr << 5), &val);
if (val != 0xffff)
break;
}
adr <<= 5;
val = PHY_BMCR_RESET;
at91rm9200_EmacWritePhy(p_mac, PHY_BMCR | adr, &val);
udelay(1000);
val = 0x01e1; /* ADVERTISE_100FULL | ADVERTISE_100HALF |
* ADVERTISE_10FULL | ADVERTISE_10HALF |
* ADVERTISE_CSMA */
at91rm9200_EmacWritePhy(p_mac, PHY_ANAR | adr, &val);
at91rm9200_EmacReadPhy(p_mac, PHY_BMCR | adr, &val);
val |= PHY_BMCR_AUTON | PHY_BMCR_RST_NEG;
at91rm9200_EmacWritePhy(p_mac, PHY_BMCR | adr, &val);
timeout = 500;
do {
/* at91rm9200_EmacReadPhy() has a udelay(10000)
* in it, so this should be about 5 deconds
*/
if ((timeout--) == 0) {
printf("Autonegotiation timeout\n");
goto out;
}
at91rm9200_EmacReadPhy(p_mac, PHY_BMSR | adr, &val);
} while (!(val & PHY_BMSR_LS));
at91rm9200_EmacReadPhy(p_mac, PHY_ANLPAR | adr, &val);
if (val & PHY_ANLPAR_100) {
speed = 100;
p_mac->EMAC_CFG |= AT91C_EMAC_SPD;
} else {
speed = 10;
p_mac->EMAC_CFG &= ~AT91C_EMAC_SPD;
}
if (val & (PHY_ANLPAR_TXFD | PHY_ANLPAR_10FD)) {
fullduplex = 1;
p_mac->EMAC_CFG |= AT91C_EMAC_FD;
} else {
fullduplex = 0;
p_mac->EMAC_CFG &= ~AT91C_EMAC_FD;
}
printf("running at %d-%sDuplex\n",speed, fullduplex ? "FUll" : "Half");
out:
at91rm9200_EmacDisableMDIO (p_mac);
return 1;
}
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = phy_init_bogus;
p_phyops->IsPhyConnected = phy_is_connected;
/* This is not used anywhere */
p_phyops->GetLinkSpeed = NULL;
/* ditto */
p_phyops->AutoNegotiate = NULL;
}
#ifdef CONFIG_DRIVER_VIDEO_S1D13706
static int efb_init(struct efb_info *efb)
{
writeb(GPIO_CONTROL0_GPO, efb->regs + EFB_GPIO_CONTROL1);
writeb(PCLK_SOURCE_CLKI2, efb->regs + EFB_PCLK_CONF);
writeb(0x1, efb->regs + 0x26); /* FIXME: display specific, should be set to zero
* according to datasheet
*/
return 0;
}
/* Nanya STN Display */
static struct efb_info efb = {
.fbd = {
.xres = 320,
.yres = 240,
.bpp = 8,
.fb = (void*)0x40020000,
},
.init = efb_init,
.regs = (void*)0x40000000,
.pixclock = 100000,
.hsync_len = 1,
.left_margin = 22,
.right_margin = 1,
.vsync_len = 1,
.upper_margin = 0,
.lower_margin = 1,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.panel_type = PANEL_TYPE_STN | PANEL_TYPE_WIDTH_8 |
PANEL_TYPE_COLOR | PANEL_TYPE_FORMAT_2,
};
#endif
#define SMC_CSR3 0xFFFFFF7C
int misc_init_r(void)
{
/* Initialization of the Static Memory Controller for Chip Select 3 */
*(volatile unsigned long*)SMC_CSR3 = 0x00002185;
#ifdef CONFIG_DRIVER_VIDEO_S1D13706
s1d13706fb_init(&efb);
#endif
#ifdef CONFIG_CMD_SPLASH
splash_set_fb_data(&efb.fbd);
#endif
return 0;
}

3
board/eukrea_cpuimx27/eukrea_cpuimx27.c
View File

@ -45,6 +45,7 @@
#include <asm/mmu.h>
#include <i2c/i2c.h>
#include <i2c/lp3972.h>
#include <mach/iomux-mx27.h>
static struct device_d cfi_dev = {
.name = "cfi_flash",
@ -230,7 +231,7 @@ static int eukrea_cpuimx27_devices_init(void)
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,

25
board/eukrea_cpuimx35/Makefile Normal file
View File

@ -0,0 +1,25 @@
#
# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
obj-y += lowlevel.o
obj-y += eukrea_cpuimx35.o
obj-$(CONFIG_ARCH_IMX_INTERNAL_BOOT) += flash_header.o

23
board/eukrea_cpuimx35/config.h Normal file
View File

@ -0,0 +1,23 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_MX35_HCLK_FREQ 24000000
#endif /* __CONFIG_H */

0
board/pcm037/env/bin/_update → board/eukrea_cpuimx35/env/bin/_update vendored
View File

52
board/eukrea_cpuimx35/env/bin/boot vendored Normal file
View File

@ -0,0 +1,52 @@
#!/bin/sh
. /env/config
if [ x$1 = xjffS2 ]; then
root=jffs2
kernel=nand
fi
if [ x$1 = xubifs ]; then
root=ubifs
kernel=nand
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
if [ x$ip = xoff ]; then
bootargs="$bootargs ip=off"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
fi
if [ x$root = xjffs2 ]; then
bootargs="$bootargs root=/dev/mtdblock$rootpartnum_nand rootfstype=jffs2"
fi
if [ x$root = xubifs ]; then
bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum_nand rootfstype=ubifs"
fi
if [ x$root = xnet ]; then
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
fi
bootargs="$bootargs mtdparts=mxc_nand:$nand_parts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
else
bootm /dev/nand0.kernel.bb
fi

0
board/pcm037/env/bin/hush_hack → board/eukrea_cpuimx35/env/bin/hush_hack vendored
View File

16
board/pcm043/env/bin/init → board/eukrea_cpuimx35/env/bin/init vendored
View File

@ -4,10 +4,6 @@ PATH=/env/bin
export PATH
. /env/config
if [ -e /dev/nor0 ]; then
addpart /dev/nor0 $nor_parts
fi
if [ -e /dev/nand0 ]; then
addpart /dev/nand0 $nand_parts
@ -16,11 +12,19 @@ if [ -e /dev/nand0 ]; then
source /env/bin/hush_hack
fi
if [ -f /env/logo.bmp ]; then
bmp /env/logo.bmp
elif [ -f /env/logo.bmp.lzo ]; then
unlzo /env/logo.bmp.lzo /logo.bmp
bmp /logo.bmp
fi
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
done
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
saveenv
fi
echo
@ -28,8 +32,8 @@ echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
echo "type update_kernel [<imagename>] to update kernel into flash"
echo "type update_root [<imagename>] to update rootfs into flash"
echo
exit
fi

8
board/eukrea_cpuimx35/env/bin/update_kernel vendored Normal file
View File

@ -0,0 +1,8 @@
#!/bin/sh
. /env/config
image=$uimage
part=/dev/nand0.kernel.bb
. /env/bin/_update $1

8
board/eukrea_cpuimx35/env/bin/update_root vendored Normal file
View File

@ -0,0 +1,8 @@
#!/bin/sh
. /env/config
image=$rootfs
part=/dev/nand0.root.bb
. /env/bin/_update $1

27
board/eukrea_cpuimx35/env/config vendored Normal file
View File

@ -0,0 +1,27 @@
#!/bin/sh
# can be either 'net' or 'nand''
kernel=nand
root=ubifs
basedir=cpuimx35
uimage=$basedir/uImage
rootfs=$basedir/rootfs
autoboot_timeout=1
nfsroot=""
bootargs="console=ttymxc0,115200"
nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)"
rootpartnum_nand=3
ubiroot="eukrea-cpuimx35-rootfs"
# use 'dhcp' to do dhcp in barebox and in kernel
ip=off
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d

343
board/eukrea_cpuimx35/eukrea_cpuimx35.c Normal file
View File

@ -0,0 +1,343 @@
/*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* 2009 Marc Kleine-Budde, Pengutronix
* (c) 2010 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Derived from:
*
* * mx35_3stack.c - board file for uboot-v1
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*
*/
#include <common.h>
#include <command.h>
#include <environment.h>
#include <errno.h>
#include <fcntl.h>
#include <fec.h>
#include <fs.h>
#include <init.h>
#include <nand.h>
#include <net.h>
#include <partition.h>
#include <asm/armlinux.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mmu.h>
#include <mach/gpio.h>
#include <mach/imx-nand.h>
#include <mach/imx-regs.h>
#include <mach/iomux-mx35.h>
#include <mach/iomux-v3.h>
#include <mach/pmic.h>
#include <mach/imx-ipu-fb.h>
#include <mach/imx-pll.h>
static struct fec_platform_data fec_info = {
.xcv_type = MII100,
.phy_addr = 0x1F,
};
static struct device_d fec_dev = {
.name = "fec_imx",
.map_base = IMX_FEC_BASE,
.platform_data = &fec_info,
};
static struct memory_platform_data sdram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.name = "mem",
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.platform_data = &sdram_pdata,
};
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct device_d nand_dev = {
.name = "imx_nand",
.map_base = IMX_NFC_BASE,
.platform_data = &nand_info,
};
static struct fb_videomode imxfb_mode = {
.name = "CMO_QVGA",
.refresh = 60,
.xres = 320,
.yres = 240,
.pixclock = KHZ2PICOS(7000),
.left_margin = 68,
.right_margin = 20,
.upper_margin = 15,
.lower_margin = 4,
.hsync_len = 30,
.vsync_len = 3,
.sync = FB_SYNC_OE_ACT_HIGH,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
};
static struct imx_ipu_fb_platform_data ipu_fb_data = {
.mode = &imxfb_mode,
.bpp = 16,
};
static struct device_d imxfb_dev = {
.name = "imx-ipu-fb",
.map_base = 0x53fc0000,
.size = 0x1000,
.platform_data = &ipu_fb_data,
};
#ifdef CONFIG_MMU
static int eukrea_cpuimx35_mmu_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
#if TEXT_BASE & (0x100000 - 1)
#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
#else
arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
#endif
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
return 0;
}
postcore_initcall(eukrea_cpuimx35_mmu_init);
#endif
static int eukrea_cpuimx35_devices_init(void)
{
register_device(&nand_dev);
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
register_device(&fec_dev);
register_device(&sdram_dev);
register_device(&imxfb_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX35);
return 0;
}
device_initcall(eukrea_cpuimx35_devices_init);
static int eukrea_cpuimx35_enable_display(void)
{
gpio_direction_output(1, 1);
gpio_direction_output(0, 0);
return 0;
}
late_initcall(eukrea_cpuimx35_enable_display);
static struct device_d eukrea_cpuimx35_serial_device = {
.name = "imx_serial",
.map_base = IMX_UART1_BASE,
.size = 4096,
};
static struct pad_desc eukrea_cpuimx35_pads[] = {
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
MX35_PAD_FEC_RX_DV__FEC_RX_DV,
MX35_PAD_FEC_COL__FEC_COL,
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
MX35_PAD_FEC_TX_EN__FEC_TX_EN,
MX35_PAD_FEC_MDC__FEC_MDC,
MX35_PAD_FEC_MDIO__FEC_MDIO,
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
MX35_PAD_FEC_CRS__FEC_CRS,
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
MX35_PAD_RXD1__UART1_RXD_MUX,
MX35_PAD_TXD1__UART1_TXD_MUX,
MX35_PAD_RTS1__UART1_RTS,
MX35_PAD_CTS1__UART1_CTS,
};
static int eukrea_cpuimx35_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
ARRAY_SIZE(eukrea_cpuimx35_pads));
register_device(&eukrea_cpuimx35_serial_device);
return 0;
}
console_initcall(eukrea_cpuimx35_console_init);
static int eukrea_cpuimx35_core_init(void)
{
u32 reg;
/* enable clock for I2C1 and FEC */
reg = readl(IMX_CCM_BASE + CCM_CGR1);
reg |= 0x3 << CCM_CGR1_FEC_SHIFT;
reg = writel(reg, IMX_CCM_BASE + CCM_CGR1);
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
* not forced to user-mode.
*/
writel(0x77777777, IMX_AIPS1_BASE);
writel(0x77777777, IMX_AIPS1_BASE + 0x4);
writel(0x77777777, IMX_AIPS2_BASE);
writel(0x77777777, IMX_AIPS2_BASE + 0x4);
/*
* Clear the on and off peripheral modules Supervisor Protect bit
* for SDMA to access them. Did not change the AIPS control registers
* (offset 0x20) access type
*/
writel(0x0, IMX_AIPS1_BASE + 0x40);
writel(0x0, IMX_AIPS1_BASE + 0x44);
writel(0x0, IMX_AIPS1_BASE + 0x48);
writel(0x0, IMX_AIPS1_BASE + 0x4C);
reg = readl(IMX_AIPS1_BASE + 0x50);
reg &= 0x00FFFFFF;
writel(reg, IMX_AIPS1_BASE + 0x50);
writel(0x0, IMX_AIPS2_BASE + 0x40);
writel(0x0, IMX_AIPS2_BASE + 0x44);
writel(0x0, IMX_AIPS2_BASE + 0x48);
writel(0x0, IMX_AIPS2_BASE + 0x4C);
reg = readl(IMX_AIPS2_BASE + 0x50);
reg &= 0x00FFFFFF;
writel(reg, IMX_AIPS2_BASE + 0x50);
/* MAX (Multi-Layer AHB Crossbar Switch) setup */
/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
#define MAX_PARAM1 0x00302154
writel(MAX_PARAM1, IMX_MAX_BASE + 0x000); /* for S0 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */
writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */
/* SGPCR - always park on last master */
writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */
writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */
writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */
writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */
writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */
/* MGPCR - restore default values */
writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */
writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */
writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */
writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */
writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */
writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */
/*
* M3IF Control Register (M3IFCTL)
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
* MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000
* MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000
* MRRP[3] = USB not on priority list (0 << 0) = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
* MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
* ------------
* 0x00000040
*/
writel(0x40, IMX_M3IF_BASE);
return 0;
}
core_initcall(eukrea_cpuimx35_core_init);
#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
static int do_cpufreq(struct command *cmdtp, int argc, char *argv[])
{
unsigned long freq;
if (argc != 2)
return COMMAND_ERROR_USAGE;
freq = simple_strtoul(argv[1], NULL, 0);
switch (freq) {
case 399:
writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL);
break;
case 532:
writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL);
break;
default:
return COMMAND_ERROR_USAGE;
}
printf("Switched CPU frequency to %dMHz\n", freq);
return 0;
}
static const __maybe_unused char cmd_cpufreq_help[] =
"Usage: cpufreq 399|532\n"
"\n"
"Set CPU frequency to <freq> MHz\n";
BAREBOX_CMD_START(cpufreq)
.cmd = do_cpufreq,
.usage = "adjust CPU frequency",
BAREBOX_CMD_HELP(cmd_cpufreq_help)
BAREBOX_CMD_END

4
board/eukrea_cpuimx35/eukrea_cpuimx35.dox Normal file
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@ -0,0 +1,4 @@
/** @page eukrea_cpuimx35 Eukrea's CPUIMX35
*/

60
board/eukrea_cpuimx35/flash_header.c Normal file
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@ -0,0 +1,60 @@
#include <common.h>
#include <mach/imx-flash-header.h>
extern unsigned long _stext;
void __naked __flash_header_start go(void)
{
__asm__ __volatile__("b exception_vectors\n");
}
struct imx_dcd_entry __dcd_entry_0x400 dcd_entry[] = {
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, },
{ .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc3f, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, },
{ .ptr_type = 1, .addr = 0x80000400, .val = 0x12345678, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, },
{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, },
{ .ptr_type = 1, .addr = 0x80000033, .val = 0xda, },
{ .ptr_type = 1, .addr = 0x82000000, .val = 0xda, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001004, .val = 0x007ffc2f, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82220080, },
{ .ptr_type = 4, .addr = 0xB8001000, .val = 0x82228080, },
{ .ptr_type = 4, .addr = 0xB8001020, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB8001024, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB8001028, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB800102c, .val = 0x80000028, },
{ .ptr_type = 4, .addr = 0xB8001030, .val = 0x80000028, },
};
#define APP_DEST 0x80000000
struct imx_flash_header __flash_header_0x400 flash_header = {
.app_code_jump_vector = APP_DEST + 0x1000,
.app_code_barker = APP_CODE_BARKER,
.app_code_csf = 0,
.dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
.super_root_key = 0,
.dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
.app_dest = APP_DEST,
.dcd_barker = DCD_BARKER,
.dcd_block_len = sizeof (dcd_entry),
};
unsigned long __image_len_0x400 barebox_len = 0x40000;

218
board/eukrea_cpuimx35/lowlevel.c Normal file
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@ -0,0 +1,218 @@
/*
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <init.h>
#include <mach/imx-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
#include <asm/io.h>
#include <mach/imx-nand.h>
#include <asm/barebox-arm.h>
#include <asm-generic/memory_layout.h>
#include <asm/system.h>
/* Assuming 24MHz input clock */
#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5))
#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1))
#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1))
#ifdef CONFIG_NAND_IMX_BOOT
static void __bare_init __naked insdram(void)
{
uint32_t r;
/* Speed up NAND controller by adjusting the NFC divider */
r = readl(IMX_CCM_BASE + CCM_PDR4);
r &= ~(0xf << 28);
r |= 0x1 << 28;
writel(r, IMX_CCM_BASE + CCM_PDR4);
/* setup a stack to be able to call imx_nand_load_image() */
r = STACK_BASE + STACK_SIZE - 12;
__asm__ __volatile__("mov sp, %0" : : "r"(r));
imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
board_init_lowlevel_return();
}
#endif
void __bare_init __naked board_init_lowlevel(void)
{
uint32_t r, s;
unsigned long ccm_base = IMX_CCM_BASE;
unsigned long iomuxc_base = IMX_IOMUXC_BASE;
#ifdef CONFIG_NAND_IMX_BOOT
unsigned int *trg, *src;
int i;
#endif
r = get_cr();
r |= CR_Z; /* Flow prediction (Z) */
r |= CR_U; /* unaligned accesses */
r |= CR_FI; /* Low Int Latency */
__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(s));
s |= 0x7;
__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : : "r"(s));
set_cr(r);
r = 0;
__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
/*
* Branch predicition is now enabled. Flush the BTAC to ensure a valid
* starting point. Don't flush BTAC while it is disabled to avoid
* ARM1136 erratum 408023.
*/
__asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r));
/* invalidate I cache and D cache */
__asm__ __volatile__("mcr p15, 0, %0, c7, c7, 0" : : "r"(r));
/* invalidate TLBs */
__asm__ __volatile__("mcr p15, 0, %0, c8, c7, 0" : : "r"(r));
/* Drain the write buffer */
__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(r));
/* Also setup the Peripheral Port Remap register inside the core */
r = 0x40000015; /* start from AIPS 2GB region */
__asm__ __volatile__("mcr p15, 0, %0, c15, c2, 4" : : "r"(r));
/*
* End of ARM1136 init
*/
writel(0x003F4208, ccm_base + CCM_CCMR);
/* Set MPLL , arm clock and ahb clock*/
writel(MPCTL_PARAM_532, ccm_base + CCM_MPCTL);
writel(PPCTL_PARAM_300, ccm_base + CCM_PPCTL);
writel(0x00001000, ccm_base + CCM_PDR0);
r = readl(ccm_base + CCM_CGR0);
r |= 0x00300000;
writel(r, ccm_base + CCM_CGR0);
r = readl(ccm_base + CCM_CGR1);
r |= 0x00000C00;
r |= 0x00000003;
writel(r, ccm_base + CCM_CGR1);
r = readl(IMX_L2CC_BASE + L2X0_AUX_CTRL);
r |= 0x1000;
writel(r, IMX_L2CC_BASE + L2X0_AUX_CTRL);
/* Skip SDRAM initialization if we run from RAM */
r = get_pc();
if (r > 0x80000000 && r < 0x90000000)
board_init_lowlevel_return();
/* Set DDR Type to SDRAM, drive strength workaround *
* 0x00000000 MDDR *
* 0x00000800 3,3V SDRAM */
r = 0x00000800;
writel(r, iomuxc_base + 0x794);
writel(r, iomuxc_base + 0x798);
writel(r, iomuxc_base + 0x79c);
writel(r, iomuxc_base + 0x7a0);
writel(r, iomuxc_base + 0x7a4);
/* MDDR init, enable mDDR*/
writel(0x00000304, ESDMISC); /* was 0x00000004 */
/* set timing paramters */
writel(0x00255417, ESDCFG0);
/* select Precharge-All mode */
writel(0x92220000, ESDCTL0);
/* Precharge-All */
writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
/* select Load-Mode-Register mode */
writel(0xB8001000, ESDCTL0);
/* Load reg EMR2 */
writeb(0xda, 0x84000000);
/* Load reg EMR3 */
writeb(0xda, 0x86000000);
/* Load reg EMR1 -- enable DLL */
writeb(0xda, 0x82000400);
/* Load reg MR -- reset DLL */
writeb(0xda, 0x80000333);
/* select Precharge-All mode */
writel(0x92220000, ESDCTL0);
/* Precharge-All */
writel(0x12345678, IMX_SDRAM_CS0 + 0x400);
/* select Manual-Refresh mode */
writel(0xA2220000, ESDCTL0);
/* Manual-Refresh 2 times */
writel(0x87654321, IMX_SDRAM_CS0);
writel(0x87654321, IMX_SDRAM_CS0);
/* select Load-Mode-Register mode */
writel(0xB2220000, ESDCTL0);
/* Load reg MR -- CL3, BL8, end DLL reset */
writeb(0xda, 0x80000233);
/* Load reg EMR1 -- OCD default */
writeb(0xda, 0x82000780);
/* Load reg EMR1 -- OCD exit */
writeb(0xda, 0x82000400);
/* select normal-operation mode
* DSIZ32-bit, BL8, COL10-bit, ROW13-bit
* disable PWT & PRCT
* disable Auto-Refresh */
writel(0x82220080, ESDCTL0);
/* enable Auto-Refresh */
writel(0x82228080, ESDCTL0);
/* enable Auto-Refresh */
writel(0x00002000, ESDCTL1);
#ifdef CONFIG_NAND_IMX_BOOT
/* skip NAND boot if not running from NFC space */
r = get_pc();
if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
board_init_lowlevel_return();
src = (unsigned int *)IMX_NFC_BASE;
trg = (unsigned int *)TEXT_BASE;
/* Move ourselves out of NFC SRAM */
for (i = 0; i < 0x800 / sizeof(int); i++)
*trg++ = *src++;
/* Jump to SDRAM */
r = (unsigned int)&insdram;
__asm__ __volatile__("mov pc, %0" : : "r"(r));
#else
board_init_lowlevel_return();
#endif
}

84
board/freescale-mx25-3-stack/3stack.c
View File

@ -36,6 +36,9 @@
#include <nand.h>
#include <mach/imx-flash-header.h>
#include <mach/iomux-mx25.h>
#include <linux/err.h>
#include <i2c/i2c.h>
#include <i2c/mc34704.h>
extern unsigned long _stext;
@ -183,11 +186,35 @@ static struct device_d usbh2_dev = {
};
#endif
#define IOMUXC_BASE_ADDR 0x43FAC000
static struct i2c_board_info i2c_devices[] = {
{
I2C_BOARD_INFO("mc34704", 0x54),
},
};
static int imx25_devices_init(void)
static struct device_d i2c_dev = {
.name = "i2c-imx",
.map_base = IMX_I2C1_BASE,
};
static int imx25_3ds_pmic_init(void)
{
ulong val;
struct mc34704 *pmic;
pmic = mc34704_get();
if (pmic == NULL)
return -EIO;
return mc34704_reg_write(pmic, 0x2, 0x9);
}
static int imx25_3ds_fec_init(void)
{
int ret;
ret = imx25_3ds_pmic_init();
if (ret < 0)
return ret;
/*
* Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
@ -197,36 +224,27 @@ static int imx25_devices_init(void)
* FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
* FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
*/
writel(0x8, IOMUXC_BASE_ADDR + 0x0238); /* open drain */
writel(0x0, IOMUXC_BASE_ADDR + 0x028C); /* cmos, no pu/pd */
writel(0x8, IMX_IOMUXC_BASE + 0x0238); /* open drain */
writel(0x0, IMX_IOMUXC_BASE + 0x028C); /* cmos, no pu/pd */
#define GPIO2_BASE_ADDR 0x53FD0000
#define GPIO4_BASE_ADDR 0x53F9C000
#define GPIO_GDIR 0x04
#define GPIO_DR 0x00
#define FEC_ENABLE_GPIO 35
#define FEC_RESET_B_GPIO 104
/* make the pins output */
val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_GDIR);
writel(val, GPIO2_BASE_ADDR + GPIO_GDIR);
val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_GDIR);
writel(val, GPIO4_BASE_ADDR + GPIO_GDIR);
/* drop PHY power */
val = readl(GPIO2_BASE_ADDR + GPIO_DR) & ~(1 << 3);
writel(val, GPIO2_BASE_ADDR + GPIO_DR);
/* assert reset */
val = readl(GPIO4_BASE_ADDR + GPIO_DR) & ~(1 << 8);
writel(val, GPIO4_BASE_ADDR + GPIO_DR);
gpio_direction_output(FEC_ENABLE_GPIO, 0); /* drop PHY power */
gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
udelay(2);
/* turn on power & lift reset */
val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_DR);
writel(val, GPIO2_BASE_ADDR + GPIO_DR);
val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_DR);
writel(val, GPIO4_BASE_ADDR + GPIO_DR);
gpio_set_value(FEC_ENABLE_GPIO, 1);
gpio_set_value(FEC_RESET_B_GPIO, 1);
return 0;
}
late_initcall(imx25_3ds_fec_init);
static int imx25_devices_init(void)
{
#ifdef CONFIG_USB
/* USB does not work yet. Don't know why. Maybe
* the CPLD has to be initialized.
@ -235,11 +253,6 @@ static int imx25_devices_init(void)
register_device(&usbh2_dev);
#endif
/* FEC does only work when the CPLD is initialized.
* Currently we do not do this in barebox, so it
* does only work when Linux has been started after
* the last powercycle.
*/
register_device(&fec_dev);
if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14))
@ -256,6 +269,10 @@ static int imx25_devices_init(void)
register_device(&sdram0_dev);
register_device(&sram0_dev);
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX25_3DS);
@ -303,6 +320,9 @@ static struct pad_desc imx25_pads[] = {
MX25_PAD_VSYNC__USBH2_DATA5,
MX25_PAD_LSCLK__USBH2_DATA6,
MX25_PAD_OE_ACD__USBH2_DATA7,
/* i2c */
MX25_PAD_I2C1_CLK__SCL,
MX25_PAD_I2C1_DAT__SDA,
};
static int imx25_console_init(void)
@ -320,7 +340,7 @@ console_initcall(imx25_console_init);
#ifdef CONFIG_NAND_IMX_BOOT
void __bare_init nand_boot(void)
{
imx_nand_load_image((void *)TEXT_BASE, 256 * 1024, 2048, 16384);
imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
}
#endif

13
board/freescale-mx25-3-stack/lowlevel_init.S
View File

@ -24,7 +24,6 @@
#include <mach/imx-regs.h>
#include <mach/imx-pll.h>
#include <mach/esdctl.h>
#include <asm/cache-l2x0.h>
#define writel(val, reg) \
ldr r0, =reg; \
@ -56,13 +55,7 @@ CCM_BASE_ADDR_W: .word IMX_CCM_BASE
board_init_lowlevel:
mov r10, lr
/*
* End of ARM1136 init
*/
#define MX25_CCM_MCR 0x64
#define MX25_CCM_CGR0 0x0c
#define MX25_CCM_CGR1 0x10
#define MX25_CCM_CGR2 0x14
ldr r0, CCM_BASE_ADDR_W
/* default CLKO to 1/32 of the ARM core */
@ -75,9 +68,9 @@ board_init_lowlevel:
str r1, [r0, #MX25_CCM_MCR]
/* enable all the clocks */
writel(0x1FFFFFFF, IMX_CCM_BASE + MX25_CCM_CGR0)
writel(0xFFFFFFFF, IMX_CCM_BASE + MX25_CCM_CGR1)
writel(0x000FDFFF, IMX_CCM_BASE + MX25_CCM_CGR2)
writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0)
writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1)
writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2)
writel(0x0000FEFF, IMX_CCM_BASE + MX25_CCM_MCR)
/* Skip SDRAM initialization if we run from RAM */

1
board/imx21ads/imx21ads.c
View File

@ -35,6 +35,7 @@
#include <asm/mach-types.h>
#include <mach/imx-nand.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx21.h>
#define MX21ADS_IO_REG 0xCC800000
#define MX21ADS_IO_LCDON (1 << 9)

3
board/imx27ads/imx27ads.c
View File

@ -31,6 +31,7 @@
#include <fs.h>
#include <fcntl.h>
#include <asm/mach-types.h>
#include <mach/iomux-mx27.h>
static struct device_d cfi_dev = {
.name = "cfi_flash",
@ -114,7 +115,7 @@ static int mx27ads_devices_init(void)
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,

47
board/pcm037/env/bin/boot vendored
View File

@ -1,47 +0,0 @@
#!/bin/sh
. /env/config
if [ x$1 = xnand ]; then
root=nand
kernel=nand
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$1 = xnor ]; then
root=nor
kernel=nor
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xnand ]; then
bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
elif [ x$root = xnor ]; then
bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
fi
bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;imx_nand:$nand_parts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
elif [ $kernel = nor ]; then
bootm /dev/nor0.kernel
else
bootm /dev/nand0.kernel.bb
fi

37
board/pcm037/env/bin/init vendored
View File

@ -1,37 +0,0 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
if [ -e /dev/nor0 ]; then
addpart /dev/nor0 $nor_parts
fi
if [ -e /dev/nand0 ]; then
addpart /dev/nand0 $nand_parts
# Uh, oh, hush first expands wildcards and then starts executing
# commands. What a bug!
source /env/bin/hush_hack
fi
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
done
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
fi
echo
echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
echo
exit
fi
boot

16
board/pcm037/env/bin/update_root vendored
View File

@ -1,16 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.root.bb
elif [ x$1 = xnor ]; then
part=/dev/nor0.root
else
echo "usage: $0 nor|nand [imagename]"
exit 1
fi
. /env/bin/_update $2

62
board/pcm037/env/config vendored
View File

@ -1,24 +1,11 @@
#!/bin/sh
# can be either 'net', 'nor' or 'nand''
kernel=net
root=net
uimage=uImage-pcm037
jffs2=root-pcm037.jffs2
autoboot_timeout=3
nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
bootargs="console=ttymxc0,115200"
nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
rootpart_nor="/dev/mtdblock3"
nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
rootpart_nand="/dev/mtdblock7"
machine=pcm037
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
@ -26,3 +13,44 @@ ip=dhcp
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'net', 'nor' or 'nand'
kernel_loc=net
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nor=3
nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

31
board/pcm037/pcm037.c
View File

@ -33,6 +33,7 @@
#include <asm/armlinux.h>
#include <mach/gpio.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <partition.h>
#include <asm/mach-types.h>
#include <mach/imx-nand.h>
@ -117,6 +118,7 @@ static struct device_d sdram1_dev = {
struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct device_d nand_dev = {
@ -226,8 +228,37 @@ static void pcm037_usb_init(void)
}
#endif
#ifdef CONFIG_MMU
static void pcm037_mmu_init(void)
{
mmu_init();
arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED);
arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED);
setup_dma_coherent(0x10000000);
#if TEXT_BASE & (0x100000 - 1)
#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
#else
arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
#endif
mmu_enable();
#ifdef CONFIG_CACHE_L2X0
l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000);
#endif
}
#else
static void pcm037_mmu_init(void)
{
}
#endif
static int imx31_devices_init(void)
{
pcm037_mmu_init();
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
__REG(CSCR_L(0)) = 0x10000d03;
__REG(CSCR_A(0)) = 0x00720900;

36
board/pcm038/env/bin/_update vendored
View File

@ -1,36 +0,0 @@
#!/bin/sh
if [ -z "$part" -o -z "$image" ]; then
echo "define \$part and \$image"
exit 1
fi
if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
if [ $# = 1 ]; then
image=$1
fi
if [ x$ip = xdhcp ]; then
dhcp
fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
exit 1
fi
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part

47
board/pcm038/env/bin/boot vendored
View File

@ -1,47 +0,0 @@
#!/bin/sh
. /env/config
if [ x$1 = xnand ]; then
root=nand
kernel=nand
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$1 = xnor ]; then
root=nor
kernel=nor
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xnand ]; then
bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
elif [ x$root = xnor ]; then
bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
fi
bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;imx_nand:$nand_parts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
elif [ $kernel = nor ]; then
bootm /dev/nor0.kernel
else
bootm /dev/nand0.kernel.bb
fi

15
board/pcm038/env/bin/update_kernel vendored
View File

@ -1,15 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.kernel.bb
elif [ x$1 = xnor ]; then
part=/dev/nor0.kernel
else
echo "usage: $0 nor|nand [imagename]"
exit 1
fi
. /env/bin/_update $2

16
board/pcm038/env/bin/update_root vendored
View File

@ -1,16 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.root.bb
elif [ x$1 = xnor ]; then
part=/dev/nor0.root
else
echo "usage: $0 nor|nand [imagename]"
exit 1
fi
. /env/bin/_update $2

62
board/pcm038/env/config vendored
View File

@ -1,24 +1,11 @@
#!/bin/sh
# can be either 'net', 'nor' or 'nand''
kernel=net
root=net
uimage=uImage-pcm038
jffs2=root-pcm038.jffs2
autoboot_timeout=3
nfsroot="/ptx/work/octopus/rsc/svn/oselas/bsp/phytec/phyCORE-i.MX27/OSELAS.BSP-Phytec-phyCORE-i.MX27-trunk/root"
bootargs="console=ttymxc0,115200"
nor_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
rootpart_nor="/dev/mtdblock3"
nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
rootpart_nand="/dev/mtdblock7"
machine=pcm038
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
@ -26,3 +13,44 @@ ip=dhcp
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'net', 'nor' or 'nand'
kernel_loc=net
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nor=3
nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

3
board/pcm038/pcm038.c
View File

@ -42,6 +42,7 @@
#include <asm/mmu.h>
#include <usb/isp1504.h>
#include <mach/spi.h>
#include <mach/iomux-mx27.h>
static struct device_d cfi_dev = {
.name = "cfi_flash",
@ -229,7 +230,7 @@ static int pcm038_devices_init(void)
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,

36
board/pcm043/env/bin/_update vendored
View File

@ -1,36 +0,0 @@
#!/bin/sh
if [ -z "$part" -o -z "$image" ]; then
echo "define \$part and \$image"
exit 1
fi
if [ ! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
if [ $# = 1 ]; then
image=$1
fi
if [ x$ip = xdhcp ]; then
dhcp
fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
exit 1
fi
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part

47
board/pcm043/env/bin/boot vendored
View File

@ -1,47 +0,0 @@
#!/bin/sh
. /env/config
if [ x$1 = xnand ]; then
root=nand
kernel=nand
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$1 = xnor ]; then
root=nor
kernel=nor
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xnand ]; then
bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
elif [ x$root = xnor ]; then
bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
fi
bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
elif [ $kernel = nor ]; then
bootm /dev/nor0.kernel
else
bootm /dev/nand0.kernel.bb
fi

1
board/pcm043/env/bin/hush_hack vendored
View File

@ -1 +0,0 @@
nand -a /dev/nand0.*

15
board/pcm043/env/bin/update_kernel vendored
View File

@ -1,15 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.kernel.bb
elif [ x$1 = xnor ]; then
part=/dev/nor0.kernel
else
echo "usage: $0 nor|nand [imagename]"
exit 1
fi
. /env/bin/_update $2

69
board/pcm043/env/config vendored
View File

@ -1,29 +1,58 @@
#!/bin/sh
# can be either 'net', 'nor' or 'nand''
kernel=nor
root=nor
uimage=uImage-pcm043
jffs2=root-pcm043.jffs2
autoboot_timeout=3
nfsroot="/path/to/nfs_root"
bootargs="console=ttymxc0,115200"
nor_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)"
rootpart_nor="/dev/mtdblock3"
nand_parts="256k(barebox)ro,128k(bareboxenv),2048k(kernel),-(root)"
rootpart_nand="/dev/mtdblock3"
machine=pcm043
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
eth0.ipaddr=192.168.3.11
eth0.netmask=255.255.255.0
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=192.168.3.10
#eth0.ethaddr=aa.bb.cc.dd.ee.ff
#eth0.serverip=a.b.c.d
# can be either 'net', 'nor' or 'nand'
kernel_loc=net
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW"
nor_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nor=3
nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

40
board/phycard-i.MX27/env/bin/boot vendored
View File

@ -1,40 +0,0 @@
#!/bin/sh
. /env/config
if [ x$1 = xnand ]; then
root=nand
kernel=nand
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xnand ]; then
bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
fi
bootargs="$bootargs mtdparts=mxc_nand:$nand_parts"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage || exit 1
bootm uImage
elif [ $kernel = nor ]; then
bootm /dev/nor0.kernel
else
bootm /dev/nand0.kernel.bb
fi

1
board/phycard-i.MX27/env/bin/hush_hack vendored
View File

@ -1 +0,0 @@
nand -a /dev/nand0.*

37
board/phycard-i.MX27/env/bin/init vendored
View File

@ -1,37 +0,0 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
if [ -e /dev/nor0 ]; then
addpart /dev/nor0 $nor_parts
fi
if [ -e /dev/nand0 ]; then
addpart /dev/nand0 $nand_parts
# Uh, oh, hush first expands wildcards and then starts executing
# commands. What a bug!
source /env/bin/hush_hack
fi
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
done
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
fi
echo
echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
echo
exit
fi
boot

15
board/phycard-i.MX27/env/bin/update_kernel vendored
View File

@ -1,15 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.kernel.bb
elif [ x$1 = xnor ]; then
part=/dev/nor0.kernel
else
echo "usage: $0 nor|nand [imagename]"
exit 1
fi
. /env/bin/_update $2

16
board/phycard-i.MX27/env/bin/update_root vendored
View File

@ -1,16 +0,0 @@
#!/bin/sh
. /env/config
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.root.bb
elif [ x$1 = xnor ]; then
part=/dev/nor0.root
else
echo "usage: $0 nor|nand [imagename]"
exit 1
fi
. /env/bin/_update $2

57
board/phycard-i.MX27/env/config vendored
View File

@ -1,21 +1,11 @@
#!/bin/sh
# can be either 'net', 'nor' or 'nand''
kernel=net
root=net
uimage=uImage-pca100
jffs2=root-pca100.jffs2
autoboot_timeout=3
nfsroot="/tmp/root"
bootargs="console=ttymxc0,115200"
nand_parts="256k(barebox)ro,128k(bareboxenv),1536k(kernel),-(root)"
rootpart_nand="/dev/mtdblock3"
machine=pca100
eth0.serverip=
user=
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
@ -23,3 +13,42 @@ ip=dhcp
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'net', 'nor' or 'nand'
kernel_loc=net
# can be either 'net', 'nor', 'nand' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root-$machine.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
kernelimage_type=zimage
kernelimage=zImage-$machine
#kernelimage_type=uimage
#kernelimage=uImage-$machine
#kernelimage_type=raw
#kernelimage=Image-$machine
#kernelimage_type=raw_lzo
#kernelimage=Image-$machine.lzo
if [ -n $user ]; then
kernelimage="$user"-"$kernelimage"
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
rootfsimage="$user"-"$rootfsimage"
else
nfsroot="$eth0.serverip:/path/to/nfs/root"
fi
autoboot_timeout=3
bootargs="console=ttymxc0,115200"
nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)"
rootfs_mtdblock_nand=7
# set a fancy prompt (if support is compiled in)
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "

3
board/phycard-i.MX27/pca100.c
View File

@ -38,6 +38,7 @@
#include <gpio.h>
#include <asm/mmu.h>
#include <usb/isp1504.h>
#include <mach/iomux-mx27.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
@ -147,7 +148,7 @@ static int pca100_devices_init(void)
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,

2
commands/loadb.c
View File

@ -724,7 +724,7 @@ static int do_load_serial_bin(struct command *cmdtp, int argc, char *argv[])
printf("%s:No console device with STDIN and STDOUT\n", argv[0]);
return -ENODEV;
}
current_baudrate = simple_strtoul(cdev->baudrate_string, NULL, 10);
current_baudrate = (int)simple_strtoul(dev_get_param(cdev->dev, "baudrate"), NULL, 10);
/* Load Defaults */
if (load_baudrate == 0)

32
commands/mem.c
View File

@ -455,27 +455,35 @@ static int do_mem_cp(struct command *cmdtp, int argc, char *argv[])
}
while (count > 0) {
int now, r, w;
int now, r, w, tmp;
now = min(RW_BUF_SIZE, count);
if ((r = read(sourcefd, rw_buf, now)) < 0) {
r = read(sourcefd, rw_buf, now);
if (r < 0) {
perror("read");
goto out;
}
if ((w = write(destfd, rw_buf, r)) < 0) {
perror("write");
goto out;
if (!r)
break;
tmp = 0;
now = r;
while (now) {
w = write(destfd, rw_buf + tmp, now);
if (w < 0) {
perror("write");
goto out;
}
if (!w)
break;
now -= w;
tmp += w;
}
if (r < now)
break;
if (w < r)
break;
count -= now;
count -= r;
}
if (count) {

38
commands/net.c
View File

@ -35,44 +35,6 @@
#include <errno.h>
#include <libbb.h>
void netboot_update_env(void)
{
struct eth_device *eth_current = eth_get_current();
char tmp[22];
if (NetOurGatewayIP)
dev_set_param_ip(&eth_current->dev, "gateway", NetOurGatewayIP);
if (NetOurSubnetMask)
dev_set_param_ip(&eth_current->dev, "netmask", NetOurSubnetMask);
if (NetOurHostName[0])
setenv ("hostname", NetOurHostName);
if (NetOurRootPath[0])
setenv ("rootpath", NetOurRootPath);
if (NetOurIP)
dev_set_param_ip(&eth_current->dev, "ipaddr", NetOurIP);
if (NetServerIP)
dev_set_param_ip(&eth_current->dev, "serverip", NetServerIP);
if (NetOurDNSIP) {
ip_to_string (NetOurDNSIP, tmp);
setenv ("dnsip", tmp);
}
#ifdef CONFIG_BOOTP_DNS2
if (NetOurDNS2IP) {
ip_to_string (NetOurDNS2IP, tmp);
setenv ("dnsip2", tmp);
}
#endif
if (NetOurNISDomain[0])
setenv ("domain", NetOurNISDomain);
}
#ifdef CONFIG_NET_RARP
extern void RarpRequest(void);

4
common/Kconfig
View File

@ -339,8 +339,8 @@ config DEFAULT_ENVIRONMENT_PATH
depends on DEFAULT_ENVIRONMENT
prompt "Default environment path"
help
The path the default environment will be taken from. Relative
pathes will be relative to the barebox Toplevel dir, but absolute
Space separated list of pathes the default environment will be taken from.
Relative pathes will be relative to the barebox Toplevel dir, but absolute
pathes are fine aswell.
endmenu

5
common/Makefile
View File

@ -22,9 +22,10 @@ ifdef CONFIG_DEFAULT_ENVIRONMENT
$(obj)/startup.o: include/barebox_default_env.h
$(obj)/env.o: include/barebox_default_env.h
ENV_FILES := $(shell find $(srctree)/$(CONFIG_DEFAULT_ENVIRONMENT_PATH))
ENV_FILES := $(shell cd $(srctree); for i in $(CONFIG_DEFAULT_ENVIRONMENT_PATH); do find $${i} -type f -exec readlink -f {} \;; done)
endif # ifdef CONFIG_DEFAULT_ENVIRONMENT
include/barebox_default_env.h: $(ENV_FILES)
$(Q)scripts/bareboxenv -s $(srctree)/$(CONFIG_DEFAULT_ENVIRONMENT_PATH) barebox_default_env
$(Q)scripts/genenv $(srctree) $(CONFIG_DEFAULT_ENVIRONMENT_PATH)
$(Q)cat barebox_default_env | scripts/bin2c default_environment > $@

40
common/console.c
View File

@ -57,26 +57,32 @@ static int console_std_set(struct device_d *dev, struct param_d *param,
const char *val)
{
struct console_device *cdev = dev->type_data;
char active[4];
unsigned int flag = 0, i = 0;
if (!val)
dev_param_set_generic(dev, param, NULL);
if (strchr(val, 'i') && cdev->f_caps & CONSOLE_STDIN) {
cdev->active[i++] = 'i';
active[i++] = 'i';
flag |= CONSOLE_STDIN;
}
if (strchr(val, 'o') && cdev->f_caps & CONSOLE_STDOUT) {
cdev->active[i++] = 'o';
active[i++] = 'o';
flag |= CONSOLE_STDOUT;
}
if (strchr(val, 'e') && cdev->f_caps & CONSOLE_STDERR) {
cdev->active[i++] = 'e';
active[i++] = 'e';
flag |= CONSOLE_STDERR;
}
cdev->active[i] = 0;
active[i] = 0;
cdev->f_active = flag;
dev_param_set_generic(dev, param, active);
return 0;
}
@ -85,8 +91,12 @@ static int console_baudrate_set(struct device_d *dev, struct param_d *param,
{
struct console_device *cdev = dev->type_data;
int baudrate;
char baudstr[16];
unsigned char c;
if (!val)
dev_param_set_generic(dev, param, NULL);
baudrate = simple_strtoul(val, NULL, 10);
if (cdev->f_active) {
@ -101,7 +111,8 @@ static int console_baudrate_set(struct device_d *dev, struct param_d *param,
} else
cdev->setbrg(cdev, baudrate);
sprintf(cdev->baudrate_string, "%d", baudrate);
sprintf(baudstr, "%d", baudrate);
dev_param_set_generic(dev, param, baudstr);
return 0;
}
@ -129,29 +140,20 @@ int console_register(struct console_device *newcdev)
register_device(dev);
if (newcdev->setbrg) {
newcdev->baudrate_param.set = console_baudrate_set;
newcdev->baudrate_param.name = "baudrate";
sprintf(newcdev->baudrate_string, "%d",
CONFIG_BAUDRATE);
console_baudrate_set(dev, &newcdev->baudrate_param,
newcdev->baudrate_string);
newcdev->baudrate_param.value = newcdev->baudrate_string;
dev_add_param(dev, &newcdev->baudrate_param);
dev_add_param(dev, "baudrate", console_baudrate_set, NULL, 0);
dev_set_param(dev, "baudrate", "115200");
}
newcdev->active_param.set = console_std_set;
newcdev->active_param.name = "active";
newcdev->active_param.value = newcdev->active;
dev_add_param(dev, &newcdev->active_param);
dev_add_param(dev, "active", console_std_set, NULL, 0);
initialized = CONSOLE_INIT_FULL;
#ifdef CONFIG_CONSOLE_ACTIVATE_ALL
console_std_set(dev, &newcdev->active_param, "ioe");
dev_set_param(dev, "active", "ioe");
#endif
#ifdef CONFIG_CONSOLE_ACTIVATE_FIRST
if (list_empty(&console_list)) {
first = 1;
console_std_set(dev, &newcdev->active_param, "ioe");
dev_set_param(dev, "active", "ioe");
}
#endif

7
common/misc.c
View File

@ -56,6 +56,10 @@ const char *strerror(int errnum)
case ENAMETOOLONG : str = "File name too long"; break;
case ENOSYS : str = "Function not implemented"; break;
case ENOTEMPTY : str = "Directory not empty"; break;
case EHOSTUNREACH : str = "No route to host"; break;
case EINTR : str = "Interrupted system call"; break;
case ENETUNREACH : str = "Network is unreachable"; break;
case ENETDOWN : str = "Network is down"; break;
#if 0 /* These are probably not needed */
case ENOTBLK : str = "Block device required"; break;
case EFBIG : str = "File too large"; break;
@ -79,8 +83,6 @@ const char *strerror(int errnum)
case EAFNOSUPPORT : str = "Address family not supported by protocol"; break;
case EADDRINUSE : str = "Address already in use"; break;
case EADDRNOTAVAIL : str = "Cannot assign requested address"; break;
case ENETDOWN : str = "Network is down"; break;
case ENETUNREACH : str = "Network is unreachable"; break;
case ENETRESET : str = "Network dropped connection because of reset"; break;
case ECONNABORTED : str = "Software caused connection abort"; break;
case ECONNRESET : str = "Connection reset by peer"; break;
@ -88,7 +90,6 @@ const char *strerror(int errnum)
case ETIMEDOUT : str = "Connection timed out"; break;
case ECONNREFUSED : str = "Connection refused"; break;
case EHOSTDOWN : str = "Host is down"; break;
case EHOSTUNREACH : str = "No route to host"; break;
case EALREADY : str = "Operation already in progress"; break;
case EINPROGRESS : str = "Operation now in progress"; break;
case ESTALE : str = "Stale NFS file handle"; break;

5
board/phycard-i.MX27/env/bin/_update → defaultenv/bin/_update
View File

@ -20,7 +20,7 @@ fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
echo "Server did not reply! Update aborted."
exit 1
fi
@ -28,9 +28,12 @@ unprotect $part
echo
echo "erasing partition $part"
echo
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part
protect $part

109
defaultenv/bin/boot Normal file
View File

@ -0,0 +1,109 @@
#!/bin/sh
. /env/config
if [ x$1 = xnand ]; then
rootfs_loc=nand
kernel_loc=nand
elif [ x$1 = xnor ]; then
rootfs_loc=nor
kernel_loc=nor
elif [ x$1 = xnet ]; then
rootfs_loc=net
kernel_loc=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
elif [ x$ip = xnone ]; then
bootargs="ip=none"
else
bootargs="$bootargs ip=$eth0.ipaddr::$eth0.gateway:$eth0.netmask:::"
fi
if [ x$rootfs_loc = xnet ]; then
bootargs="$bootargs root=/dev/nfs nfsroot=$nfsroot,v3,tcp noinitrd"
elif [ x$rootfs_loc = xinitrd ]; then
bootargs="$bootargs root=/dev/ram0 rdinit=/sbin/init"
else
if [ x$rootfs_loc = xnand ]; then
rootfs_mtdblock=$rootfs_mtdblock_nand
else
rootfs_mtdblock=$rootfs_mtdblock_nor
fi
if [ x$rootfs_type = xubifs ]; then
bootargs="$bootargs root=ubi0:root ubi.mtd=$rootfs_mtdblock"
else
bootargs="$bootargs root=/dev/mtdblock$rootfs_mtdblock"
fi
bootargs="$bootargs rootfstype=$rootfs_type noinitrd"
fi
if [ -n $nor_parts ]; then
mtdparts="${mtdparts}physmap-flash.o:${nor_parts};"
fi
if [ -n $nand_parts ]; then
mtdparts="${mtdparts}$nand_device:${nor_parts};"
fi
if [ -n $mtdparts ]; then
bootargs="${bootargs} mtdparts=\"${mtdparts}\""
fi
if [ ! -e /dev/ram0.kernelraw ]; then
# arm raw kernel images are usually located at sdram start + 0x8000
addpart dev/ram0 8M@0x8000(kernelraw)
fi
if [ ! -e /dev/ram0.kernel ]; then
# Here we can safely put the kernel without risking of overwriting it
# while extracting
addpart dev/ram0 8M(kernel)
fi
if [ x$kernel_loc = xnet ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
if [ $kernelimage_type = uimage ]; then
netload="/dev/ram0.kernel"
elif [ $kernelimage_type = zimage ]; then
netload="/dev/ram0.kernel"
elif [ $kernelimage_type = raw ]; then
netload="/dev/ram0.kernelraw"
elif [ $kernelimage_type = raw_lzo ]; then
netload="/dev/ram0.kernel"
else
echo "error: set kernelimage_type to one of 'uimage', 'zimage', 'raw' or 'raw_lzo'"
exit 1
fi
tftp $kernelimage $netload || exit 1
kdev="$netload"
elif [ x$kernel_loc = xnor ]; then
kdev="/dev/nor0.kernel"
elif [ x$kernel_loc = xnand ]; then
kdev="/dev/nand0.kernel.bb"
else
echo "error: set kernel_loc to one of 'net', 'nand' or 'nor'"
exit 1
fi
echo "booting kernel of type $kernelimage_type from $kdev"
if [ x$kernelimage_type = xuimage ]; then
bootm $kdev
elif [ x$kernelimage_type = xzimage ]; then
bootz $kdev
elif [ x$kernelimage_type = xraw ]; then
if [ $kernel_loc != net ]; then
cp $kdev /dev/ram0.kernelraw
fi
bootu /dev/ram0.kernelraw
elif [ x$kernelimage_type = xraw_lzo ]; then
unlzo $kdev /dev/ram0.kernelraw
bootu /dev/ram0.kernelraw
fi

0
board/pcm038/env/bin/hush_hack → defaultenv/bin/hush_hack
View File

11
board/pcm038/env/bin/init → defaultenv/bin/init
View File

@ -13,14 +13,11 @@ if [ -e /dev/nand0 ]; then
# Uh, oh, hush first expands wildcards and then starts executing
# commands. What a bug!
source /env/bin/hush_hack
source /env/bin/hush_hack
fi
if [ -z $eth0.ethaddr ]; then
while [ -z $eth0.ethaddr ]; do
readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
done
echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
if [ -f /env/bin/init_board ]; then
/env/bin/init_board
fi
echo
@ -29,7 +26,7 @@ timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel nand|nor [<imagename>] to update kernel into flash"
echo "type update_root nand|nor [<imagename>] to update rootfs into flash"
echo "type update_rootfs nand|nor [<imagename>] to update rootfs into flash"
echo
exit
fi

2
board/pcm037/env/bin/update_kernel → defaultenv/bin/update_kernel
View File

@ -1,8 +1,8 @@
#!/bin/sh
. /env/config
image=$kernelimage
image=$uimage
if [ x$1 = xnand ]; then
part=/dev/nand0.kernel.bb
elif [ x$1 = xnor ]; then

4
board/pcm043/env/bin/update_root → defaultenv/bin/update_rootfs
View File

@ -2,7 +2,8 @@
. /env/config
image=$uimage
image=$rootfsimage
if [ x$1 = xnand ]; then
part=/dev/nand0.root.bb
elif [ x$1 = xnor ]; then
@ -13,4 +14,3 @@ else
fi
. /env/bin/_update $2

3
drivers/i2c/Kconfig
View File

@ -10,6 +10,9 @@ config DRIVER_I2C_IMX
config DRIVER_I2C_MC13892
bool "MC13892 a.k.a. PMIC driver"
config DRIVER_I2C_MC34704
bool "MC34704 PMIC driver"
config DRIVER_I2C_MC9SDZ60
bool "MC9SDZ60 driver"

1
drivers/i2c/Makefile
View File

@ -3,5 +3,6 @@ obj-$(CONFIG_I2C) += i2c.o
obj-$(CONFIG_DRIVER_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_DRIVER_I2C_MC13892) += mc13892.o
obj-$(CONFIG_DRIVER_I2C_MC34704) += mc34704.o
obj-$(CONFIG_DRIVER_I2C_MC9SDZ60) += mc9sdz60.o
obj-$(CONFIG_DRIVER_I2C_LP3972) += lp3972.o

140
drivers/i2c/mc34704.c Normal file
View File

@ -0,0 +1,140 @@
/*
* Copyright (C) 2007 Sascha Hauer, Pengutronix
* 2009 Marc Kleine-Budde <mkl@pengutronix.de>
* Copyright (C) 2010 Baruch Siach <baruch@tkos.co.il>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <init.h>
#include <driver.h>
#include <xfuncs.h>
#include <errno.h>
#include <i2c/i2c.h>
#include <i2c/mc34704.h>
#define DRIVERNAME "mc34704"
#define to_mc34704(a) container_of(a, struct mc34704, cdev)
static struct mc34704 *mc34704_dev;
struct mc34704 *mc34704_get(void)
{
if (!mc34704_dev)
return NULL;
return mc34704_dev;
}
EXPORT_SYMBOL(mc34704_get);
int mc34704_reg_read(struct mc34704 *mc34704, u8 reg, u8 *val)
{
int ret;
ret = i2c_read_reg(mc34704->client, reg, val, 1);
return ret == 1 ? 0 : ret;
}
EXPORT_SYMBOL(mc34704_reg_read)
int mc34704_reg_write(struct mc34704 *mc34704, u8 reg, u8 val)
{
int ret;
ret = i2c_write_reg(mc34704->client, reg, &val, 1);
return ret == 1 ? 0 : ret;
}
EXPORT_SYMBOL(mc34704_reg_write)
static ssize_t mc34704_read(struct cdev *cdev, void *_buf, size_t count,
ulong offset, ulong flags)
{
struct mc34704 *priv = to_mc34704(cdev);
u8 *buf = _buf;
size_t i = count;
int err;
while (i) {
err = mc34704_reg_read(priv, offset, buf);
if (err)
return (ssize_t)err;
buf++;
i--;
offset++;
}
return count;
}
static ssize_t mc34704_write(struct cdev *cdev, const void *_buf, size_t count,
ulong offset, ulong flags)
{
struct mc34704 *mc34704 = to_mc34704(cdev);
const u8 *buf = _buf;
size_t i = count;
int err;
while (i) {
err = mc34704_reg_write(mc34704, offset, *buf);
if (err)
return (ssize_t)err;
buf++;
i--;
offset++;
}
return count;
}
static struct file_operations mc34704_fops = {
.lseek = dev_lseek_default,
.read = mc34704_read,
.write = mc34704_write,
};
static int mc34704_probe(struct device_d *dev)
{
if (mc34704_dev)
return -EBUSY;
mc34704_dev = xzalloc(sizeof(struct mc34704));
mc34704_dev->cdev.name = DRIVERNAME;
mc34704_dev->client = to_i2c_client(dev);
mc34704_dev->cdev.size = 256;
mc34704_dev->cdev.dev = dev;
mc34704_dev->cdev.ops = &mc34704_fops;
devfs_create(&mc34704_dev->cdev);
return 0;
}
static struct driver_d mc34704_driver = {
.name = DRIVERNAME,
.probe = mc34704_probe,
};
static int mc34704_init(void)
{
register_driver(&mc34704_driver);
return 0;
}
device_initcall(mc34704_init);

7
drivers/nand/nand.c
View File

@ -210,6 +210,7 @@ static struct file_operations nand_ops_oob = {
int add_mtd_device(struct mtd_info *mtd)
{
struct nand_chip *chip = mtd->priv;
char str[16];
strcpy(mtd->class_dev.name, "nand");
register_device(&mtd->class_dev);
@ -220,10 +221,8 @@ int add_mtd_device(struct mtd_info *mtd)
mtd->cdev.priv = mtd;
mtd->cdev.dev = &mtd->class_dev;
mtd->param_size.flags = PARAM_FLAG_RO;
mtd->param_size.name = "size";
mtd->param_size.value = asprintf("%u", mtd->size);
dev_add_param(&mtd->class_dev, &mtd->param_size);
sprintf(str, "%u", mtd->size);
dev_add_param_fixed(&mtd->class_dev, "size", str);
devfs_create(&mtd->cdev);

2
drivers/net/at91_ether.c
View File

@ -190,7 +190,7 @@ static int at91rm9200_eth_rx (struct eth_device *edev)
return 0;
size = rbfp->size & RBF_SIZE;
NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
net_receive((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
rbfp->addr &= ~RBF_OWNER;
if (rbfp->addr & RBF_WRAP)

2
drivers/net/cs8900.c
View File

@ -309,7 +309,7 @@ static int cs8900_recv(struct eth_device *dev)
if (len & 1) {
*addr++ = readw(priv->regs + CS8900_RTDATA0);
}
NetReceive(NetRxPackets[0], len);
net_receive(NetRxPackets[0], len);
return len;
}

2
drivers/net/dm9000.c
View File

@ -416,7 +416,7 @@ static int dm9000_eth_rx (struct eth_device *edev)
/* Pass to upper layer */
debug("passing packet to upper layer\n");
NetReceive(NetRxPackets[0], RxLen);
net_receive(NetRxPackets[0], RxLen);
return RxLen;
}
return 0;

4
drivers/net/ep93xx.c
View File

@ -335,9 +335,9 @@ static int ep93xx_eth_rcv_packet(struct eth_device *edev)
* protocol stack. We track the total number of
* bytes in the frame (nbytes_frame) which will be
* used when we pass the data off to the protocol
* layer via NetReceive().
* layer via net_receive().
*/
NetReceive((uchar *)priv->rx_dq.current->word1,
net_receive((uchar *)priv->rx_dq.current->word1,
RX_STATUS_FRAME_LEN(priv->rx_sq.current));
pr_debug("reporting %d bytes...\n",
RX_STATUS_FRAME_LEN(priv->rx_sq.current));

2
drivers/net/fec_imx.c
View File

@ -515,7 +515,7 @@ static int fec_recv(struct eth_device *dev)
*/
frame = phys_to_virt(readl(&rbd->data_pointer));
frame_length = readw(&rbd->data_length) - 4;
NetReceive(frame->data, frame_length);
net_receive(frame->data, frame_length);
len = frame_length;
} else {
if (bd_status & FEC_RBD_ERR) {

2
drivers/net/fec_mpc5200.c
View File

@ -645,7 +645,7 @@ static int mpc5xxx_fec_recv(struct eth_device *dev)
*/
memcpy(buff, frame->head, 14);
memcpy(buff + 14, frame->data, frame_length);
NetReceive(buff, frame_length);
net_receive(buff, frame_length);
len = frame_length;
}
/*

2
drivers/net/macb.c
View File

@ -190,7 +190,7 @@ static int macb_recv(struct eth_device *edev)
buffer = (void *)NetRxPackets[0];
}
NetReceive(buffer, length);
net_receive(buffer, length);
if (++rx_tail >= CFG_MACB_RX_RING_SIZE)
rx_tail = 0;
reclaim_rx_buffers(macb, rx_tail);

2
drivers/net/netx_eth.c
View File

@ -111,7 +111,7 @@ static int netx_eth_rx (struct eth_device *edev)
/* get data */
memcpy((void*)NetRxPackets[0], (void *)(SRAM_BASE(seg) + frameno * 1560), len);
/* pass to barebox */
NetReceive(NetRxPackets[0], len);
net_receive(NetRxPackets[0], len);
PFIFO_REG(PFIFO_BASE(EMPTY_PTR_FIFO(xcno))) =
FIFO_PTR_SEGMENT(seg) |

2
drivers/net/smc91111.c
View File

@ -1156,7 +1156,7 @@ static int smc91c111_eth_rx(struct eth_device *edev)
if (!is_error) {
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[0], packet_length);
net_receive(NetRxPackets[0], packet_length);
return packet_length;
}

2
drivers/net/smc911x.c
View File

@ -668,7 +668,7 @@ static int smc911x_eth_rx(struct eth_device *edev)
": dropped bad packet. Status: 0x%08x\n",
status);
else
NetReceive(NetRxPackets[0], pktlen);
net_receive(NetRxPackets[0], pktlen);
}
return 0;

2
drivers/net/tap.c
View File

@ -48,7 +48,7 @@ int tap_eth_rx (struct eth_device *edev)
length = linux_read_nonblock(priv->fd, NetRxPackets[0], PKTSIZE);
if (length > 0)
NetReceive(NetRxPackets[0], length);
net_receive(NetRxPackets[0], length);
return 0;
}

14
drivers/net/usb/asix.c
View File

@ -415,17 +415,17 @@ static int asix_rx_fixup(struct usbnet *dev, void *buf, int len)
while (len > 0) {
if ((short)(header & 0x0000ffff) != ~((short)((header & 0xffff0000) >> 16)))
dev_err(&dev->dev, "asix_rx_fixup() Bad Header Length");
dev_err(&dev->edev.dev, "asix_rx_fixup() Bad Header Length");
/* get the packet length */
size = (unsigned short) (header & 0x0000ffff);
if (size > 1514) {
dev_err(&dev->dev, "asix_rx_fixup() Bad RX Length %d", size);
dev_err(&dev->edev.dev, "asix_rx_fixup() Bad RX Length %d", size);
return 0;
}
NetReceive(buf, size);
net_receive(buf, size);
buf += ((size + 1) & 0xfffe);
len -= ((size + 1) & 0xfffe);
@ -440,7 +440,7 @@ static int asix_rx_fixup(struct usbnet *dev, void *buf, int len)
}
if (len < 0) {
dev_err(&dev->dev,"asix_rx_fixup() Bad SKB Length %d", len);
dev_err(&dev->edev.dev,"asix_rx_fixup() Bad SKB Length %d", len);
return -1;
}
return 0;
@ -503,13 +503,13 @@ static int ax88172_bind(struct usbnet *dev)
unsigned long gpio_bits = dev->driver_info->data;
struct asix_data *data = (struct asix_data *)&dev->data;
dev_dbg(&dev->dev, "%s\n", __func__);
dev_dbg(&dev->edev.dev, "%s\n", __func__);
data->eeprom_len = AX88172_EEPROM_LEN;
ret = usbnet_get_endpoints(dev);
if (ret) {
dev_err(&dev->dev, "can not get EPs\n");
dev_err(&dev->edev.dev, "can not get EPs\n");
return ret;
}

11
drivers/net/usb/usbnet.c
View File

@ -74,7 +74,7 @@ int usbnet_get_endpoints(struct usbnet *dev)
in->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
dev->out = usb_sndbulkpipe (dev->udev,
out->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
dev_dbg(&dev->dev, "found endpoints: IN=%d OUT=%d\n",
dev_dbg(&dev->edev.dev, "found endpoints: IN=%d OUT=%d\n",
in->bEndpointAddress, out->bEndpointAddress);
return 0;
@ -89,14 +89,14 @@ static int usbnet_send(struct eth_device *edev, void *eth_data, int data_length)
struct driver_info *info = dev->driver_info;
int len, alen, ret;
dev_dbg(&dev->dev, "%s\n",__func__);
dev_dbg(&edev->dev, "%s\n",__func__);
/* some devices want funky USB-level framing, for
* win32 driver (usually) and/or hardware quirks
*/
if(info->tx_fixup) {
if(info->tx_fixup(dev, eth_data, data_length, tx_buffer, &len)) {
dev_dbg(&dev->dev, "can't tx_fixup packet");
dev_dbg(&edev->dev, "can't tx_fixup packet");
return 0;
}
} else {
@ -137,7 +137,7 @@ static int usbnet_recv(struct eth_device *edev)
if (info->rx_fixup)
return info->rx_fixup(dev, rx_buf, alen);
else
NetReceive(rx_buf, alen);
net_receive(rx_buf, alen);
}
return 0;
@ -191,7 +191,7 @@ int usbnet_probe(struct usb_device *usbdev, const struct usb_device_id *prod)
struct driver_info *info;
int status;
dev_dbg(&edev->dev, "%s\n", __func__);
dev_dbg(&usbdev->dev, "%s\n", __func__);
undev = xzalloc(sizeof (*undev));
@ -206,6 +206,7 @@ int usbnet_probe(struct usb_device *usbdev, const struct usb_device_id *prod)
edev->recv = usbnet_recv,
edev->halt = usbnet_halt,
edev->priv = undev;
edev->dev = usbdev->dev; /* will be overwritten by eth_register */
info = (struct driver_info *)prod->driver_info;
undev->driver_info = info;

5
drivers/nor/cfi_flash.c
View File

@ -42,6 +42,7 @@
#include <malloc.h>
#include <asm/io.h>
#include <errno.h>
#include <progress.h>
#include "cfi_flash.h"
/*
@ -499,11 +500,13 @@ static int cfi_erase(struct cdev *cdev, size_t count, unsigned long offset)
start = find_sector(finfo, cdev->dev->map_base + offset);
end = find_sector(finfo, cdev->dev->map_base + offset + count - 1);
init_progression_bar(end - start);
for (i = start; i <= end; i++) {
ret = finfo->cfi_cmd_set->flash_erase_one(finfo, i);
if (ret)
goto out;
printf(".");
show_progress(i - start);
}
out:
putchar('\n');

135
drivers/serial/serial_imx.c
View File

@ -24,34 +24,35 @@
#include <init.h>
#include <malloc.h>
#include <notifier.h>
#include <asm/io.h>
#define URXD0(base) __REG( 0x0 +(base)) /* Receiver Register */
#define URTX0(base) __REG( 0x40 +(base)) /* Transmitter Register */
#define UCR1(base) __REG( 0x80 +(base)) /* Control Register 1 */
#define UCR2(base) __REG( 0x84 +(base)) /* Control Register 2 */
#define UCR3(base) __REG( 0x88 +(base)) /* Control Register 3 */
#define UCR4(base) __REG( 0x8c +(base)) /* Control Register 4 */
#define UFCR(base) __REG( 0x90 +(base)) /* FIFO Control Register */
#define USR1(base) __REG( 0x94 +(base)) /* Status Register 1 */
#define USR2(base) __REG( 0x98 +(base)) /* Status Register 2 */
#define UESC(base) __REG( 0x9c +(base)) /* Escape Character Register */
#define UTIM(base) __REG( 0xa0 +(base)) /* Escape Timer Register */
#define UBIR(base) __REG( 0xa4 +(base)) /* BRM Incremental Register */
#define UBMR(base) __REG( 0xa8 +(base)) /* BRM Modulator Register */
#define UBRC(base) __REG( 0xac +(base)) /* Baud Rate Count Register */
#define URXD0 0x0 /* Receiver Register */
#define URTX0 0x40 /* Transmitter Register */
#define UCR1 0x80 /* Control Register 1 */
#define UCR2 0x84 /* Control Register 2 */
#define UCR3 0x88 /* Control Register 3 */
#define UCR4 0x8c /* Control Register 4 */
#define UFCR 0x90 /* FIFO Control Register */
#define USR1 0x94 /* Status Register 1 */
#define USR2 0x98 /* Status Register 2 */
#define UESC 0x9c /* Escape Character Register */
#define UTIM 0xa0 /* Escape Timer Register */
#define UBIR 0xa4 /* BRM Incremental Register */
#define UBMR 0xa8 /* BRM Modulator Register */
#define UBRC 0xac /* Baud Rate Count Register */
#ifdef CONFIG_ARCH_IMX1
#define BIPR1(base) __REG( 0xb0 +(base)) /* Incremental Preset Register 1 */
#define BIPR2(base) __REG( 0xb4 +(base)) /* Incremental Preset Register 2 */
#define BIPR3(base) __REG( 0xb8 +(base)) /* Incremental Preset Register 3 */
#define BIPR4(base) __REG( 0xbc +(base)) /* Incremental Preset Register 4 */
#define BMPR1(base) __REG( 0xc0 +(base)) /* BRM Modulator Register 1 */
#define BMPR2(base) __REG( 0xc4 +(base)) /* BRM Modulator Register 2 */
#define BMPR3(base) __REG( 0xc8 +(base)) /* BRM Modulator Register 3 */
#define BMPR4(base) __REG( 0xcc +(base)) /* BRM Modulator Register 4 */
#define UTS(base) __REG( 0xd0 +(base)) /* UART Test Register */
#define BIPR1 0xb0 /* Incremental Preset Register 1 */
#define BIPR2 0xb4 /* Incremental Preset Register 2 */
#define BIPR3 0xb8 /* Incremental Preset Register 3 */
#define BIPR4 0xbc /* Incremental Preset Register 4 */
#define BMPR1 0xc0 /* BRM Modulator Register 1 */
#define BMPR2 0xc4 /* BRM Modulator Register 2 */
#define BMPR3 0xc8 /* BRM Modulator Register 3 */
#define BMPR4 0xcc /* BRM Modulator Register 4 */
#define UTS 0xd0 /* UART Test Register */
#else
#define ONEMS(base) __REG( 0xb0 +(base)) /* One Millisecond register */
#define UTS(base) __REG( 0xb4 +(base)) /* UART Test Register */
#define ONEMS 0xb0 /* One Millisecond register */
#define UTS 0xb4 /* UART Test Register */
#endif
/* UART Control Register Bit Fields.*/
@ -175,7 +176,7 @@ static int imx_serial_reffreq(ulong base)
{
ulong rfdiv;
rfdiv = (UFCR(base) >> 7) & 7;
rfdiv = (readl(base + UFCR) >> 7) & 7;
rfdiv = rfdiv < 6 ? 6 - rfdiv : 7;
return imx_get_uartclk() / rfdiv;
@ -190,45 +191,42 @@ static int imx_serial_init_port(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
ulong base = dev->map_base;
uint32_t val;
writel(UCR1_VAL, base + UCR1);
writel(UCR2_WS | UCR2_IRTS, base + UCR2);
writel(UCR3_VAL, base + UCR3);
writel(UCR4_VAL, base + UCR4);
writel(0x0000002B, base + UESC);
writel(0, base + UTIM);
writel(0, base + UBIR);
writel(0, base + UBMR);
writel(0, base + UTS);
UCR1(base) = UCR1_VAL;
UCR2(base) = UCR2_WS | UCR2_IRTS;
UCR3(base) = UCR3_VAL;
UCR4(base) = UCR4_VAL;
UESC(base) = 0x0000002B;
UTIM(base) = 0;
UBIR(base) = 0;
UBMR(base) = 0;
UTS(base) = 0;
/* Configure FIFOs */
UFCR(base) = 0xa81;
writel(0xa81, base + UFCR);
#ifdef ONEMS
ONEMS(base) = imx_serial_reffreq(base) / 1000;
writel(imx_serial_reffreq(base) / 1000, base + ONEMS);
#endif
/* Enable FIFOs */
UCR2(base) |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
val = readl(base + UCR2);
val |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
writel(val, base + UCR2);
/* Clear status flags */
USR2(base) |= USR2_ADET |
USR2_DTRF |
USR2_IDLE |
USR2_IRINT |
USR2_WAKE |
USR2_RTSF |
USR2_BRCD |
USR2_ORE |
USR2_RDR;
val = readl(base + USR2);
val |= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_IRINT | USR2_WAKE |
USR2_RTSF | USR2_BRCD | USR2_ORE | USR2_RDR;
writel(val, base + USR2);
/* Clear status flags */
USR1(base) |= USR1_PARITYERR |
USR1_RTSD |
USR1_ESCF |
USR1_FRAMERR |
USR1_AIRINT |
USR1_AWAKE;
val = readl(base + USR2);
val |= USR1_PARITYERR | USR1_RTSD | USR1_ESCF | USR1_FRAMERR | USR1_AIRINT |
USR1_AWAKE;
writel(val, base + USR2);
return 0;
}
@ -238,9 +236,9 @@ static void imx_serial_putc(struct console_device *cdev, char c)
struct device_d *dev = cdev->dev;
/* Wait for Tx FIFO not full */
while (UTS(dev->map_base) & UTS_TXFULL);
while (readl(dev->map_base + UTS) & UTS_TXFULL);
URTX0(dev->map_base) = c;
writel(c, dev->map_base + URTX0);
}
static int imx_serial_tstc(struct console_device *cdev)
@ -248,7 +246,7 @@ static int imx_serial_tstc(struct console_device *cdev)
struct device_d *dev = cdev->dev;
/* If receive fifo is empty, return false */
if (UTS(dev->map_base) & UTS_RXEMPTY)
if (readl(dev->map_base + UTS) & UTS_RXEMPTY)
return 0;
return 1;
}
@ -258,9 +256,9 @@ static int imx_serial_getc(struct console_device *cdev)
struct device_d *dev = cdev->dev;
unsigned char ch;
while (UTS(dev->map_base) & UTS_RXEMPTY);
while (readl(dev->map_base + UTS) & UTS_RXEMPTY);
ch = URXD0(dev->map_base);
ch = readl(dev->map_base + URXD0);
return ch;
}
@ -269,7 +267,7 @@ static void imx_serial_flush(struct console_device *cdev)
{
struct device_d *dev = cdev->dev;
while (!(USR2(dev->map_base) & USR2_TXDC));
while (!(readl(dev->map_base + USR2) & USR2_TXDC));
}
static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
@ -277,18 +275,22 @@ static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate)
struct device_d *dev = cdev->dev;
struct imx_serial_priv *priv = container_of(cdev,
struct imx_serial_priv, cdev);
uint32_t val;
ulong base = dev->map_base;
ulong ucr1 = UCR1(base);
ulong ucr1 = readl(base + UCR1);
/* disable UART */
UCR1(base) &= ~UCR1_UARTEN;
val = readl(base + UCR1);
val &= ~UCR1_UARTEN;
writel(val, base + UCR1);
/* Set the numerator value minus one of the BRM ratio */
UBIR(base) = (baudrate / 100) - 1;
writel((baudrate / 100) - 1, base + UBIR);
/* Set the denominator value minus one of the BRM ratio */
UBMR(base) = ((imx_serial_reffreq(base) / 1600) - 1);
writel((imx_serial_reffreq(base) / 1600) - 1, base + UBMR);
UCR1(base) = ucr1;
writel(ucr1, base + UCR1);
priv->baudrate = baudrate;
@ -310,6 +312,7 @@ static int imx_serial_probe(struct device_d *dev)
{
struct console_device *cdev;
struct imx_serial_priv *priv;
uint32_t val;
priv = malloc(sizeof(*priv));
cdev = &priv->cdev;
@ -327,7 +330,9 @@ static int imx_serial_probe(struct device_d *dev)
imx_serial_setbaudrate(cdev, 115200);
/* Enable UART */
UCR1(cdev->dev->map_base) |= UCR1_UARTEN;
val = readl(cdev->dev->map_base + UCR1);
val |= UCR1_UARTEN;
writel(val, cdev->dev->map_base + UCR1);
console_register(cdev);
priv->notify.notifier_call = imx_clocksource_clock_change;

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