ARM: i.MX: introduce clk parent rate changes
Let dividers and gates change the parent rates. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -214,7 +214,7 @@ static int imx6_ccm_probe(struct device_d *dev)
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clks[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
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clks[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
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clks[enet_ref] = clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table, 0);
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clks[enet_ref] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
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/* name parent_name reg idx */
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clks[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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@ -4,13 +4,21 @@
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static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_divider(name, parent, reg, shift, width, 0);
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return clk_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT);
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}
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static inline struct clk *imx_clk_divider_table(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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const struct clk_div_table *table)
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{
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return clk_divider_table(name, parent, reg, shift, width, table,
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CLK_SET_RATE_PARENT);
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}
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static inline struct clk *imx_clk_fixed_factor(const char *name,
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const char *parent, unsigned int mult, unsigned int div)
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{
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return clk_fixed_factor(name, parent, mult, div, 0);
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return clk_fixed_factor(name, parent, mult, div, CLK_SET_RATE_PARENT);
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}
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static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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@ -22,7 +30,7 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_gate(name, parent, reg, shift, 0);
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return clk_gate(name, parent, reg, shift, CLK_SET_RATE_PARENT);
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}
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struct clk *imx_clk_pllv1(const char *name, const char *parent,
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