Merge branch 'for-next/tegra'
Conflicts: arch/arm/dts/Makefile images/Makefile
This commit is contained in:
commit
6e30646fa2
|
@ -165,14 +165,16 @@ config ARCH_TEGRA
|
||||||
bool "NVIDIA Tegra"
|
bool "NVIDIA Tegra"
|
||||||
select CPU_V7
|
select CPU_V7
|
||||||
select HAS_DEBUG_LL
|
select HAS_DEBUG_LL
|
||||||
select BUILTIN_DTB
|
|
||||||
select COMMON_CLK
|
select COMMON_CLK
|
||||||
select COMMON_CLK_OF_PROVIDER
|
select COMMON_CLK_OF_PROVIDER
|
||||||
select CLKDEV_LOOKUP
|
select CLKDEV_LOOKUP
|
||||||
select GPIOLIB
|
select GPIOLIB
|
||||||
select GPIO_TEGRA
|
select GPIO_TEGRA
|
||||||
|
select HAVE_DEFAULT_ENVIRONMENT_NEW
|
||||||
|
select HAVE_PBL_MULTI_IMAGES
|
||||||
select OFDEVICE
|
select OFDEVICE
|
||||||
select OFTREE
|
select OFTREE
|
||||||
|
select RELOCATABLE
|
||||||
|
|
||||||
config ARCH_ZYNQ
|
config ARCH_ZYNQ
|
||||||
bool "Xilinx Zynq-based boards"
|
bool "Xilinx Zynq-based boards"
|
||||||
|
|
|
@ -80,6 +80,7 @@ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
|
||||||
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
|
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
|
||||||
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
|
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
|
||||||
obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/
|
obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/
|
||||||
|
obj-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += toradex-colibri-t20-iris/
|
||||||
obj-$(CONFIG_MACH_TOSHIBA_AC100) += toshiba-ac100/
|
obj-$(CONFIG_MACH_TOSHIBA_AC100) += toshiba-ac100/
|
||||||
obj-$(CONFIG_MACH_TQMA53) += tqma53/
|
obj-$(CONFIG_MACH_TQMA53) += tqma53/
|
||||||
obj-$(CONFIG_MACH_TQMA6X) += tqma6x/
|
obj-$(CONFIG_MACH_TQMA6X) += tqma6x/
|
||||||
|
|
|
@ -0,0 +1,2 @@
|
||||||
|
CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t
|
||||||
|
lwl-y += entry.o
|
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <sizes.h>
|
||||||
|
#include <asm/barebox-arm.h>
|
||||||
|
#include <asm/barebox-arm-head.h>
|
||||||
|
#include <mach/lowlevel.h>
|
||||||
|
|
||||||
|
extern char __dtb_tegra20_colibri_iris_start[];
|
||||||
|
|
||||||
|
ENTRY_FUNCTION(start_toradex_colibri_t20_iris)(void)
|
||||||
|
{
|
||||||
|
uint32_t fdt;
|
||||||
|
|
||||||
|
__barebox_arm_head();
|
||||||
|
|
||||||
|
tegra_cpu_lowlevel_setup();
|
||||||
|
|
||||||
|
fdt = (uint32_t)__dtb_tegra20_colibri_iris_start - get_runtime_offset();
|
||||||
|
|
||||||
|
tegra_avp_reset_vector(fdt);
|
||||||
|
}
|
|
@ -1,7 +0,0 @@
|
||||||
if MACH_TOSHIBA_AC100
|
|
||||||
|
|
||||||
config ARCH_TEXT_BASE
|
|
||||||
hex
|
|
||||||
default 0x01000000
|
|
||||||
|
|
||||||
endif
|
|
|
@ -1 +1,3 @@
|
||||||
|
CFLAGS_pbl-entry.o := -mcpu=arm7tdmi -march=armv4t
|
||||||
|
lwl-y += entry.o
|
||||||
obj-y += board.o
|
obj-y += board.o
|
||||||
|
|
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify it
|
||||||
|
* under the terms and conditions of the GNU General Public License,
|
||||||
|
* version 2, as published by the Free Software Foundation.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||||
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||||
|
* more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <sizes.h>
|
||||||
|
#include <asm/barebox-arm.h>
|
||||||
|
#include <asm/barebox-arm-head.h>
|
||||||
|
#include <mach/lowlevel.h>
|
||||||
|
|
||||||
|
extern char __dtb_tegra20_paz00_start[];
|
||||||
|
|
||||||
|
ENTRY_FUNCTION(start_toshiba_ac100)(void)
|
||||||
|
{
|
||||||
|
uint32_t fdt;
|
||||||
|
|
||||||
|
__barebox_arm_head();
|
||||||
|
|
||||||
|
tegra_cpu_lowlevel_setup();
|
||||||
|
|
||||||
|
fdt = (uint32_t)__dtb_tegra20_paz00_start - get_runtime_offset();
|
||||||
|
|
||||||
|
tegra_avp_reset_vector(fdt);
|
||||||
|
}
|
|
@ -1,18 +1,21 @@
|
||||||
CONFIG_BUILTIN_DTB_NAME="tegra20-colibri-iris"
|
|
||||||
CONFIG_ARCH_TEGRA=y
|
CONFIG_ARCH_TEGRA=y
|
||||||
|
CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS=y
|
||||||
|
CONFIG_MACH_TOSHIBA_AC100=y
|
||||||
CONFIG_AEABI=y
|
CONFIG_AEABI=y
|
||||||
CONFIG_CMD_ARM_MMUINFO=y
|
CONFIG_CMD_ARM_MMUINFO=y
|
||||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
||||||
|
CONFIG_ARM_UNWIND=y
|
||||||
|
CONFIG_MMU=y
|
||||||
CONFIG_STACK_SIZE=0x10000
|
CONFIG_STACK_SIZE=0x10000
|
||||||
CONFIG_MALLOC_SIZE=0x4000000
|
CONFIG_MALLOC_SIZE=0x4000000
|
||||||
CONFIG_LONGHELP=y
|
CONFIG_LONGHELP=y
|
||||||
CONFIG_GLOB=y
|
|
||||||
CONFIG_GLOB_SORT=y
|
|
||||||
CONFIG_HUSH_FANCY_PROMPT=y
|
CONFIG_HUSH_FANCY_PROMPT=y
|
||||||
CONFIG_HUSH_GETOPT=y
|
|
||||||
CONFIG_CMDLINE_EDITING=y
|
CONFIG_CMDLINE_EDITING=y
|
||||||
CONFIG_AUTO_COMPLETE=y
|
CONFIG_AUTO_COMPLETE=y
|
||||||
|
CONFIG_MENU=y
|
||||||
|
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
|
||||||
CONFIG_CMD_EDIT=y
|
CONFIG_CMD_EDIT=y
|
||||||
|
CONFIG_CMD_EXPORT=y
|
||||||
CONFIG_CMD_MEMINFO=y
|
CONFIG_CMD_MEMINFO=y
|
||||||
CONFIG_CMD_IOMEM=y
|
CONFIG_CMD_IOMEM=y
|
||||||
CONFIG_CMD_BOOTZ=y
|
CONFIG_CMD_BOOTZ=y
|
|
@ -1,42 +0,0 @@
|
||||||
CONFIG_BUILTIN_DTB_NAME="tegra20-paz00"
|
|
||||||
CONFIG_ARCH_TEGRA=y
|
|
||||||
CONFIG_TEGRA_UART_A=y
|
|
||||||
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
|
||||||
CONFIG_TEXT_BASE=0x01000000
|
|
||||||
CONFIG_BROKEN=y
|
|
||||||
CONFIG_EXPERIMENTAL=y
|
|
||||||
CONFIG_PROMPT="toshiba ac100> "
|
|
||||||
CONFIG_LONGHELP=y
|
|
||||||
CONFIG_CMDLINE_EDITING=y
|
|
||||||
CONFIG_AUTO_COMPLETE=y
|
|
||||||
# CONFIG_ERRNO_MESSAGES is not set
|
|
||||||
# CONFIG_DEFAULT_ENVIRONMENT is not set
|
|
||||||
CONFIG_POLLER=y
|
|
||||||
CONFIG_ENABLE_DEVICE_NOISE=y
|
|
||||||
CONFIG_CMD_SLEEP=y
|
|
||||||
# CONFIG_CMD_TRUE is not set
|
|
||||||
# CONFIG_CMD_FALSE is not set
|
|
||||||
CONFIG_CMD_TFTP=y
|
|
||||||
CONFIG_CMD_LOADB=y
|
|
||||||
CONFIG_CMD_LOADY=y
|
|
||||||
CONFIG_CMD_LOADS=y
|
|
||||||
CONFIG_CMD_MEMINFO=y
|
|
||||||
CONFIG_CMD_MD5SUM=y
|
|
||||||
CONFIG_CMD_SHA1SUM=y
|
|
||||||
CONFIG_CMD_BOOTM_SHOW_TYPE=y
|
|
||||||
CONFIG_CMD_RESET=y
|
|
||||||
CONFIG_CMD_GO=y
|
|
||||||
CONFIG_CMD_OFTREE=y
|
|
||||||
CONFIG_NET=y
|
|
||||||
CONFIG_NET_DHCP=y
|
|
||||||
CONFIG_NET_PING=y
|
|
||||||
CONFIG_NET_NETCONSOLE=y
|
|
||||||
CONFIG_DRIVER_SERIAL_NS16550=y
|
|
||||||
CONFIG_NET_USB=y
|
|
||||||
CONFIG_NET_USB_ASIX=y
|
|
||||||
# CONFIG_SPI is not set
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_EHCI=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_FS_TFTP=y
|
|
||||||
CONFIG_FS_FAT=y
|
|
|
@ -13,6 +13,9 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
|
||||||
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
|
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
|
||||||
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
|
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
|
||||||
socfpga_cyclone5_socrates.dtb
|
socfpga_cyclone5_socrates.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_TEGRA) += \
|
||||||
|
tegra20-colibri-iris.dtb \
|
||||||
|
tegra20-paz00.dtb
|
||||||
|
|
||||||
BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
|
BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
|
||||||
obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
|
obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
|
||||||
|
@ -25,6 +28,8 @@ pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6q-phytec-pbab01.dtb.o
|
||||||
pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
|
pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
|
||||||
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o
|
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o
|
||||||
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
|
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
|
||||||
|
pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += tegra20-colibri-iris.dtb.o
|
||||||
|
pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
|
||||||
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
|
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
|
||||||
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
|
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
|
||||||
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
|
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
|
||||||
|
|
|
@ -1,13 +1,11 @@
|
||||||
if ARCH_TEGRA
|
if ARCH_TEGRA
|
||||||
|
|
||||||
choice
|
config ARCH_TEXT_BASE
|
||||||
prompt "Tegra processor type"
|
hex
|
||||||
|
default 0x0
|
||||||
|
|
||||||
config ARCH_TEGRA_2x_SOC
|
config BOARDINFO
|
||||||
bool "Tegra 20"
|
default ""
|
||||||
select PINCTRL_TEGRA20
|
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
choice
|
choice
|
||||||
prompt "Tegra debug UART"
|
prompt "Tegra debug UART"
|
||||||
|
@ -44,34 +42,21 @@ endchoice
|
||||||
|
|
||||||
# ---------------------------------------------------------
|
# ---------------------------------------------------------
|
||||||
|
|
||||||
if ARCH_TEGRA_2x_SOC
|
config ARCH_TEGRA_2x_SOC
|
||||||
|
bool
|
||||||
|
select PINCTRL_TEGRA20
|
||||||
|
|
||||||
config ARCH_TEXT_BASE
|
menu "select Tegra boards to be built"
|
||||||
hex
|
|
||||||
default 0x00108000
|
|
||||||
|
|
||||||
choice
|
config MACH_TORADEX_COLIBRI_T20_IRIS
|
||||||
prompt "Tegra 20 Board Type"
|
bool "Toradex Colibri T20 on Iris Carrier"
|
||||||
|
select ARCH_TEGRA_2x_SOC
|
||||||
config MACH_TEGRA20_GENERIC
|
|
||||||
bool "Generic DT based board"
|
|
||||||
help
|
|
||||||
Say Y here if you are building for a generic DT based board.
|
|
||||||
|
|
||||||
config MACH_TOSHIBA_AC100
|
config MACH_TOSHIBA_AC100
|
||||||
bool "Toshiba AC100"
|
bool "Toshiba AC100"
|
||||||
help
|
select ARCH_TEGRA_2x_SOC
|
||||||
Say Y here if you are using Toshiba AC100 smartbook.
|
|
||||||
|
|
||||||
endchoice
|
endmenu
|
||||||
|
|
||||||
if MACH_TEGRA20_GENERIC
|
|
||||||
|
|
||||||
endif #MACH_TEGRA20_GENERIC
|
|
||||||
|
|
||||||
source arch/arm/boards/toshiba-ac100/Kconfig
|
|
||||||
|
|
||||||
endif #ARCH_TEGRA_2x_SOC
|
|
||||||
|
|
||||||
# ---------------------------------------------------------
|
# ---------------------------------------------------------
|
||||||
|
|
||||||
|
|
|
@ -1,4 +1,5 @@
|
||||||
CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
|
CFLAGS_tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
|
||||||
|
CFLAGS_pbl-tegra_avp_init.o := -mcpu=arm7tdmi -march=armv4t
|
||||||
lwl-y += tegra_avp_init.o
|
lwl-y += tegra_avp_init.o
|
||||||
lwl-y += tegra_maincomplex_init.o
|
lwl-y += tegra_maincomplex_init.o
|
||||||
obj-y += tegra20.o
|
obj-y += tegra20.o
|
||||||
|
|
|
@ -40,7 +40,8 @@
|
||||||
#define T20_ODMDATA_UARTID_SHIFT 15
|
#define T20_ODMDATA_UARTID_SHIFT 15
|
||||||
#define T20_ODMDATA_UARTID_MASK (7 << T20_ODMDATA_UARTID_SHIFT)
|
#define T20_ODMDATA_UARTID_MASK (7 << T20_ODMDATA_UARTID_SHIFT)
|
||||||
|
|
||||||
static inline u32 tegra_get_odmdata(void)
|
static inline __attribute__((always_inline))
|
||||||
|
u32 tegra_get_odmdata(void)
|
||||||
{
|
{
|
||||||
u32 bctsize, bctptr, odmdata;
|
u32 bctsize, bctptr, odmdata;
|
||||||
|
|
||||||
|
@ -62,7 +63,8 @@ enum tegra_chiptype {
|
||||||
TEGRA20 = 0,
|
TEGRA20 = 0,
|
||||||
};
|
};
|
||||||
|
|
||||||
static inline enum tegra_chiptype tegra_get_chiptype(void)
|
static inline __attribute__((always_inline))
|
||||||
|
enum tegra_chiptype tegra_get_chiptype(void)
|
||||||
{
|
{
|
||||||
u32 hidrev;
|
u32 hidrev;
|
||||||
|
|
||||||
|
@ -76,7 +78,8 @@ static inline enum tegra_chiptype tegra_get_chiptype(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline int tegra_get_num_cores(void)
|
static inline __attribute__((always_inline))
|
||||||
|
int tegra_get_num_cores(void)
|
||||||
{
|
{
|
||||||
switch (tegra_get_chiptype()) {
|
switch (tegra_get_chiptype()) {
|
||||||
case TEGRA20:
|
case TEGRA20:
|
||||||
|
@ -89,7 +92,8 @@ static inline int tegra_get_num_cores(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Runtime data */
|
/* Runtime data */
|
||||||
static inline int tegra_cpu_is_maincomplex(void)
|
static inline __attribute__((always_inline))
|
||||||
|
int tegra_cpu_is_maincomplex(void)
|
||||||
{
|
{
|
||||||
u32 tag0;
|
u32 tag0;
|
||||||
|
|
||||||
|
@ -98,7 +102,8 @@ static inline int tegra_cpu_is_maincomplex(void)
|
||||||
return (tag0 & 0xff) == 0x55;
|
return (tag0 & 0xff) == 0x55;
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline uint32_t tegra20_get_ramsize(void)
|
static inline __attribute__((always_inline))
|
||||||
|
uint32_t tegra20_get_ramsize(void)
|
||||||
{
|
{
|
||||||
switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
|
switch ((tegra_get_odmdata() & T20_ODMDATA_RAMSIZE_MASK) >>
|
||||||
T20_ODMDATA_RAMSIZE_SHIFT) {
|
T20_ODMDATA_RAMSIZE_SHIFT) {
|
||||||
|
@ -120,7 +125,8 @@ static long uart_id_to_base[] = {
|
||||||
TEGRA_UARTE_BASE,
|
TEGRA_UARTE_BASE,
|
||||||
};
|
};
|
||||||
|
|
||||||
static inline long tegra20_get_debuguart_base(void)
|
static inline __attribute__((always_inline))
|
||||||
|
long tegra20_get_debuguart_base(void)
|
||||||
{
|
{
|
||||||
u32 odmdata;
|
u32 odmdata;
|
||||||
int id;
|
int id;
|
||||||
|
@ -146,7 +152,8 @@ static inline long tegra20_get_debuguart_base(void)
|
||||||
#define CRC_OSC_CTRL_OSC_FREQ_SHIFT 30
|
#define CRC_OSC_CTRL_OSC_FREQ_SHIFT 30
|
||||||
#define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
|
#define CRC_OSC_CTRL_OSC_FREQ_MASK (0x3 << CRC_OSC_CTRL_OSC_FREQ_SHIFT)
|
||||||
|
|
||||||
static inline unsigned int tegra_get_osc_clock(void)
|
static inline unsigned __attribute__((always_inline))
|
||||||
|
int tegra_get_osc_clock(void)
|
||||||
{
|
{
|
||||||
u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
|
u32 osc_ctrl = readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL);
|
||||||
|
|
||||||
|
@ -165,5 +172,20 @@ static inline unsigned int tegra_get_osc_clock(void)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline __attribute__((always_inline))
|
||||||
|
void tegra_cpu_lowlevel_setup(void)
|
||||||
|
{
|
||||||
|
uint32_t r;
|
||||||
|
|
||||||
|
/* set the cpu to SVC32 mode */
|
||||||
|
__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
|
||||||
|
r &= ~0x1f;
|
||||||
|
r |= 0xd3;
|
||||||
|
__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* reset vector for the AVP, to be called from board reset vector */
|
||||||
|
void tegra_avp_reset_vector(uint32_t boarddata);
|
||||||
|
|
||||||
/* reset vector for the main CPU complex */
|
/* reset vector for the main CPU complex */
|
||||||
void tegra_maincomplex_entry(void);
|
void tegra_maincomplex_entry(void);
|
||||||
|
|
|
@ -65,3 +65,5 @@
|
||||||
#define PMC_PWRGATE_STATUS_VE (1 << 2)
|
#define PMC_PWRGATE_STATUS_VE (1 << 2)
|
||||||
#define PMC_PWRGATE_STATUS_TD (1 << 1)
|
#define PMC_PWRGATE_STATUS_TD (1 << 1)
|
||||||
#define PMC_PWRGATE_STATUS_CPU (1 << 0)
|
#define PMC_PWRGATE_STATUS_CPU (1 << 0)
|
||||||
|
|
||||||
|
#define PMC_SCRATCH(i) (0x050 + 0x4*i)
|
||||||
|
|
|
@ -19,21 +19,11 @@
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/barebox-arm-head.h>
|
#include <asm/barebox-arm-head.h>
|
||||||
|
#include <asm/barebox-arm.h>
|
||||||
#include <mach/lowlevel.h>
|
#include <mach/lowlevel.h>
|
||||||
#include <mach/tegra20-car.h>
|
#include <mach/tegra20-car.h>
|
||||||
#include <mach/tegra20-pmc.h>
|
#include <mach/tegra20-pmc.h>
|
||||||
|
|
||||||
static inline void tegra_cpu_lowlevel_setup(void)
|
|
||||||
{
|
|
||||||
uint32_t r;
|
|
||||||
|
|
||||||
/* set the cpu to SVC32 mode */
|
|
||||||
__asm__ __volatile__("mrs %0, cpsr":"=r"(r));
|
|
||||||
r &= ~0x1f;
|
|
||||||
r |= 0xd3;
|
|
||||||
__asm__ __volatile__("msr cpsr, %0" : : "r"(r));
|
|
||||||
}
|
|
||||||
|
|
||||||
/* instruct the PMIC to enable the CPU power rail */
|
/* instruct the PMIC to enable the CPU power rail */
|
||||||
static void enable_maincomplex_powerrail(void)
|
static void enable_maincomplex_powerrail(void)
|
||||||
{
|
{
|
||||||
|
@ -108,8 +98,6 @@ static void init_pllx(void)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
chiptype = tegra_get_chiptype();
|
chiptype = tegra_get_chiptype();
|
||||||
if (chiptype < 0)
|
|
||||||
BUG();
|
|
||||||
|
|
||||||
osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) &
|
osc_freq = (readl(TEGRA_CLK_RESET_BASE + CRC_OSC_CTRL) &
|
||||||
CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT;
|
CRC_OSC_CTRL_OSC_FREQ_MASK) >> CRC_OSC_CTRL_OSC_FREQ_SHIFT;
|
||||||
|
@ -187,24 +175,12 @@ static void maincomplex_powerup(void)
|
||||||
writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
|
writel(reg, TEGRA_PMC_BASE + PMC_REMOVE_CLAMPING_CMD);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
void barebox_arm_reset_vector(void)
|
void tegra_avp_reset_vector(uint32_t boarddata)
|
||||||
{
|
{
|
||||||
int num_cores;
|
int num_cores;
|
||||||
|
|
||||||
/* minimal initialization, OK for both ARMv4 and ARMv7 */
|
|
||||||
tegra_cpu_lowlevel_setup();
|
|
||||||
|
|
||||||
/*
|
|
||||||
* If we are already running on the main CPU complex jump straight
|
|
||||||
* to the maincomplex entry point.
|
|
||||||
*/
|
|
||||||
if (tegra_cpu_is_maincomplex())
|
|
||||||
tegra_maincomplex_entry();
|
|
||||||
|
|
||||||
/* get the number of cores in the main CPU complex of the current SoC */
|
/* get the number of cores in the main CPU complex of the current SoC */
|
||||||
num_cores = tegra_get_num_cores();
|
num_cores = tegra_get_num_cores();
|
||||||
if (!num_cores)
|
|
||||||
BUG();
|
|
||||||
|
|
||||||
/* bring down main CPU complex (this may be a warm boot) */
|
/* bring down main CPU complex (this may be a warm boot) */
|
||||||
enable_maincomplex_powerrail();
|
enable_maincomplex_powerrail();
|
||||||
|
@ -212,7 +188,11 @@ void barebox_arm_reset_vector(void)
|
||||||
stop_maincomplex_clocks(num_cores);
|
stop_maincomplex_clocks(num_cores);
|
||||||
|
|
||||||
/* set start address for the main CPU complex processors */
|
/* set start address for the main CPU complex processors */
|
||||||
writel(barebox_arm_head, TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
|
writel(tegra_maincomplex_entry - get_runtime_offset(),
|
||||||
|
TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
|
||||||
|
|
||||||
|
/* put boarddata in scratch reg, for main CPU to fetch after startup */
|
||||||
|
writel(boarddata, TEGRA_PMC_BASE + PMC_SCRATCH(10));
|
||||||
|
|
||||||
/* bring up main CPU complex */
|
/* bring up main CPU complex */
|
||||||
start_cpu0_clocks();
|
start_cpu0_clocks();
|
||||||
|
|
|
@ -19,6 +19,7 @@
|
||||||
#include <asm/barebox-arm-head.h>
|
#include <asm/barebox-arm-head.h>
|
||||||
#include <asm/barebox-arm.h>
|
#include <asm/barebox-arm.h>
|
||||||
#include <mach/lowlevel.h>
|
#include <mach/lowlevel.h>
|
||||||
|
#include <mach/tegra20-pmc.h>
|
||||||
|
|
||||||
void tegra_maincomplex_entry(void)
|
void tegra_maincomplex_entry(void)
|
||||||
{
|
{
|
||||||
|
@ -33,14 +34,9 @@ void tegra_maincomplex_entry(void)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
/* If we don't know the chiptype, better bail out */
|
/* If we don't know the chiptype, better bail out */
|
||||||
BUG();
|
unreachable();
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
barebox_arm_entry(rambase, ramsize,
|
||||||
* The standard load address for Tegra systems is 0x10800 which means
|
readl(TEGRA_PMC_BASE + PMC_SCRATCH(10)));
|
||||||
* the barebox binary will always be below the malloc area for all
|
|
||||||
* reasonable malloc area sizes. We offset the RAM base address by 8MB
|
|
||||||
* to pretend barebox is in another bank.
|
|
||||||
*/
|
|
||||||
barebox_arm_entry(rambase + SZ_8M, ramsize - SZ_8M, 0);
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -109,6 +109,7 @@ $(obj)/%.img: $(obj)/$$(FILE_$$(@F))
|
||||||
include $(srctree)/images/Makefile.imx
|
include $(srctree)/images/Makefile.imx
|
||||||
include $(srctree)/images/Makefile.mvebu
|
include $(srctree)/images/Makefile.mvebu
|
||||||
include $(srctree)/images/Makefile.socfpga
|
include $(srctree)/images/Makefile.socfpga
|
||||||
|
include $(srctree)/images/Makefile.tegra
|
||||||
|
|
||||||
targets += $(image-y) pbl.lds barebox.x barebox.z
|
targets += $(image-y) pbl.lds barebox.x barebox.z
|
||||||
targets += $(patsubst %,%.pblx,$(pblx-y))
|
targets += $(patsubst %,%.pblx,$(pblx-y))
|
||||||
|
|
|
@ -0,0 +1,14 @@
|
||||||
|
#
|
||||||
|
# barebox image generation Makefile for Tegra images
|
||||||
|
#
|
||||||
|
|
||||||
|
board = $(srctree)/arch/$(ARCH)/boards
|
||||||
|
|
||||||
|
# ----------------------- Tegra20 based boards ---------------------------
|
||||||
|
pblx-$(CONFIG_MACH_TOSHIBA_AC100) += start_toshiba_ac100
|
||||||
|
FILE_barebox-tegra20-toshiba-ac100.img = start_toshiba_ac100.pblx
|
||||||
|
image-$(CONFIG_MACH_TOSHIBA_AC100) += barebox-tegra20-toshiba-ac100.img
|
||||||
|
|
||||||
|
pblx-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += start_toradex_colibri_t20_iris
|
||||||
|
FILE_barebox-tegra20-toradex-colibri-t20-iris.img = start_toradex_colibri_t20_iris.pblx
|
||||||
|
image-$(CONFIG_MACH_TORADEX_COLIBRI_T20_IRIS) += barebox-tegra20-toradex-colibri-t20-iris.img
|
Loading…
Reference in New Issue