clocksource: mvebu: split initialization for Armada 370/XP
Timers found on Marvell Armada 370 and XP require different setup. While timer clock on Armada 370 can be derived from a divided reference clocks, Armada XP always uses a 25MHz reference. This also updates compatibles to destinguish timers for both SoCs and fixes some whitespace issues on defines. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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@ -20,23 +20,26 @@
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#include <io.h>
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#include <io.h>
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#define TIMER_CTRL_OFF 0x0000
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#define TIMER_CTRL_OFF 0x0000
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#define TIMER0_EN 0x0001
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#define TIMER0_EN BIT(0)
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#define TIMER0_RELOAD_EN 0x0002
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#define TIMER0_RELOAD_EN BIT(1)
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#define TIMER0_25MHZ 0x0800
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#define TIMER0_25MHZ BIT(11)
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#define TIMER0_DIV(div) ((div) << 19)
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#define TIMER0_DIV(div) ((div) << 19)
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#define TIMER1_EN 0x0004
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#define TIMER0_DIV_MASK TIMER0_DIV(0x7)
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#define TIMER1_RELOAD_EN 0x0008
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#define TIMER1_EN BIT(2)
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#define TIMER1_25MHZ 0x1000
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#define TIMER1_RELOAD_EN BIT(3)
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#define TIMER1_25MHZ BIT(12)
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#define TIMER1_DIV(div) ((div) << 22)
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#define TIMER1_DIV(div) ((div) << 22)
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#define TIMER1_DIV_MASK TIMER1_DIV(0x7)
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#define TIMER_EVENTS_STATUS 0x0004
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#define TIMER_EVENTS_STATUS 0x0004
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#define TIMER0_CLR_MASK (~0x1)
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#define TIMER0_CLR_MASK (~BIT(0))
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#define TIMER1_CLR_MASK (~0x100)
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#define TIMER1_CLR_MASK (~BIT(9))
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#define TIMER0_RELOAD_OFF 0x0010
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#define TIMER0_RELOAD_OFF 0x0010
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#define TIMER0_VAL_OFF 0x0014
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#define TIMER0_VAL_OFF 0x0014
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#define TIMER1_RELOAD_OFF 0x0018
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#define TIMER1_RELOAD_OFF 0x0018
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#define TIMER1_VAL_OFF 0x001c
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#define TIMER1_VAL_OFF 0x001c
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#define TIMER_DIVIDER_SHIFT 5
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#define TIMER_DIVIDER_SHIFT 5
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#define TIMER_DIVIDER BIT(TIMER_DIVIDER_SHIFT)
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static __iomem void *timer_base;
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static __iomem void *timer_base;
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@ -53,24 +56,35 @@ static struct clocksource cs = {
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static int mvebu_timer_probe(struct device_d *dev)
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static int mvebu_timer_probe(struct device_d *dev)
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{
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{
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struct clk *tclk;
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struct clk *clk;
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u32 val;
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u32 rate, div, val;
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timer_base = dev_request_mem_region(dev, 0);
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timer_base = dev_request_mem_region(dev, 0);
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tclk = clk_get(dev, NULL);
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val = __raw_readl(timer_base + TIMER_CTRL_OFF);
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val = __raw_readl(timer_base + TIMER_CTRL_OFF);
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val &= ~TIMER0_25MHZ;
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val &= ~(TIMER0_25MHZ | TIMER0_DIV_MASK);
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if (of_device_is_compatible(dev->device_node,
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"marvell,armada-370-timer")) {
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clk = clk_get(dev, NULL);
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div = TIMER_DIVIDER;
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val |= TIMER0_DIV(TIMER_DIVIDER_SHIFT);
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rate = clk_get_rate(clk) / TIMER_DIVIDER;
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} else {
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clk = clk_get(dev, "fixed");
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div = 1;
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val |= TIMER0_25MHZ;
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rate = clk_get_rate(clk);
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}
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__raw_writel(val, timer_base + TIMER_CTRL_OFF);
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__raw_writel(val, timer_base + TIMER_CTRL_OFF);
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__raw_writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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__raw_writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
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__raw_writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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__raw_writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
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val = __raw_readl(timer_base + TIMER_CTRL_OFF);
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val = __raw_readl(timer_base + TIMER_CTRL_OFF);
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val |= TIMER0_EN | TIMER0_RELOAD_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
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val |= TIMER0_EN | TIMER0_RELOAD_EN;
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__raw_writel(val, timer_base + TIMER_CTRL_OFF);
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__raw_writel(val, timer_base + TIMER_CTRL_OFF);
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cs.mult = clocksource_hz2mult(clk_get_rate(tclk), cs.shift);
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cs.mult = clocksource_hz2mult(rate, cs.shift);
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init_clock(&cs);
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init_clock(&cs);
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@ -78,7 +92,8 @@ static int mvebu_timer_probe(struct device_d *dev)
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}
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}
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static struct of_device_id mvebu_timer_dt_ids[] = {
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static struct of_device_id mvebu_timer_dt_ids[] = {
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{ .compatible = "marvell,armada-370-xp-timer", },
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{ .compatible = "marvell,armada-370-timer", },
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{ .compatible = "marvell,armada-xp-timer", },
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{ }
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{ }
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};
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};
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