at91: add Ronetix pm9261 board support
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Ilko Iliev <iliev@ronetix.at>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
parent
d923f0dedb
commit
7a5cb50f08
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@ -79,6 +79,7 @@ board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
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board-$(CONFIG_MACH_PCM037) := pcm037
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board-$(CONFIG_MACH_PCM038) := pcm038
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board-$(CONFIG_MACH_PCM043) := pcm043
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board-$(CONFIG_MACH_PM9261) := pm9261
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board-$(CONFIG_MACH_PM9263) := pm9263
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board-$(CONFIG_MACH_SCB9328) := scb9328
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board-$(CONFIG_MACH_NESO) := guf-neso
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@ -0,0 +1 @@
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obj-y += init.o
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@ -0,0 +1,110 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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#define MASTER_PLL_DIV 15
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#define MASTER_PLL_MUL 162
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#define MAIN_PLL_DIV 2
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/* clocks */
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#define CONFIG_SYS_MOR_VAL \
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(AT91_PMC_MOSCEN | \
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(255 << 8)) /* Main Oscillator Start-up Time */
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#define CONFIG_SYS_PLLAR_VAL \
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(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
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AT91_PMC_OUT | \
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((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR1_VAL \
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(AT91_PMC_CSS_SLOW | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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/* PCK/2 = MCK Master Clock from PLLA */
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#define CONFIG_SYS_MCKR2_VAL \
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(AT91_PMC_CSS_PLLA | \
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AT91_PMC_PRES_1 | \
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AT91SAM9_PMC_MDIV_2 | \
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AT91_PMC_PDIV_1)
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/* define PDC[31:16] as DATA[31:16] */
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#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
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/* no pull-up for D[31:16] */
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#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
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/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
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#define CONFIG_SYS_MATRIX_EBICSA_VAL \
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(AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC)
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/* SDRAM */
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/* SDRAMC_MR Mode register */
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#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
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/* SDRAMC_TR - Refresh Timer register */
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#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
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/* SDRAMC_CR - Configuration register*/
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#define CONFIG_SYS_SDRC_CR_VAL \
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(AT91_SDRAMC_NC_9 | \
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AT91_SDRAMC_NR_13 | \
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AT91_SDRAMC_NB_4 | \
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AT91_SDRAMC_CAS_3 | \
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AT91_SDRAMC_DBW_32 | \
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(1 << 8) | /* Write Recovery Delay */ \
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(7 << 12) | /* Row Cycle Delay */ \
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(3 << 16) | /* Row Precharge Delay */ \
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(2 << 20) | /* Row to Column Delay */ \
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(5 << 24) | /* Active to Precharge Delay */ \
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(1 << 28)) /* Exit Self Refresh to Active Delay */
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/* Memory Device Register -> SDRAM */
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#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
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#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
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#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
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#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
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#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
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#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
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#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
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#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
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/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
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#define CONFIG_SYS_SMC0_SETUP0_VAL \
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(AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \
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AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10))
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#define CONFIG_SYS_SMC0_PULSE0_VAL \
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(AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \
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AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11))
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#define CONFIG_SYS_SMC0_CYCLE0_VAL \
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(AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22))
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#define CONFIG_SYS_SMC0_MODE0_VAL \
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(AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \
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AT91_SMC_DBW_16 | \
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AT91_SMC_TDFMODE | \
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AT91_SMC_TDF_(6))
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/* user reset enable */
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#define CONFIG_SYS_RSTC_RMR_VAL \
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(AT91_RSTC_KEY | \
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AT91_RSTC_PROCRST | \
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AT91_RSTC_RSTTYP_WAKEUP | \
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AT91_RSTC_RSTTYP_WATCHDOG)
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/* Disable Watchdog */
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#define CONFIG_SYS_WDTC_WDMR_VAL \
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(AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \
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AT91_WDT_WDV | \
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AT91_WDT_WDDIS | \
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AT91_WDT_WDD)
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#endif /* __CONFIG_H */
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@ -0,0 +1,41 @@
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#!/bin/sh
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# use 'dhcp' to do dhcp in barebox and in kernel
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# use 'none' if you want to skip kernel ip autoconfiguration
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ip=dhcp
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# or set your networking parameters here
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#eth0.ipaddr=a.b.c.d
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#eth0.netmask=a.b.c.d
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#eth0.gateway=a.b.c.d
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#eth0.serverip=a.b.c.d
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# can be either 'net' or 'nand'
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kernel_loc=net
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# can be either 'net', 'nand' or 'initrd'
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rootfs_loc=net
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# can be either 'jffs2' or 'ubifs'
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rootfs_type=ubifs
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rootfsimage=root.$rootfs_type
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# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
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#kernelimage_type=zimage
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#kernelimage=zImage
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kernelimage_type=uimage
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kernelimage=uImage
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#kernelimage_type=raw
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#kernelimage=Image
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#kernelimage_type=raw_lzo
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#kernelimage=Image.lzo
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nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
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rootfs_mtdblock_nor=3
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autoboot_timeout=3
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bootargs="console=ttyS0,115200"
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# set a fancy prompt (if support is compiled in)
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PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
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@ -0,0 +1,168 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <asm/armlinux.h>
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#include <generated/mach-types.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <nand.h>
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#include <linux/mtd/nand.h>
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#include <mach/at91_pmc.h>
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#include <mach/board.h>
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#include <mach/gpio.h>
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#include <mach/io.h>
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#include <mach/at91sam9_smc.h>
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#include <mach/sam9_smc.h>
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#include <dm9000.h>
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static struct atmel_nand_data nand_pdata = {
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.ale = 22,
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.cle = 21,
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/* .det_pin = ... not connected */
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.rdy_pin = AT91_PIN_PA16,
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.enable_pin = AT91_PIN_PC14,
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#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
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.bus_width_16 = 1,
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#else
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.bus_width_16 = 0,
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#endif
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};
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static struct sam9_smc_config pm_nand_smc_config = {
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.ncs_read_setup = 0,
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.nrd_setup = 1,
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.ncs_write_setup = 0,
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.nwe_setup = 1,
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.ncs_read_pulse = 3,
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.nrd_pulse = 3,
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.ncs_write_pulse = 3,
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.nwe_pulse = 3,
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.read_cycle = 5,
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.write_cycle = 5,
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.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
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.tdf_cycles = 2,
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};
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static void pm_add_device_nand(void)
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{
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/* setup bus-width (8 or 16) */
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if (nand_pdata.bus_width_16)
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pm_nand_smc_config.mode |= AT91_SMC_DBW_16;
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else
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pm_nand_smc_config.mode |= AT91_SMC_DBW_8;
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/* configure chip-select 3 (NAND) */
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sam9_smc_configure(3, &pm_nand_smc_config);
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at91_add_device_nand(&nand_pdata);
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}
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/*
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* DM9000 ethernet device
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*/
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#if defined(CONFIG_DRIVER_NET_DM9000)
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static struct dm9000_platform_data dm9000_data = {
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.iobase = AT91_CHIPSELECT_2,
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.iodata = AT91_CHIPSELECT_2 + 4,
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.buswidth = DM9000_WIDTH_16,
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.srom = 1,
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};
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static struct device_d dm9000_dev = {
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.id = 0,
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.name = "dm9000",
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.map_base = AT91_CHIPSELECT_2,
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.size = 8,
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.platform_data = &dm9000_data,
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};
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/*
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* SMC timings for the DM9000.
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* Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings.
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*/
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static struct sam9_smc_config __initdata dm9000_smc_config = {
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.ncs_read_setup = 0,
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.nrd_setup = 2,
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.ncs_write_setup = 0,
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.nwe_setup = 2,
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.ncs_read_pulse = 8,
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.nrd_pulse = 4,
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.ncs_write_pulse = 8,
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.nwe_pulse = 4,
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.read_cycle = 16,
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.write_cycle = 16,
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.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16,
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.tdf_cycles = 1,
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};
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static void __init pm_add_device_dm9000(void)
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{
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/* Configure chip-select 2 (DM9000) */
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sam9_smc_configure(2, &dm9000_smc_config);
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register_device(&dm9000_dev);
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}
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#else
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static void __init ek_add_device_dm9000(void) {}
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#endif /* CONFIG_DRIVER_NET_DM9000 */
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static struct device_d cfi_dev = {
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.id = 0,
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.name = "cfi_flash",
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.map_base = AT91_CHIPSELECT_0,
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.size = 4 * 1024 * 1024,
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};
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static int pm9261_devices_init(void)
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{
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at91_add_device_sdram(64 * 1024 * 1024);
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pm_add_device_nand();
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register_device(&cfi_dev);
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pm_add_device_dm9000();
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devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
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devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0");
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armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
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armlinux_set_architecture(MACH_TYPE_PM9261);
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return 0;
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}
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device_initcall(pm9261_devices_init);
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static int pm9261_console_init(void)
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{
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at91_register_uart(0, 0);
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return 0;
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}
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console_initcall(pm9261_console_init);
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@ -0,0 +1,52 @@
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CONFIG_ARCH_AT91SAM9261=y
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CONFIG_MACH_PM9261=y
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CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
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CONFIG_PROMPT="PM9261:"
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CONFIG_LONGHELP=y
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CONFIG_GLOB=y
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CONFIG_HUSH_FANCY_PROMPT=y
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_MENU=y
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CONFIG_PARTITION=y
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CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
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CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9261/env/"
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CONFIG_CMD_EDIT=y
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CONFIG_CMD_SLEEP=y
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CONFIG_CMD_SAVEENV=y
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CONFIG_CMD_LOADENV=y
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CONFIG_CMD_EXPORT=y
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CONFIG_CMD_PRINTENV=y
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CONFIG_CMD_READLINE=y
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CONFIG_CMD_MENU=y
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CONFIG_CMD_MENU_MANAGEMENT=y
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CONFIG_CMD_PASSWD=y
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CONFIG_CMD_ECHO_E=y
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CONFIG_CMD_LOADB=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_MTEST=y
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CONFIG_CMD_FLASH=y
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CONFIG_CMD_BOOTM_ZLIB=y
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CONFIG_CMD_BOOTM_BZLIB=y
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CONFIG_CMD_BOOTM_SHOW_TYPE=y
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CONFIG_CMD_RESET=y
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CONFIG_CMD_GO=y
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CONFIG_CMD_TIMEOUT=y
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CONFIG_CMD_PARTITION=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_UNLZO=y
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CONFIG_NET=y
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CONFIG_NET_DHCP=y
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CONFIG_NET_NFS=y
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CONFIG_NET_PING=y
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CONFIG_NET_TFTP=y
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CONFIG_NET_TFTP_PUSH=y
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CONFIG_NET_RESOLV=y
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CONFIG_DRIVER_NET_DM9000=y
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# CONFIG_SPI is not set
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CONFIG_DRIVER_CFI=y
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CONFIG_CFI_BUFFER_WRITE=y
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CONFIG_MTD=y
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CONFIG_NAND=y
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CONFIG_NAND_ATMEL=y
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CONFIG_UBI=y
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@ -10,6 +10,7 @@ config BOARDINFO
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default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK
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default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK
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default "Bucyrus MMC-CPU" if MACH_MMCCPU
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default "Ronetix PM9261" if MACH_PM9261
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default "Ronetix PM9263" if MACH_PM9263
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config HAVE_NAND_ATMEL_BUSWIDTH_16
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@ -74,6 +75,13 @@ config MACH_AT91SAM9261EK
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Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
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<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
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config MACH_PM9261
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bool "Ronetix PM9261"
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select HAS_DM9000
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select MACH_HAS_LOWLEVEL_INIT
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help
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Say y here if you are using the Ronetix PM9261 Board
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endchoice
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endif
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