ARM: i.MX: Phytec-phyCARD-i.MX27: Use upstream dts files
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
e632356be4
commit
85c29d2860
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@ -2,7 +2,7 @@
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* Barebox specific DT overlay for Phytec PCA100 RDK
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*/
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#include "imx27-phytec-phycard-s-rdk.dts"
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#include <arm/imx27-phytec-phycard-s-rdk.dts>
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/ {
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chosen {
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@ -1,164 +0,0 @@
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/*
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* Copyright 2012 Markus Pargmann, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx27-phytec-phycard-s-som.dtsi"
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/ {
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model = "Phytec pca100 rapid development kit";
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compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
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display: display {
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model = "Primeview-PD050VL1";
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native-mode = <&timing0>;
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bits-per-pixel = <16>; /* non-standard but required */
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fsl,pcr = <0xf0c88080>; /* non-standard but required */
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display-timings {
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timing0: 640x480 {
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hactive = <640>;
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vactive = <480>;
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hback-porch = <112>;
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hfront-porch = <36>;
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hsync-len = <32>;
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vback-porch = <33>;
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vfront-porch = <33>;
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vsync-len = <2>;
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clock-frequency = <25000000>;
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};
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3v3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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};
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};
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&fb {
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display = <&display>;
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status = "okay";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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rtc@51 {
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compatible = "nxp,pcf8563";
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reg = <0x51>;
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};
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adc@64 {
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compatible = "maxim,max1037";
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vcc-supply = <®_3v3>;
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reg = <0x64>;
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};
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};
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&iomuxc {
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imx27-phycard-s-rdk {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
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MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
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>;
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};
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pinctrl_owire1: owire1grp {
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fsl,pins = <
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MX27_PAD_RTCK__OWIRE 0x0
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>;
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};
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pinctrl_sdhc2: sdhc2grp {
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fsl,pins = <
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MX27_PAD_SD2_CLK__SD2_CLK 0x0
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MX27_PAD_SD2_CMD__SD2_CMD 0x0
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MX27_PAD_SD2_D0__SD2_D0 0x0
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MX27_PAD_SD2_D1__SD2_D1 0x0
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MX27_PAD_SD2_D2__SD2_D2 0x0
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MX27_PAD_SD2_D3__SD2_D3 0x0
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MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX27_PAD_UART1_TXD__UART1_TXD 0x0
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MX27_PAD_UART1_RXD__UART1_RXD 0x0
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MX27_PAD_UART1_CTS__UART1_CTS 0x0
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MX27_PAD_UART1_RTS__UART1_RTS 0x0
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX27_PAD_UART2_TXD__UART2_TXD 0x0
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MX27_PAD_UART2_RXD__UART2_RXD 0x0
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MX27_PAD_UART2_CTS__UART2_CTS 0x0
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MX27_PAD_UART2_RTS__UART2_RTS 0x0
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX27_PAD_UART3_TXD__UART3_TXD 0x0
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MX27_PAD_UART3_RXD__UART3_RXD 0x0
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MX27_PAD_UART3_CTS__UART3_CTS 0x0
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MX27_PAD_UART3_RTS__UART3_RTS 0x0
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>;
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};
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};
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};
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&owire {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_owire1>;
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status = "okay";
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};
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&sdhci2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhc2>;
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cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&uart1 {
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fsl,uart-has-rtscts;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&uart2 {
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fsl,uart-has-rtscts;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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fsl,uart-has-rtscts;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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status = "okay";
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};
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@ -1,103 +0,0 @@
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/*
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* Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
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* and Markus Pargmann, Pengutronix
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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#include "imx27.dtsi"
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/ {
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model = "Phytec pca100";
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compatible = "phytec,imx27-pca100", "fsl,imx27";
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memory {
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reg = <0xa0000000 0x08000000>; /* 128MB */
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};
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};
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&cspi1 {
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
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<&gpio4 27 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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at24@52 {
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compatible = "at,24c32";
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pagesize = <32>;
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reg = <0x52>;
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};
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};
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&iomuxc {
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imx27-phycard-s-som {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX27_PAD_SD3_CMD__FEC_TXD0 0x0
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MX27_PAD_SD3_CLK__FEC_TXD1 0x0
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MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
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MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
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MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
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MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
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MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
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MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
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MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
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MX27_PAD_ATA_DATA7__FEC_MDC 0x0
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MX27_PAD_ATA_DATA8__FEC_CRS 0x0
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MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
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MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
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MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
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MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
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MX27_PAD_ATA_DATA13__FEC_COL 0x0
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MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
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MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
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MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
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>;
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};
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pinctrl_nfc: nfcgrp {
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fsl,pins = <
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MX27_PAD_NFRB__NFRB 0x0
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MX27_PAD_NFCLE__NFCLE 0x0
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MX27_PAD_NFWP_B__NFWP_B 0x0
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MX27_PAD_NFCE_B__NFCE_B 0x0
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MX27_PAD_NFALE__NFALE 0x0
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MX27_PAD_NFRE_B__NFRE_B 0x0
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MX27_PAD_NFWE_B__NFWE_B 0x0
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>;
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};
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};
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};
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&nfc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_nfc>;
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nand-bus-width = <8>;
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nand-ecc-mode = "hw";
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nand-on-flash-bbt;
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status = "okay";
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};
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