clk: tegra: don't bug out on zero PLL postdiv
As the real value is 2^p a input value of 0 is actually valid. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
d95bb6f81f
commit
89b062b430
|
@ -196,8 +196,6 @@ static int _get_table_rate(struct clk *hw,
|
|||
if (sel->input_rate == 0)
|
||||
return -EINVAL;
|
||||
|
||||
BUG_ON(sel->p < 1);
|
||||
|
||||
cfg->input_rate = sel->input_rate;
|
||||
cfg->output_rate = sel->output_rate;
|
||||
cfg->m = sel->m;
|
||||
|
|
Loading…
Reference in New Issue