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Merge branch 'for-next/imx'

This commit is contained in:
Sascha Hauer 2014-07-04 17:19:41 +02:00
parent ca7a800c1f f3127d1c1f
commit 8da9a22b52
57 changed files with 449 additions and 1241 deletions
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2
arch/arm/boards/Makefile
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@ -88,7 +88,7 @@ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += solidrun-hummingboard/
obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/

16
arch/arm/boards/boundarydevices-nitrogen6x/board.c
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@ -29,6 +29,8 @@ static int nitrogen6x_devices_init(void)
imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
BBU_HANDLER_FLAG_DEFAULT);
barebox_set_hostname("nitrogen6x");
return 0;
}
device_initcall(nitrogen6x_devices_init);
@ -61,17 +63,3 @@ static int nitrogen6x_coredevices_init(void)
return 0;
}
coredevice_initcall(nitrogen6x_coredevices_init);
static int nitrogen6x_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6dl-nitrogen6x") &&
!of_machine_is_compatible("fsl,imx6q-nitrogen6x"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("nitrogen6x");
return 0;
}
postcore_initcall(nitrogen6x_postcore_init);

6
arch/arm/boards/boundarydevices-nitrogen6x/env/config-board vendored
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@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc1,115200"

15
arch/arm/boards/datamodul-edm-qmx6/board.c
View File

@ -135,19 +135,8 @@ static int realq7_device_init(void)
break;
}
barebox_set_hostname("eDM-QMX6");
return 0;
}
device_initcall(realq7_device_init);
static int realq7_postcore_init(void)
{
if (!of_machine_is_compatible("dmo,imx6q-edmqmx6"))
return 0;
barebox_set_hostname("eDM-QMX6");
imx6_init_lowlevel();
return 0;
}
postcore_initcall(realq7_postcore_init);

6
arch/arm/boards/datamodul-edm-qmx6/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc1,115200"

8
arch/arm/boards/efika-mx-smartbook/env/config-board vendored
View File

@ -1,8 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc0,115200"
[ -f /env/config ] && /env/config

15
arch/arm/boards/embest-riotboard/board.c
View File

@ -72,19 +72,8 @@ static int riotboard_device_init(void)
imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc3.barebox",
BBU_HANDLER_FLAG_DEFAULT);
barebox_set_hostname("riotboard");
return 0;
}
device_initcall(riotboard_device_init);
static int riotboard_lwl_init(void)
{
if (!of_machine_is_compatible("embest,riotboard"))
return 0;
barebox_set_hostname("riotboard");
imx6_init_lowlevel();
return 0;
}
postcore_initcall(riotboard_lwl_init);

2
arch/arm/boards/freescale-mx51-babbage/board.c
View File

@ -157,6 +157,8 @@ static int imx51_babbage_init(void)
if (!of_machine_is_compatible("fsl,imx51-babbage"))
return 0;
barebox_set_hostname("babbage");
mc13xxx_register_init_callback(babbage_power_init);
armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE);

7
arch/arm/boards/freescale-mx51-babbage/env/config-board vendored
View File

@ -1,7 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=babbage
global.linux.bootargs.base="console=ttymxc0,115200"

6
arch/arm/boards/freescale-mx53-qsb/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc0,115200"

7
arch/arm/boards/freescale-mx53-vmx53/env/config-board vendored
View File

@ -1,7 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=vmx53
global.linux.bootargs.base="console=ttymxc0,115200"

2
arch/arm/boards/freescale-mx6-arm2/board.c
View File

@ -147,8 +147,6 @@ static int arm2_console_init(void)
{
mxc_iomux_v3_setup_multiple_pads(arm2_pads, ARRAY_SIZE(arm2_pads));
imx6_init_lowlevel();
barebox_set_model("Freescale i.MX6 Armadillo2");
barebox_set_hostname("armadillo2");

13
arch/arm/boards/freescale-mx6-sabrelite/board.c
View File

@ -179,20 +179,9 @@ static int sabrelite_coredevices_init(void)
phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
ksz9021rn_phy_fixup);
return 0;
}
coredevice_initcall(sabrelite_coredevices_init);
static int sabrelite_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabrelite") &&
!of_machine_is_compatible("fsl,imx6dl-sabrelite"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("sabrelite");
return 0;
}
postcore_initcall(sabrelite_postcore_init);
coredevice_initcall(sabrelite_coredevices_init);

6
arch/arm/boards/freescale-mx6-sabrelite/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc1,115200"

14
arch/arm/boards/freescale-mx6-sabresd/board.c
View File

@ -69,6 +69,7 @@ static int sabresd_devices_init(void)
return 0;
armlinux_set_architecture(3980);
barebox_set_hostname("sabresd");
return 0;
}
@ -89,16 +90,3 @@ static int sabresd_coredevices_init(void)
* gpios are available.
*/
coredevice_initcall(sabresd_coredevices_init);
static int sabresd_postcore_init(void)
{
if (!of_machine_is_compatible("fsl,imx6q-sabresd"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("sabresd");
return 0;
}
postcore_initcall(sabresd_postcore_init);

6
arch/arm/boards/freescale-mx6-sabresd/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc0,115200"

15
arch/arm/boards/gk802/board.c
View File

@ -69,19 +69,8 @@ static int gk802_env_init(void)
devfs_add_partition(bootsource_name, 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, barebox_name);
devfs_add_partition(bootsource_name, SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, default_environment_name);
barebox_set_hostname("gk802");
return 0;
}
late_initcall(gk802_env_init);
static int gk802_console_init(void)
{
if (!of_machine_is_compatible("zealz,imx6q-gk802"))
return 0;
barebox_set_hostname("gk802");
imx6_init_lowlevel();
return 0;
}
postcore_initcall(gk802_console_init);

11
arch/arm/boards/guf-santaro/board.c
View File

@ -26,17 +26,6 @@
#include <mach/bbu.h>
#include <mach/imx6.h>
static int santaro_postcore_init(void)
{
if (!of_machine_is_compatible("guf,imx6q-santaro"))
return 0;
imx6_init_lowlevel();
return 0;
}
postcore_initcall(santaro_postcore_init);
static int santaro_device_init(void)
{
uint32_t flag_sd = 0, flag_emmc = 0;

7
arch/arm/boards/karo-tx25/env/init/config-board vendored
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@ -1,7 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.hostname=tx25
global.linux.bootargs.base="console=ttymxc0,115200"

6
arch/arm/boards/karo-tx53/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc0,115200"

11
arch/arm/boards/phytec-phycard-imx6/board.c
View File

@ -47,14 +47,3 @@ static int phytec_pcaaxl3_init(void)
return 0;
}
device_initcall(phytec_pcaaxl3_init);
static int phytec_pcaaxl3_core_init(void)
{
if (!of_machine_is_compatible("phytec,imx6q-pcaaxl3"))
return 0;
imx6_init_lowlevel();
return 0;
}
postcore_initcall(phytec_pcaaxl3_core_init);

6
arch/arm/boards/phytec-phycore-imx27/Makefile
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@ -1,3 +1,3 @@
obj-y += pcm038.o
lwl-y += lowlevel.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970.o
obj-y += pcm038.o pcm970.o
lwl-y += lowlevel.o
bbenv-y += defaultenv-pcm038

0
arch/arm/boards/phytec-phycore-imx27/env/boot/nand-ubi → arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nand-ubi
View File

9
arch/arm/boards/phytec-phycore-imx27/defaultenv-pcm038/boot/nor Normal file
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@ -0,0 +1,9 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "nor"
exit
fi
global.bootm.image="/dev/nor0.kernel"
global.linux.bootargs.dyn.root="root=/dev/mtdblock3 ro"

6
arch/arm/boards/phytec-phycore-imx27/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc0,115200"

11
arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nand vendored
View File

@ -1,11 +0,0 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "NAND partitions"
exit
fi
mtdparts="512k(nand0.barebox)ro,128k(nand0.bareboxenv),4M(nand0.kernel),-(nand0.root)"
kernelname="mxc_nand"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}

11
arch/arm/boards/phytec-phycore-imx27/env/init/mtdparts-nor vendored
View File

@ -1,11 +0,0 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "NOR partitions"
exit
fi
mtdparts="512k(nor0.barebox)ro,128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
kernelname="physmap-flash.0"
mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}

24
arch/arm/boards/phytec-phycore-imx27/lowlevel.c
View File

@ -33,7 +33,7 @@
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
void __bare_init __naked barebox_arm_reset_vector(void)
static void __bare_init __naked noinline phytec_phycorce_imx27_common_init(void *fdt)
{
uint32_t r;
int i;
@ -93,12 +93,22 @@ void __bare_init __naked barebox_arm_reset_vector(void)
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL,
MX27_ESDCTL_BASE_ADDR + IMX_ESDCTL0);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND)) {
/* setup a stack to be able to call mx27_barebox_boot_nand_external() */
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 8);
if (IS_ENABLED(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND))
imx27_barebox_boot_nand_external(fdt);
imx27_barebox_boot_nand_external(0);
}
out:
imx27_barebox_entry(NULL);
imx27_barebox_entry(fdt);
}
extern char __dtb_imx27_phytec_phycore_rdk_start[];
ENTRY_FUNCTION(start_phytec_phycore_imx27, r0, r1, r2)
{
void *fdt;
arm_setup_stack(MX27_IRAM_BASE_ADDR + MX27_IRAM_SIZE - 12);
fdt = __dtb_imx27_phytec_phycore_rdk_start - get_runtime_offset();
phytec_phycorce_imx27_common_init(fdt);
}

432
arch/arm/boards/phytec-phycore-imx27/pcm038.c
View File

@ -10,79 +10,30 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
*/
#define pr_fmt(fmt) "pcm038: " fmt
#include <common.h>
#include <bootsource.h>
#include <net.h>
#include <init.h>
#include <environment.h>
#include <mach/imx27-regs.h>
#include <fec.h>
#include <sizes.h>
#include <notifier.h>
#include <common.h>
#include <gpio.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
#include <nand.h>
#include <spi/spi.h>
#include <init.h>
#include <io.h>
#include <mach/imx-nand.h>
#include <mach/imx-pll.h>
#include <mach/weim.h>
#include <mach/imxfb.h>
#include <i2c/i2c.h>
#include <mach/spi.h>
#include <mach/iomux-mx27.h>
#include <notifier.h>
#include <sizes.h>
#include <envfs.h>
#include <mach/devices-imx27.h>
#include <mach/iim.h>
#include <mach/imx-pll.h>
#include <mach/imx27-regs.h>
#include <mach/imxfb.h>
#include <mach/iomux-mx27.h>
#include <mfd/mc13xxx.h>
#include <mach/generic.h>
#include <mach/bbu.h>
#include "pll.h"
#define PCM038_GPIO_PMIC_IRQ (GPIO_PORTB + 23)
#define PCM038_GPIO_FEC_RST (GPIO_PORTC + 30)
#define PCM970_GPIO_SPI_CS1 (GPIO_PORTD + 27)
#define PCM038_GPIO_SPI_CS0 (GPIO_PORTD + 28)
#define PCM038_GPIO_OTG_STP (GPIO_PORTE + 1)
static struct fec_platform_data fec_info = {
.xcv_type = PHY_INTERFACE_MODE_MII,
.phy_addr = 1,
};
static int pcm038_spi_cs[] = {
PCM038_GPIO_SPI_CS0,
#ifdef CONFIG_MACH_PCM970_BASEBOARD
PCM970_GPIO_SPI_CS1,
#endif
};
static struct spi_imx_master pcm038_spi_0_data = {
.chipselect = pcm038_spi_cs,
.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
};
static struct spi_board_info pcm038_spi_board_info[] = {
{
.name = "mc13783",
.bus_num = 0,
.chip_select = 0,
}
};
static struct imx_nand_platform_data nand_info = {
.width = 1,
.hw_ecc = 1,
.flash_bbt = 1,
};
static struct imx_fb_videomode imxfb_mode = {
.mode = {
.name = "Sharp-LQ035Q7",
@ -106,51 +57,96 @@ static struct imx_fb_videomode imxfb_mode = {
* - data enable low active
* - enable sharp mode
*/
.pcr = 0xF00080C0,
.pcr = 0xf00080c0,
.bpp = 16,
};
static struct imx_fb_platform_data pcm038_fb_data = {
.mode = &imxfb_mode,
.num_modes = 1,
.pwmr = 0x00A903FF,
.pwmr = 0x00a903ff,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
/**
* The spctl0 register is a beast: Seems you can read it
* only one times without writing it again.
*/
static inline uint32_t get_pll_spctl10(void)
static const unsigned int pcm038_pins[] = {
/* Display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB */
PE1_PF_USBOTG_STP,
};
static int pcm038_init(void)
{
uint32_t reg;
reg = readl(MX27_CCM_BASE_ADDR + MX27_SPCTL0);
writel(reg, MX27_CCM_BASE_ADDR + MX27_SPCTL0);
return reg;
}
/**
* If the PLL settings are in place switch the CPU core frequency to the max. value
*/
static int pcm038_power_init(void)
{
uint32_t spctl0 = get_pll_spctl10();
struct mc13xxx *mc13xxx = mc13xxx_get();
char *envdev;
uint32_t i, bbu_nand_flags = 0, bbu_nor_flags = 0;
/* PLL registers already set to their final values? */
if (spctl0 == SPCTL0_VAL &&
readl(MX27_CCM_BASE_ADDR + MX27_MPCTL0) == MPCTL0_VAL) {
console_flush();
if (mc13xxx) {
mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
if (!of_machine_is_compatible("phytec,imx27-pcm038"))
return 0;
/* Apply delay for STP line to stop ULPI */
imx_gpio_mode(PCM038_GPIO_OTG_STP | GPIO_GPIO);
gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
mdelay(1);
for (i = 0; i < ARRAY_SIZE(pcm038_pins); i++)
imx_gpio_mode(pcm038_pins[i]);
imx27_add_fb(&pcm038_fb_data);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
of_device_enable_path("/chosen/environment-nand");
bbu_nand_flags |= BBU_HANDLER_FLAG_DEFAULT;
envdev = "NAND";
break;
default:
of_device_enable_path("/chosen/environment-nor");
bbu_nor_flags |= BBU_HANDLER_FLAG_DEFAULT;
envdev = "NOR";
break;
}
pr_notice("Using environment in %s Flash\n", envdev);
if (!mc13xxx) {
pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n");
return 0;
}
mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(0),
MC13783_SWX_VOLTAGE(MC13783_SWX_VOLTAGE_1_450) |
MC13783_SWX_VOLTAGE_DVS(MC13783_SWX_VOLTAGE_1_450) |
MC13783_SWX_VOLTAGE_STANDBY(MC13783_SWX_VOLTAGE_1_450));
mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
mc13xxx_reg_write(mc13xxx, MC13783_REG_SWITCHERS(4),
MC13783_SW1A_MODE(MC13783_SWX_MODE_NO_PULSE_SKIP) |
MC13783_SW1A_MODE_STANDBY(MC13783_SWX_MODE_NO_PULSE_SKIP) |
MC13783_SW1A_SOFTSTART |
@ -159,246 +155,36 @@ static int pcm038_power_init(void)
MC13783_SW1B_SOFTSTART |
MC13783_SW_PLL_FACTOR(32));
/* Setup VMMC voltage */
if (IS_ENABLED(CONFIG_MCI_IMX)) {
u32 val;
mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_SETTING(1), &val);
/* VMMC1 = 3.00 V */
val &= ~(7 << 6);
val |= 6 << 6;
mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_SETTING(1), val);
mc13xxx_reg_read(mc13xxx, MC13783_REG_REG_MODE(1), &val);
/* Enable VMMC1 */
val |= 1 << 18;
mc13xxx_reg_write(mc13xxx, MC13783_REG_REG_MODE(1), val);
}
/* wait for required power level to run the CPU at 400 MHz */
udelay(100000);
writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR);
writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
} else {
pr_err("Failed to initialize PMIC. Will continue with low CPU speed\n");
}
if (IS_ENABLED(CONFIG_MCI_IMX)) {
/* VMMC1 = 3.00 V */
mc13xxx_set_bits(mc13xxx, MC13783_REG_REG_SETTING(1),
7 << 6, 6 << 6);
/* Enable VMMC */
mc13xxx_set_bits(mc13xxx, MC13783_REG_REG_MODE(1),
1 << 18, 1 << 18);
}
/* clock gating enable */
/* Wait for required power level to run the CPU at 400 MHz */
mdelay(100);
console_flush();
writel(CSCR_VAL_FINAL, MX27_CCM_BASE_ADDR + MX27_CSCR);
writel(0x130410c3, MX27_CCM_BASE_ADDR + MX27_PCDR0);
writel(0x09030911, MX27_CCM_BASE_ADDR + MX27_PCDR1);
/* Clocks have changed. Notify clients */
clock_notifier_call_chain();
/* Clock gating enable */
writel(0x00050f08, MX27_SYSCTRL_BASE_ADDR + MX27_GPCR);
return 0;
}
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.boot",
bbu_nand_flags);
imx_bbu_external_nor_register_handler("nor", "/dev/nor0.boot",
bbu_nor_flags);
struct imxusb_platformdata pcm038_otg_pdata = {
.mode = IMX_USB_MODE_DEVICE,
.flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI,
};
static const struct devfs_partition pcm038_nand0_partitions[] = {
{
.offset = 0,
.size = SZ_512K,
.flags = DEVFS_PARTITION_FIXED,
.name = "self_raw",
.bbname = "self0",
}, {
.offset = DEVFS_PARTITION_APPEND, /* 512 KiB */
.size = SZ_128K,
.flags = DEVFS_PARTITION_FIXED,
.name = "env_raw",
.bbname = "env0",
}, {
/* sentinel */
}
};
static const struct devfs_partition pcm038_nor0_partitions[] = {
{
.offset = 0,
.size = SZ_512K,
.flags = DEVFS_PARTITION_FIXED,
.name = "self0",
}, {
.offset = DEVFS_PARTITION_APPEND, /* 512 KiB */
.size = SZ_128K,
.flags = DEVFS_PARTITION_FIXED,
.name = "env0",
}, {
/* sentinel */
}
};
static int pcm038_devices_init(void)
{
int i;
u64 uid = 0;
char *envdev;
long sram_size;
unsigned int mode[] = {
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* CSPI1 */
PD25_PF_CSPI1_RDY,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* Display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB OTG */
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* I2C1 */
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
/* Misc */
PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT,
PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT,
#ifdef CONFIG_MACH_PCM970_BASEBOARD
PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT,
#endif
PCM038_GPIO_PMIC_IRQ | GPIO_GPIO | GPIO_IN,
};
/* configure 16 bit nor flash on cs0 */
imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900);
/* configure SRAM on cs1 */
imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
/* SRAM can be up to 2MiB */
sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M);
if (sram_size)
add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size,
IORESOURCE_MEM_WRITEABLE);
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
pcm038_power_init();
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
gpio_set_value(PCM038_GPIO_FEC_RST, 1);
imx27_add_fec(&fec_info);
/* Apply delay for STP line to stop ULPI */
gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
mdelay(1);
imx_gpio_mode(PE1_PF_USBOTG_STP);
if (IS_ENABLED(CONFIG_USB_GADGET_DRIVER_ARC))
imx27_add_usbotg(&pcm038_otg_pdata);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_create_partitions("nand0", pcm038_nand0_partitions);
envdev = "NAND";
break;
default:
devfs_create_partitions("nor0", pcm038_nor0_partitions);
protect_file("/dev/env0", 1);
envdev = "NOR";
}
pr_notice("Using environment in %s Flash\n", envdev);
if (imx_iim_read(1, 0, &uid, 6) == 6)
armlinux_set_serial(uid);
armlinux_set_architecture(MACH_TYPE_PCM038);
defaultenv_append_directory(defaultenv_pcm038);
return 0;
}
device_initcall(pcm038_devices_init);
static int pcm038_console_init(void)
{
barebox_set_model("Phytec phyCORE-i.MX27");
barebox_set_hostname("phycore-imx27");
imx27_add_uart0();
return 0;
}
console_initcall(pcm038_console_init);
device_initcall(pcm038_init);

208
arch/arm/boards/phytec-phycore-imx27/pcm970.c
View File

@ -12,27 +12,20 @@
*/
#include <common.h>
#include <io.h>
#include <init.h>
#include <sizes.h>
#include <gpio.h>
#include <init.h>
#include <io.h>
#include <platform_ide.h>
#include <sizes.h>
#include <mach/imx27-regs.h>
#include <mach/iomux-mx27.h>
#include <mach/weim.h>
#include <mach/devices-imx27.h>
#include <usb/chipidea-imx.h>
#define GPIO_IDE_POWER (GPIO_PORTE + 18)
#define GPIO_IDE_PCOE (GPIO_PORTF + 7)
#define GPIO_IDE_RESET (GPIO_PORTF + 10)
static struct resource pcm970_ide_resources[] = {
{
.start = MX27_PCMCIA_MEM_BASE_ADDR,
.end = MX27_PCMCIA_MEM_BASE_ADDR + SZ_1K - 1,
.flags = IORESOURCE_MEM,
},
DEFINE_RES_MEM(MX27_PCMCIA_MEM_BASE_ADDR, SZ_1K),
};
static void pcm970_ide_reset(int state)
@ -54,142 +47,83 @@ static struct device_d pcm970_ide_device = {
.platform_data = &pcm970_ide_pdata,
};
static void pcm970_ide_init(void)
{
uint32_t i;
unsigned int mode[] = {
/* PCMCIA */
PF20_PF_PC_CD1,
PF19_PF_PC_CD2,
PF18_PF_PC_WAIT,
PF17_PF_PC_READY,
PF16_PF_PC_PWRON,
PF14_PF_PC_VS1,
PF13_PF_PC_VS2,
PF12_PF_PC_BVD1,
PF11_PF_PC_BVD2,
PF9_PF_PC_IOIS16,
PF8_PF_PC_RW,
GPIO_IDE_PCOE | GPIO_GPIO | GPIO_OUT, /* PCOE */
GPIO_IDE_RESET | GPIO_GPIO | GPIO_OUT, /* Reset */
GPIO_IDE_POWER | GPIO_GPIO | GPIO_OUT, /* Power */
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i] | GPIO_PUEN);
/* Always set PCOE signal to low */
gpio_set_value(GPIO_IDE_PCOE, 0);
/* Assert RESET line */
gpio_set_value(GPIO_IDE_RESET, 0);
/* Power up CF-card (Also switched on User-LED) */
gpio_set_value(GPIO_IDE_POWER, 1);
mdelay(10);
/* Reset PCMCIA Status Change Register */
writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR);
mdelay(10);
/* Check PCMCIA Input Pins Register for Card Detect & Power */
if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) &
((1 << 8) | (3 << 3))) != (1 << 8)) {
printf("CompactFlash card not found. Driver not enabled.\n");
return;
}
/* Disable all interrupts */
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER);
/* Disable all PCMCIA banks */
for (i = 0; i < 5; i++)
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(i));
/* Not use internal PCOE */
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR);
/* Setup PCMCIA bank0 for Common memory mode */
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0));
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0));
writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf,
MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
/* Clear PCMCIA General Status Register */
writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR);
/* Make PCMCIA bank0 valid */
i = readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
writel(i | (1 << 29), MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
platform_device_register(&pcm970_ide_device);
}
static void pcm970_mmc_init(void)
{
uint32_t i;
unsigned int mode[] = {
/* SD2 */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
imx27_add_mmc1(NULL);
}
struct imxusb_platformdata pcm970_usbh2_pdata = {
.flags = MXC_EHCI_MODE_ULPI | MXC_EHCI_INTERFACE_DIFF_UNI,
.mode = IMX_USB_MODE_HOST,
static const unsigned int pcmcia_pins[] = {
PF20_PF_PC_CD1,
PF19_PF_PC_CD2,
PF18_PF_PC_WAIT,
PF17_PF_PC_READY,
PF16_PF_PC_PWRON,
PF14_PF_PC_VS1,
PF13_PF_PC_VS2,
PF12_PF_PC_BVD1,
PF11_PF_PC_BVD2,
PF9_PF_PC_IOIS16,
PF8_PF_PC_RW,
GPIO_IDE_PCOE | GPIO_GPIO | GPIO_OUT, /* PCOE */
GPIO_IDE_RESET | GPIO_GPIO | GPIO_OUT, /* Reset */
GPIO_IDE_POWER | GPIO_GPIO | GPIO_OUT, /* Power */
};
static int pcm970_init(void)
{
int i;
unsigned int mode[] = {
/* USB Host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
4 | GPIO_PORTA | GPIO_GPIO | GPIO_OUT,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
if (!of_machine_is_compatible("phytec,imx27-pcm970"))
return 0;
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
if (IS_ENABLED(CONFIG_DISK_INTF_PLATFORM_IDE)) {
uint32_t i;
/* Configure SJA1000 on cs4 */
imx27_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
for (i = 0; i < ARRAY_SIZE(pcmcia_pins); i++)
imx_gpio_mode(pcmcia_pins[i] | GPIO_PUEN);
if (IS_ENABLED(CONFIG_USB)) {
/* Stop ULPI */
gpio_direction_output(4, 1);
mdelay(1);
imx_gpio_mode(PA4_PF_USBH2_STP);
/* Always set PCOE signal to low */
gpio_set_value(GPIO_IDE_PCOE, 0);
imx27_add_usbh2(&pcm970_usbh2_pdata);
/* Assert RESET line */
gpio_set_value(GPIO_IDE_RESET, 0);
/* Power up CF-card (Also switched on User-LED) */
gpio_set_value(GPIO_IDE_POWER, 1);
mdelay(10);
/* Reset PCMCIA Status Change Register */
writel(0x00000fff, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PSCR);
mdelay(10);
/* Check PCMCIA Input Pins Register for Card Detect & Power */
if ((readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PIPR) &
((1 << 8) | (3 << 3))) != (1 << 8)) {
printf("CF card not found. Driver not enabled.\n");
return 0;
}
/* Disable all interrupts */
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PER);
/* Disable all PCMCIA banks */
for (i = 0; i < 5; i++)
writel(0, MX27_PCMCIA_CTL_BASE_ADDR +
MX27_PCMCIA_POR(i));
/* Not use internal PCOE */
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGCR);
/* Setup PCMCIA bank0 for Common memory mode */
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PBR(0));
writel(0, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POFR(0));
writel((0 << 25) | (17 << 17) | (4 << 11) | (3 << 5) | 0xf,
MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
/* Clear PCMCIA General Status Register */
writel(0x0000001f, MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_PGSR);
/* Make PCMCIA bank0 valid */
i = readl(MX27_PCMCIA_CTL_BASE_ADDR + MX27_PCMCIA_POR(0));
writel(i | (1 << 29), MX27_PCMCIA_CTL_BASE_ADDR +
MX27_PCMCIA_POR(0));
platform_device_register(&pcm970_ide_device);
}
if (IS_ENABLED(CONFIG_DISK_INTF_PLATFORM_IDE))
pcm970_ide_init();
if (IS_ENABLED(CONFIG_MCI_IMX))
pcm970_mmc_init();
return 0;
}
late_initcall(pcm970_init);

11
arch/arm/boards/phytec-phyflex-imx6/board.c
View File

@ -105,14 +105,3 @@ static int phytec_pfla02_init(void)
return 0;
}
device_initcall(phytec_pfla02_init);
static int phytec_pfla02_core_init(void)
{
if (!of_machine_is_compatible("phytec,imx6x-pbab01"))
return 0;
imx6_init_lowlevel();
return 0;
}
postcore_initcall(phytec_pfla02_core_init);

0
arch/arm/boards/solidrun-hummingboard/Makefile → arch/arm/boards/solidrun-microsom/Makefile
View File

15
arch/arm/boards/solidrun-hummingboard/board.c → arch/arm/boards/solidrun-microsom/board.c
View File

@ -72,6 +72,8 @@ static int hummingboard_device_init(void)
gpio_direction_output(IMX_GPIO_NR(3, 22), 1);
gpio_direction_output(IMX_GPIO_NR(1, 0), 1);
barebox_set_hostname("hummingboard");
return 0;
}
device_initcall(hummingboard_device_init);
@ -87,16 +89,3 @@ static int hummingboard_late_init(void)
return 0;
}
late_initcall(hummingboard_late_init);
static int hummingboard_lwl_init(void)
{
if (!of_machine_is_compatible("solidrun,hummingboard"))
return 0;
barebox_set_hostname("hummingboard");
imx6_init_lowlevel();
return 0;
}
postcore_initcall(hummingboard_lwl_init);

0
arch/arm/boards/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg → arch/arm/boards/solidrun-microsom/flash-header-solidrun-hummingboard.imxcfg
View File

0
arch/arm/boards/solidrun-hummingboard/lowlevel.c → arch/arm/boards/solidrun-microsom/lowlevel.c
View File

6
arch/arm/boards/tqma53/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc1,115200"

13
arch/arm/boards/tqma6x/board.c
View File

@ -113,17 +113,8 @@ static int tqma6x_env_init(void)
default_environment_path_set("/dev/mmc2.boot1");
barebox_set_hostname("mba6x");
return 0;
}
late_initcall(tqma6x_env_init);
static int tqma6x_core_init(void)
{
if (!of_machine_is_compatible("tq,mba6x"))
return 0;
imx6_init_lowlevel();
return 0;
}
postcore_initcall(tqma6x_core_init);

14
arch/arm/boards/udoo/board.c
View File

@ -164,6 +164,7 @@ static int udoo_devices_init(void)
udoo_epit_init();
armlinux_set_bootparams((void *)0x10000100);
barebox_set_hostname("udoo");
return 0;
}
@ -179,16 +180,3 @@ static int udoo_coredevices_init(void)
return 0;
}
coredevice_initcall(udoo_coredevices_init);
static int udoo_postcore_init(void)
{
if (!of_machine_is_compatible("udoo,imx6qdl-udoo"))
return 0;
imx6_init_lowlevel();
barebox_set_hostname("udoo");
return 0;
}
postcore_initcall(udoo_postcore_init);

6
arch/arm/boards/udoo/env/config-board vendored
View File

@ -1,6 +0,0 @@
#!/bin/sh
# board defaults, do not change in running system. Change /env/config
# instead
global.linux.bootargs.base="console=ttymxc1,115200"

13
arch/arm/boards/variscite-mx6/board.c
View File

@ -120,16 +120,3 @@ static int variscite_custom_init(void)
return 0;
}
device_initcall(variscite_custom_init);
static int variscite_custom_core_init(void)
{
if (!of_machine_is_compatible("variscite,imx6q-custom"))
return 0;
imx6_init_lowlevel();
pr_debug("Completing custom_core_init()\n");
return 0;
}
postcore_initcall(variscite_custom_core_init);

81
arch/arm/configs/freescale-mx51-babbage_defconfig
View File

@ -1,81 +0,0 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_FREESCALE_MX51_PDK=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx51-babbage/env/"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NET_RESOLV=y
CONFIG_OFDEVICE=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_MTD=y
CONFIG_MTD_DATAFLASH=y
CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_MFD_MC13XXX=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y

117
arch/arm/configs/freescale-mx53-qsb_defconfig
View File

@ -1,117 +0,0 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_FREESCALE_MX53_LOCO=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x0
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx53-qsb/env/"
CONFIG_RESET_SOURCE=y
CONFIG_DEBUG_INFO=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_LET=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_PASSWD=y
CONFIG_PASSWD_MODE_STAR=y
CONFIG_CMD_TIME=y
CONFIG_CMD_LN=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_SHA256SUM=y
CONFIG_CMD_SHA224SUM=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_BOOTM_AIMAGE=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_CMD_WD=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_NET_NFS=y
CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_OFDEVICE=y
CONFIG_SMSC_PHY=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
CONFIG_NET_USB_SMSC95XX=y
# CONFIG_SPI is not set
CONFIG_I2C=y
CONFIG_I2C_IMX=y
CONFIG_DISK_AHCI=y
CONFIG_DISK_AHCI_IMX=y
CONFIG_USB=y
CONFIG_USB_IMX_CHIPIDEA=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_MFD_MC13XXX=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y
CONFIG_LED_TRIGGERS=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y

84
arch/arm/configs/freescale-mx6-sabrelite_defconfig
View File

@ -1,84 +0,0 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_SABRELITE=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_MALLOC_SIZE=0x4000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx6-sabrelite/env"
CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_LN=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_BOOTM_AIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_CLK=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_OFDEVICE=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_MTD=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_STORAGE=y
CONFIG_MCI=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y
CONFIG_LZO_DECOMPRESS=y

71
arch/arm/configs/freescale-mx6-sabresd_defconfig
View File

@ -1,71 +0,0 @@
CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_SABRESD=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_THUMB2_BAREBOX=y
CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x08f80000
CONFIG_MALLOC_SIZE=0x4000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/freescale-mx6-sabresd/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_BOOTM_AIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_DRIVER_SPI_IMX=y
CONFIG_MTD=y
CONFIG_MTD_M25P80=y
CONFIG_MTD_SST25L=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_IMX_ESDHC=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y
CONFIG_LZO_DECOMPRESS=y

72
arch/arm/configs/imx_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_ARCH_IMX=y
CONFIG_IMX_MULTI_BOARDS=y
CONFIG_MACH_TX25=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_PCM038=y
CONFIG_IMX_IIM=y
CONFIG_IMX_IIM_FUSE_BLOW=y
CONFIG_AEABI=y
@ -14,7 +15,6 @@ CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_RELOCATABLE=y
CONFIG_PANIC_HANG=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
@ -23,55 +23,56 @@ CONFIG_BLSPEC=y
CONFIG_CONSOLE_ACTIVATE_NONE=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_RESET_SOURCE=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_READF=y
CONFIG_CMD_LET=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENUTREE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_LN=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_MM=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_RESET=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_FILETYPE=y
CONFIG_CMD_LN=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_LET=y
CONFIG_CMD_MSLEEP=y
CONFIG_CMD_READF=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MIITOOL=y
CONFIG_CMD_PING=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_EDIT=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENUTREE=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MM=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DETECT=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIME=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
@ -96,6 +97,7 @@ CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_MCI=y
CONFIG_MCI_IMX=y
CONFIG_MFD_MC13XXX=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y

2
arch/arm/configs/imx_v7_defconfig
View File

@ -15,7 +15,7 @@ CONFIG_MACH_TQMA6X=y
CONFIG_MACH_SABRELITE=y
CONFIG_MACH_SABRESD=y
CONFIG_MACH_NITROGEN6X=y
CONFIG_MACH_SOLIDRUN_HUMMINGBOARD=y
CONFIG_MACH_SOLIDRUN_MICROSOM=y
CONFIG_MACH_EMBEST_RIOTBOARD=y
CONFIG_MACH_UDOO=y
CONFIG_MACH_VARISCITE_MX6=y

77
arch/arm/configs/phytec-phycore-imx27_defconfig
View File

@ -1,77 +0,0 @@
CONFIG_ARCH_IMX=y
CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND=y
CONFIG_ARCH_IMX27=y
CONFIG_MACH_PCM038=y
CONFIG_AEABI=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0xa7f00000
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_MALLOC_TLSF=y
CONFIG_KALLSYMS=y
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phytec-phycore-imx27/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_IOMEM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTM_VERBOSE=y
CONFIG_CMD_BOOTM_INITRD=y
CONFIG_CMD_BOOTM_OFTREE=y
CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y
CONFIG_CMD_UIMAGE=y
# CONFIG_CMD_BOOTU is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_OFTREE=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_SPLASH=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_MAGICVAR=y
CONFIG_CMD_MAGICVAR_HELP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_NET=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_NET_NETCONSOLE=y
CONFIG_NET_RESOLV=y
CONFIG_DRIVER_NET_FEC_IMX=y
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
CONFIG_DRIVER_CFI=y
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_MTD=y
CONFIG_NAND=y
# CONFIG_NAND_ECC_SOFT is not set
# CONFIG_NAND_ECC_HW_SYNDROME is not set
CONFIG_NAND_IMX=y
CONFIG_USB=y
CONFIG_USB_IMX_CHIPIDEA=y
CONFIG_USB_EHCI=y
CONFIG_USB_ULPI=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_DRIVER_VIDEO_IMX=y
CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_ZLIB=y
CONFIG_LZO_DECOMPRESS=y

2
arch/arm/cpu/setupc.S
View File

@ -37,7 +37,6 @@ ENTRY(setup_c)
mov pc, lr
ENDPROC(setup_c)
#ifdef CONFIG_RELOCATABLE
/*
* void relocate_to_adr(unsigned long targetadr)
*
@ -93,4 +92,3 @@ ENTRY(relocate_to_adr)
mov pc, lr
ENDPROC(relocate_to_adr)
#endif

27
arch/arm/cpu/uncompress.c
View File

@ -47,15 +47,27 @@ static void __noreturn noinline uncompress_start_payload(unsigned long membase,
void __noreturn (*barebox)(unsigned long, unsigned long, void *);
uint32_t endmem = membase + memsize;
unsigned long barebox_base;
uint32_t *ptr;
uint32_t *image_end;
void *pg_start;
unsigned long pc = get_pc();
arm_early_mmu_cache_invalidate();
endmem -= STACK_SIZE; /* stack */
if (IS_ENABLED(CONFIG_PBL_RELOCATABLE))
relocate_to_current_adr();
image_end = (void *)ld_var(__image_end) - get_runtime_offset();
if (IS_ENABLED(CONFIG_PBL_RELOCATABLE)) {
/*
* If we run from inside the memory just relocate the binary
* to the current address. Otherwise it may be a readonly location.
* Copy and relocate to the start of the memory in this case.
*/
if (pc > membase && pc < membase + memsize)
relocate_to_current_adr();
else
relocate_to_adr(membase);
}
if (IS_ENABLED(CONFIG_RELOCATABLE))
barebox_base = arm_barebox_image_place(membase + memsize);
@ -74,9 +86,12 @@ static void __noreturn noinline uncompress_start_payload(unsigned long membase,
free_mem_ptr = endmem;
free_mem_end_ptr = free_mem_ptr + SZ_128K;
ptr = (void *)__image_end;
pg_start = ptr + 1;
pg_len = *(ptr);
/*
* image_end is the first location after the executable. It contains
* the size of the appended compressed binary followed by the binary.
*/
pg_start = image_end + 1;
pg_len = *(image_end);
pbl_barebox_uncompress((void*)barebox_base, pg_start, pg_len);

6
arch/arm/dts/Makefile
View File

@ -4,7 +4,8 @@ dtb-$(CONFIG_ARCH_AM33XX) += \
am335x-bone-common.dtb \
am335x-phytec-phycore.dtb
dtb-$(CONFIG_ARCH_IMX25) += imx25-karo-tx25.dtb
dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk-bb.dtb
dtb-$(CONFIG_ARCH_IMX27) += imx27-phytec-phycard-s-rdk-bb.dtb \
imx27-phytec-phycore-rdk.dtb
dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
imx51-genesi-efika-sb.dtb
dtb-$(CONFIG_ARCH_IMX53) += imx53-mba53.dtb \
@ -59,6 +60,7 @@ pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
pbl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o
pbl-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o
pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o
pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o
pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o
@ -67,7 +69,7 @@ pbl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o
pbl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += imx6dl-hummingboard.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o
pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o
pbl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o
pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o

71
arch/arm/dts/imx27-phytec-phycore-rdk.dts Normal file
View File

@ -0,0 +1,71 @@
/*
* Barebox specific DT overlay for Phytec PCM-970 RDK
*/
#include <arm/imx27-phytec-phycore-rdk.dts>
/ {
chosen {
stdout-path = &uart1;
environment-nor {
compatible = "barebox,environment";
device-path = &nor, "partname:env";
status = "disabled";
};
environment-nand {
compatible = "barebox,environment";
device-path = &nfc, "partname:env";
status = "disabled";
};
};
};
&iim {
barebox,provide-mac-address = <&fec 1 0>;
};
&nfc {
partition@0 {
label = "boot";
reg = <0x00000000 0x00080000>;
};
partition@1 {
label = "env";
reg = <0x00080000 0x00020000>;
};
partition@2 {
label = "kernel";
reg = <0x000a0000 0x00400000>;
};
partition@3 {
label = "root";
reg = <0x004a0000 0>;
};
};
&nor {
partition@0 {
label = "boot";
reg = <0x00000000 0x00080000>;
};
partition@1 {
label = "env";
reg = <0x00080000 0x00020000>;
};
partition@2 {
label = "kernel";
reg = <0x000a0000 0x00400000>;
};
partition@3 {
label = "root";
reg = <0x004a0000 0>;
};
};

33
arch/arm/mach-imx/Kconfig
View File

@ -193,6 +193,15 @@ config MACH_PCA100
Say Y here if you are using Phytec's phyCard-i.MX27 (pca100) equipped
with a Freescale i.MX27 Processor
config MACH_PCM038
bool "phyCORE-i.MX27"
select ARCH_IMX27
select HAVE_DEFAULT_ENVIRONMENT_NEW
select ARCH_IMX_EXTERNAL_BOOT_NAND
help
Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
with a Freescale i.MX27 Processor
config MACH_EFIKA_MX_SMARTBOOK
bool "Efika MX smartbook"
select ARCH_IMX51
@ -260,8 +269,8 @@ config MACH_NITROGEN6X
bool "BoundaryDevices Nitrogen6x"
select ARCH_IMX6
config MACH_SOLIDRUN_HUMMINGBOARD
bool "SolidRun Hummingboard"
config MACH_SOLIDRUN_MICROSOM
bool "SolidRun MicroSOM based devices"
select ARCH_IMX6
config MACH_EMBEST_RIOTBOARD
@ -344,26 +353,6 @@ config MACH_IMX27ADS
Say Y here if you are using the Freescale i.MX27ads board equipped
with a Freescale i.MX27 Processor
config MACH_PCM038
bool "phyCORE-i.MX27"
select ARCH_IMX27
select IMX_IIM
select SPI
select DRIVER_SPI_IMX
select MFD_MC13XXX
select HAVE_DEFAULT_ENVIRONMENT_NEW
help
Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
with a Freescale i.MX27 Processor
config MACH_PCM970_BASEBOARD
bool "PHYTEC PCM970 development board"
depends on MACH_PCM038
default y
help
This adds board specific devices that can be found on Phytec's
PCM970 evaluation board.
config MACH_NESO
bool "Garz+Fricke Neso"
select ARCH_IMX27

46
arch/arm/mach-imx/imx-bbu-internal.c
View File

@ -59,7 +59,16 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler,
return fd;
if (imx_handler->flags & IMX_INTERNAL_FLAG_ERASE) {
debug("%s: eraseing %s from 0 to 0x%08x\n", __func__,
debug("%s: unprotecting %s from 0 to 0x%08x\n", __func__,
data->devicefile, image_len);
ret = protect(fd, image_len, 0, 0);
if (ret && ret != -ENOSYS) {
printf("unprotecting %s failed with %s\n", data->devicefile,
strerror(-ret));
goto err_close;
}
debug("%s: erasing %s from 0 to 0x%08x\n", __func__,
data->devicefile, image_len);
ret = erase(fd, image_len, 0);
if (ret) {
@ -92,6 +101,16 @@ static int imx_bbu_write_device(struct imx_internal_bbu_handler *imx_handler,
if (ret < 0)
goto err_close;
if (imx_handler->flags & IMX_INTERNAL_FLAG_ERASE) {
debug("%s: protecting %s from 0 to 0x%08x\n", __func__,
data->devicefile, image_len);
ret = protect(fd, image_len, 0, 1);
if (ret && ret != -ENOSYS) {
printf("protecting %s failed with %s\n", data->devicefile,
strerror(-ret));
}
}
ret = 0;
err_close:
@ -351,6 +370,19 @@ static int imx_bbu_internal_v2_update(struct bbu_handler *handler, struct bbu_da
return ret;
}
static int imx_bbu_external_update(struct bbu_handler *handler, struct bbu_data *data)
{
struct imx_internal_bbu_handler *imx_handler =
container_of(handler, struct imx_internal_bbu_handler, handler);
int ret;
ret = imx_bbu_check_prereq(data);
if (ret)
return ret;
return imx_bbu_write_device(imx_handler, data, data->image, data->len);
}
static struct imx_internal_bbu_handler *__init_handler(const char *name, char *devicefile,
unsigned long flags)
{
@ -484,3 +516,15 @@ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefil
return __register_handler(imx_handler);
}
int imx_bbu_external_nor_register_handler(const char *name, char *devicefile,
unsigned long flags)
{
struct imx_internal_bbu_handler *imx_handler;
imx_handler = __init_handler(name, devicefile, flags);
imx_handler->flags = IMX_INTERNAL_FLAG_ERASE;
imx_handler->handler.handler = imx_bbu_external_update;
return __register_handler(imx_handler);
}

14
arch/arm/mach-imx/imx6.c
View File

@ -114,6 +114,8 @@ int imx6_init(void)
u32 rev;
u32 mx6_silicon_revision;
imx6_init_lowlevel();
imx6_boot_save_loc((void *)MX6_SRC_BASE_ADDR);
rev = readl(MX6_ANATOP_BASE_ADDR + SI_REV);
@ -130,6 +132,18 @@ int imx6_init(void)
mx6_silicon_revision = IMX_CHIP_REV_1_2;
break;
case 0x03:
mx6_silicon_revision = IMX_CHIP_REV_1_3;
break;
case 0x04:
mx6_silicon_revision = IMX_CHIP_REV_1_4;
break;
case 0x05:
mx6_silicon_revision = IMX_CHIP_REV_1_5;
break;
default:
mx6_silicon_revision = IMX_CHIP_REV_UNKNOWN;
}

9
arch/arm/mach-imx/include/mach/bbu.h
View File

@ -29,6 +29,9 @@ int imx6_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefil
int imx6_bbu_nand_register_handler(const char *name, unsigned long flags);
int imx_bbu_external_nor_register_handler(const char *name, char *devicefile,
unsigned long flags);
#else
static inline int imx51_bbu_internal_mmc_register_handler(const char *name, char *devicefile,
@ -71,6 +74,12 @@ static inline int imx6_bbu_nand_register_handler(const char *name, unsigned long
{
return -ENOSYS;
}
static inline int imx_bbu_external_nor_register_handler(const char *name, char *devicefile,
unsigned long flags)
{
return -ENOSYS;
}
#endif
#if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)

2
arch/arm/mach-imx/include/mach/revision.h
View File

@ -6,6 +6,8 @@
#define IMX_CHIP_REV_1_1 0x11
#define IMX_CHIP_REV_1_2 0x12
#define IMX_CHIP_REV_1_3 0x13
#define IMX_CHIP_REV_1_4 0x14
#define IMX_CHIP_REV_1_5 0x15
#define IMX_CHIP_REV_2_0 0x20
#define IMX_CHIP_REV_2_1 0x21
#define IMX_CHIP_REV_2_2 0x22

10
images/Makefile.imx
View File

@ -23,6 +23,10 @@ pblx-$(CONFIG_MACH_PCA100) += start_phytec_phycard_imx27
FILE_barebox-phytec-phycard-imx27.img = start_phytec_phycard_imx27.pblx
image-$(CONFIG_MACH_PCA100) += barebox-phytec-phycard-imx27.img
pblx-$(CONFIG_MACH_PCM038) += start_phytec_phycore_imx27
FILE_barebox-phytec-phycore-imx27.img = start_phytec_phycore_imx27.pblx
image-$(CONFIG_MACH_PCM038) += barebox-phytec-phycore-imx27.img
# ----------------------- i.MX51 based boards ---------------------------
pblx-$(CONFIG_MACH_FREESCALE_MX51_PDK) += start_imx51_babbage
CFG_start_imx51_babbage.pblx.imximg = $(board)/freescale-mx51-babbage/flash-header-imx51-babbage.imxcfg
@ -146,10 +150,10 @@ CFG_start_imx6q_sabresd.pblx.imximg = $(board)/freescale-mx6-sabresd/flash-heade
FILE_barebox-freescale-imx6q-sabresd.img = start_imx6q_sabresd.pblx.imximg
image-$(CONFIG_MACH_SABRESD) += barebox-freescale-imx6q-sabresd.img
pblx-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += start_imx6dl_hummingboard
CFG_start_imx6dl_hummingboard.pblx.imximg = $(board)/solidrun-hummingboard/flash-header-solidrun-hummingboard.imxcfg
pblx-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += start_imx6dl_hummingboard
CFG_start_imx6dl_hummingboard.pblx.imximg = $(board)/solidrun-microsom/flash-header-solidrun-hummingboard.imxcfg
FILE_barebox-solidrun-imx6dl-hummingboard.img = start_imx6dl_hummingboard.pblx.imximg
image-$(CONFIG_MACH_SOLIDRUN_HUMMINGBOARD) += barebox-solidrun-imx6dl-hummingboard.img
image-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += barebox-solidrun-imx6dl-hummingboard.img
pblx-$(CONFIG_MACH_NITROGEN6X) += start_imx6q_nitrogen6x_1g
CFG_start_imx6q_nitrogen6x_1g.pblx.imximg = $(board)/boundarydevices-nitrogen6x/flash-header-nitrogen6x-1g.imxcfg