PCM051: Update RAM timings
Updated timings for new MT41J256M16HA15EIT RAM. Timings are backward compatible to the MT41J256M8HX15E RAMs Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -15,7 +15,7 @@
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#include <mach/wdt.h>
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#include <debug_ll.h>
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static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
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static const struct am33xx_cmd_control MT41J256M16HA15EIT_1x512MB_cmd = {
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.slave_ratio0 = 0x40,
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.dll_lock_diff0 = 0x0,
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.invert_clkout0 = 0x1,
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@ -27,23 +27,21 @@ static const struct am33xx_cmd_control MT41J256M8HX15E_2x256M8_cmd = {
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.invert_clkout2 = 0x1,
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};
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static const struct am33xx_emif_regs MT41J256M8HX15E_2x256M8_regs = {
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static const struct am33xx_emif_regs MT41J256M16HA15EIT_1x512MB_regs = {
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.emif_read_latency = 0x6,
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.emif_tim1 = 0x0668A39B,
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.emif_tim2 = 0x26337FDA,
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.emif_tim3 = 0x501F830F,
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.sdram_config = 0x61C04832,
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.emif_tim1 = 0x0888A39B,
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.emif_tim2 = 0x26517FDA,
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.emif_tim3 = 0x501F84EF,
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.sdram_config = 0x61C04B32,
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.zq_config = 0x50074BE4,
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.sdram_ref_ctrl = 0x0000093B,
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};
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static const struct am33xx_ddr_data MT41J256M8HX15E_2x256M8_data = {
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static const struct am33xx_ddr_data MT41J256M16HA15EIT_1x512MB_data = {
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.rd_slave_ratio0 = 0x3B,
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.wr_dqs_slave_ratio0 = 0x85,
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.fifo_we_slave_ratio0 = 0x100,
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.wr_slave_ratio0 = 0xC1,
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.use_rank0_delay = 0x01,
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.dll_lock_diff0 = 0x0,
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.wr_dqs_slave_ratio0 = 0x3B,
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.fifo_we_slave_ratio0 = 0x96,
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.wr_slave_ratio0 = 0x76,
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};
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extern char __dtb_am335x_phytec_phycore_start[];
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@ -72,9 +70,9 @@ static noinline void pcm051_board_init(void)
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am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
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am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
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&MT41J256M8HX15E_2x256M8_regs,
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&MT41J256M8HX15E_2x256M8_data);
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am335x_sdram_init(0x18B, &MT41J256M16HA15EIT_1x512MB_cmd,
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&MT41J256M16HA15EIT_1x512MB_regs,
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&MT41J256M16HA15EIT_1x512MB_data);
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am33xx_uart_soft_reset((void *)AM33XX_UART0_BASE);
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am33xx_enable_uart0_pin_mux();
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