tegra: change cpu internal reset layout for Tegra124
Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -43,8 +43,12 @@ static void assert_maincomplex_reset(int num_cores)
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u32 mask = 0;
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int i;
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for (i = 0; i < num_cores; i++)
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mask |= 0x1111 << i;
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for (i = 0; i < num_cores; i++) {
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if (tegra_get_chiptype() >= TEGRA114)
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mask |= 0x111001 << i;
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else
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mask |= 0x1111 << i;
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}
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writel(mask, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_SET);
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writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_SET);
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@ -53,7 +57,14 @@ static void assert_maincomplex_reset(int num_cores)
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/* release reset state of the first core of the main CPU complex */
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static void deassert_cpu0_reset(void)
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{
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writel(0x1111, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR);
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u32 reg;
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if (tegra_get_chiptype() >= TEGRA114)
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reg = 0x21fff00f;
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else
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reg = 0x1111;
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_RST_CPU_CMPLX_CLR);
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writel(CRC_RST_DEV_L_CPU, TEGRA_CLK_RESET_BASE + CRC_RST_DEV_L_CLR);
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}
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@ -185,7 +196,7 @@ static void start_cpu0_clocks(void)
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/* deassert clock stop for cpu 0 */
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reg = readl(TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
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reg &= ~CRC_CLK_CPU_CMPLX_CPU0_CLK_STP;
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reg &= ~(0xf << 8);
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writel(reg, TEGRA_CLK_RESET_BASE + CRC_CLK_CPU_CMPLX);
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/* enable main CPU complex clock */
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