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tegra: add architectural timer init 

If the bootloader doesn't init the architectural timer
on Cortex A15 Linux falls over when trying to boot.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach 2014-06-03 22:35:06 +02:00 committed by Sascha Hauer
parent 22920598a5
commit 9a13c92e5a
3 changed files with 58 additions and 0 deletions
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3
arch/arm/mach-tegra/include/mach/iomap.h
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@ -257,6 +257,9 @@
#define TEGRA_CSITE_BASE 0x70040000
#define TEGRA_CSITE_SIZE SZ_256K
#define TEGRA_SYSCTR0_BASE 0x700F0000
#define TEGRA_SYSCTR0_SIZE SZ_64K
#define TEGRA_USB_BASE 0xC5000000
#define TEGRA_USB_SIZE SZ_16K

30
arch/arm/mach-tegra/include/mach/tegra114-sysctr.h Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* Register definitions */
#define TEGRA_SYSCTR0_CNTCR 0x00
#define TEGRA_SYSCTR0_CNTCR_ENABLE (1 << 0)
#define TEGRA_SYSCTR0_CNTCR_HDBG (1 << 1)
#define TEGRA_SYSCTR0_CNTSR 0x04
#define TEGRA_SYSCTR0_CNTCV0 0x08
#define TEGRA_SYSCTR0_CNTCV1 0x0c
#define TEGRA_SYSCTR0_CNTFID0 0x20
#define TEGRA_SYSCTR0_CNTFID1 0x24

25
arch/arm/mach-tegra/tegra20.c
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@ -20,6 +20,7 @@
#include <asm/memory.h>
#include <mach/iomap.h>
#include <mach/lowlevel.h>
#include <mach/tegra114-sysctr.h>
static struct NS16550_plat debug_uart = {
.shift = 2,
@ -84,3 +85,27 @@ static int tegra30_mem_init(void)
return 0;
}
mem_initcall(tegra30_mem_init);
static int tegra114_architected_timer_init(void)
{
u32 freq, reg;
if (!of_machine_is_compatible("nvidia,tegra114") &&
!of_machine_is_compatible("nvidia,tegra124"))
return 0;
freq = tegra_get_osc_clock();
/* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
/* Tegra specific SYSCTR */
writel(freq, TEGRA_SYSCTR0_BASE + TEGRA_SYSCTR0_CNTFID0);
reg = readl(TEGRA_SYSCTR0_BASE + TEGRA_SYSCTR0_CNTCR);
reg |= TEGRA_SYSCTR0_CNTCR_ENABLE | TEGRA_SYSCTR0_CNTCR_HDBG;
writel(reg, TEGRA_SYSCTR0_BASE + TEGRA_SYSCTR0_CNTCR);
return 0;
}
coredevice_initcall(tegra114_architected_timer_init);