CLK: clk-divider: Respect CLK_DIVIDER_HIWORD_MASK flag

It is required for Rockchip SoCs where clock settings registers have
write-enable mask in high word.

Signed-off-by: Andrey Panov <rockford@yandex.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

drivers/clk/clk-divider.c

@@ -197,6 +197,10 @@ static int clk_divider_set_rate(struct clk *clk, unsigned long rate,
 	val = readl(divider->reg);
 	val &= ~(div_mask(divider) << divider->shift);
 	val |= value << divider->shift;
+
+	if (clk->flags & CLK_DIVIDER_HIWORD_MASK)
+		val |= div_mask(divider) << (divider->shift + 16);
+
 	writel(val, divider->reg);
 
 	return 0;

include/linux/clk.h

@@ -248,6 +248,8 @@ struct clk_divider {
 	int table_size;
 };
 
+#define CLK_DIVIDER_HIWORD_MASK		(1 << 3)
+
 #define CLK_MUX_HIWORD_MASK		(1 << 2)
 
 extern struct clk_ops clk_divider_ops;