ARM: clps711x: Using COMMON_CLK
This patch adds support for COMMON_CLK API for CLPS711X targets. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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b41afe3c22
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@ -40,6 +40,7 @@ config ARCH_CLPS711X
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bool "Cirrus Logic EP711x/EP721x/EP731x"
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bool "Cirrus Logic EP711x/EP721x/EP731x"
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select CLKDEV_LOOKUP
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select CLKDEV_LOOKUP
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select CLOCKSOURCE_CLPS711X
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select CLOCKSOURCE_CLPS711X
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select COMMON_CLK
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select CPU_32v4T
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select CPU_32v4T
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config ARCH_EP93XX
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config ARCH_EP93XX
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@ -11,6 +11,7 @@
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#include <init.h>
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#include <init.h>
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#include <sizes.h>
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#include <sizes.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clkdev.h>
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#include <mach/clps711x.h>
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#include <mach/clps711x.h>
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@ -18,32 +19,37 @@
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#define CLPS711X_OSC_FREQ 3686400
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#define CLPS711X_OSC_FREQ 3686400
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#define CLPS711X_EXT_FREQ 13000000
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#define CLPS711X_EXT_FREQ 13000000
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static struct clk {
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enum clps711x_clks {
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unsigned long rate;
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dummy, cpu, bus, uart, timer_hf, timer_lf, tc1, tc2, clk_max
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} uart_clk, bus_clk, timer_clk;
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};
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unsigned long clk_get_rate(struct clk *clk)
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static struct {
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const char *name;
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struct clk *clk;
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} clks[clk_max] = {
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{ "dummy", },
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{ "cpu", },
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{ "bus", },
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{ "uart", },
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{ "timer_hf", },
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{ "timer_lf", },
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{ "tc1", },
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{ "tc2", },
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};
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static const char *tc_sel_clks[] = {
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"timer_lf",
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"timer_hf",
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};
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static __init void clps711x_clk_register(enum clps711x_clks id)
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{
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{
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return clk->rate;
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clk_register_clkdev(clks[id].clk, clks[id].name, NULL);
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}
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}
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EXPORT_SYMBOL(clk_get_rate);
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int clk_enable(struct clk *clk)
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static __init int clps711x_clk_init(void)
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{
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{
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/* Do nothing */
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unsigned int f_cpu, f_bus, f_uart, f_timer_hf, f_timer_lf, pll;
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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/* Do nothing */
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}
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EXPORT_SYMBOL(clk_disable);
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static int clocks_init(void)
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{
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int pll, cpu;
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u32 tmp;
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u32 tmp;
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tmp = readl(PLLR) >> 24;
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tmp = readl(PLLR) >> 24;
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@ -54,57 +60,68 @@ static int clocks_init(void)
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tmp = readl(SYSFLG2);
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tmp = readl(SYSFLG2);
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if (tmp & SYSFLG2_CKMODE) {
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if (tmp & SYSFLG2_CKMODE) {
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cpu = CLPS711X_EXT_FREQ;
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f_cpu = CLPS711X_EXT_FREQ;
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bus_clk.rate = CLPS711X_EXT_FREQ;
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f_bus = CLPS711X_EXT_FREQ;
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} else {
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} else {
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cpu = pll;
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f_cpu = pll;
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if (cpu >= 36864000)
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if (f_cpu >= 36864000)
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bus_clk.rate = cpu / 2;
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f_bus = f_cpu / 2;
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else
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else
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bus_clk.rate = 36864000 / 2;
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f_bus = 36864000 / 2;
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}
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}
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uart_clk.rate = DIV_ROUND_CLOSEST(bus_clk.rate, 10);
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f_uart = f_bus / 10;
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if (tmp & SYSFLG2_CKMODE) {
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if (tmp & SYSFLG2_CKMODE) {
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tmp = readw(SYSCON2);
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tmp = readw(SYSCON2);
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if (tmp & SYSCON2_OSTB)
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if (tmp & SYSCON2_OSTB)
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timer_clk.rate = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
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f_timer_hf = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
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else
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else
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timer_clk.rate = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
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f_timer_hf = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
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} else
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} else
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timer_clk.rate = DIV_ROUND_CLOSEST(cpu, 144);
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f_timer_hf = DIV_ROUND_CLOSEST(f_cpu, 144);
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f_timer_lf = DIV_ROUND_CLOSEST(f_timer_hf, 256);
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/* Turn timers in free running mode */
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tmp = readl(SYSCON1);
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tmp = readl(SYSCON1);
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tmp &= ~SYSCON1_TC2M; /* Free running mode */
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tmp &= ~(SYSCON1_TC1M | SYSCON1_TC2M);
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tmp |= SYSCON1_TC2S; /* High frequency source */
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writel(tmp, SYSCON1);
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writel(tmp, SYSCON1);
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return 0;
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clks[dummy].clk = clk_fixed(clks[dummy].name, 0);
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}
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clks[cpu].clk = clk_fixed(clks[cpu].name, f_cpu);
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core_initcall(clocks_init);
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clks[bus].clk = clk_fixed(clks[bus].name, f_bus);
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clks[uart].clk = clk_fixed(clks[uart].name, f_uart);
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clks[timer_hf].clk = clk_fixed(clks[timer_hf].name, f_timer_hf);
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clks[timer_lf].clk = clk_fixed(clks[timer_lf].name, f_timer_lf);
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clks[tc1].clk = clk_mux(clks[tc1].name, IOMEM(SYSCON1), 5, 1,
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tc_sel_clks, ARRAY_SIZE(tc_sel_clks));
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clks[tc2].clk = clk_mux(clks[tc2].name, IOMEM(SYSCON1), 7, 1,
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tc_sel_clks, ARRAY_SIZE(tc_sel_clks));
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static struct clk_lookup clocks_lookups[] = {
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clps711x_clk_register(dummy);
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CLKDEV_CON_ID("bus", &bus_clk),
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clps711x_clk_register(cpu);
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CLKDEV_DEV_ID("clps711x_serial0", &uart_clk),
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clps711x_clk_register(bus);
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CLKDEV_DEV_ID("clps711x_serial1", &uart_clk),
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clps711x_clk_register(uart);
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CLKDEV_DEV_ID("clps711x-cs", &timer_clk),
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clps711x_clk_register(timer_hf);
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};
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clps711x_clk_register(timer_lf);
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clps711x_clk_register(tc1);
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static int clkdev_init(void)
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clps711x_clk_register(tc2);
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{
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clkdev_add_table(clocks_lookups, ARRAY_SIZE(clocks_lookups));
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return 0;
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return 0;
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}
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}
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postcore_initcall(clkdev_init);
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postcore_initcall(clps711x_clk_init);
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static const char *clps711x_clocksrc_name = "clps711x-cs";
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static const char *clps711x_clocksrc_name = "clps711x-cs";
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static __init int clps711x_core_init(void)
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static __init int clps711x_core_init(void)
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{
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{
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/* Using TC2 in low frequency mode as clocksource */
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clk_set_parent(clks[tc2].clk, clks[timer_lf].clk);
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clk_add_alias(NULL, clps711x_clocksrc_name, "tc2", NULL);
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add_generic_device(clps711x_clocksrc_name, DEVICE_ID_SINGLE, NULL,
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add_generic_device(clps711x_clocksrc_name, DEVICE_ID_SINGLE, NULL,
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TC2D, SZ_2, IORESOURCE_MEM, NULL);
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TC2D, SZ_2, IORESOURCE_MEM, NULL);
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return 0;
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return 0;
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}
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}
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coredevice_initcall(clps711x_core_init);
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coredevice_initcall(clps711x_core_init);
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@ -14,6 +14,8 @@
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/memory.h>
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#include <asm/memory.h>
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#include <linux/clk.h>
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#include <mach/clps711x.h>
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#include <mach/clps711x.h>
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static int clps711x_mem_init(void)
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static int clps711x_mem_init(void)
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@ -98,10 +100,12 @@ void clps711x_add_uart(unsigned int id)
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{
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{
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switch (id) {
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switch (id) {
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case 0:
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case 0:
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clk_add_alias(NULL, "clps711x_serial0", "uart", NULL);
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add_generic_device_res("clps711x_serial", 0, uart0_resources,
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add_generic_device_res("clps711x_serial", 0, uart0_resources,
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ARRAY_SIZE(uart0_resources), NULL);
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ARRAY_SIZE(uart0_resources), NULL);
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break;
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break;
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case 1:
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case 1:
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clk_add_alias(NULL, "clps711x_serial1", "uart", NULL);
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add_generic_device_res("clps711x_serial", 1, uart1_resources,
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add_generic_device_res("clps711x_serial", 1, uart1_resources,
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ARRAY_SIZE(uart1_resources), NULL);
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ARRAY_SIZE(uart1_resources), NULL);
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break;
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break;
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