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ARM: i.MX: edmqmx6: correct MMDC init 

This is a squashed commit of the following downstream
commits:
- Set CS0_END in MMDC0_MDASP to 32Gb (4GB)T
- Fix writes to MMDC0_MDSCR
- Enable bank interleaving (BI_ON) and set write
  additional latency (WALAT) to 1 cycle in MMDC0_MDMISC
- Set ARCR_DYN_JMP=1 and ARCR_DYN_MAX=15 in MMDC0_MAARCR

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Philipp Zabel 2014-02-27 14:53:20 +01:00 committed by Sascha Hauer
parent b9f2564473
commit c5853fbbf5
1 changed files with 4 additions and 9 deletions
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13
arch/arm/boards/datamodul-edm-qmx6/lowlevel.c
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@ -99,24 +99,19 @@ static void sdram_init(void)
writel(0x8A8F7934, 0x021b000c);
writel(0xDB568E65, 0x021b0010);
writel(0x01FF00DB, 0x021b0014);
writel(0x00000740, 0x021b0018);
writel(0x00011740, 0x021b0018);
writel(0x00008000, 0x021b001c);
writel(0x000026d2, 0x021b002c);
writel(0x008F0E21, 0x021b0030);
writel(0x00000047, 0x021b0040);
writel(0x11420000, 0x021b0400);
writel(0x0000007f, 0x021b0040);
writel(0x114201f0, 0x021b0400);
writel(0x11420000, 0x021b4400);
writel(0x841A0000, 0x021b0000);
writel(0x04108032, 0x021b001c);
writel(0x00008033, 0x021b001c);
writel(0x00028033, 0x021b001c);
writel(0x00048031, 0x021b001c);
writel(0x09308030, 0x021b001c);
writel(0x04008040, 0x021b001c);
writel(0x0410803A, 0x021b001c);
writel(0x0000803B, 0x021b001c);
writel(0x00048039, 0x021b001c);
writel(0x09308038, 0x021b001c);
writel(0x04008048, 0x021b001c);
writel(0x00005800, 0x021b0020);
writel(0x00011117, 0x021b0818);
writel(0x00011117, 0x021b4818);