ARM: i.MX6: Add video clocks
This adds the IPU, LVDS and HDMI clocks. As these are many, depend on the IPU driver being compiled in. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
6d610de61c
commit
ce6755ca1c
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@ -19,6 +19,8 @@
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <mach/imx6-regs.h>
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#include <mach/revision.h>
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#include <mach/imx6.h>
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#include "clk.h"
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@ -84,8 +86,10 @@ enum mx6q_clks {
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usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
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pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
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ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
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sata_ref, pcie_ref, sata_ref_100m, pcie_ref_125m, enet_ref,
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clk_max
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sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
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usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
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spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
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lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
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};
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static struct clk *clks[clk_max];
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@ -171,6 +175,62 @@ static const char *cko1_sels[] = {
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"pll4_audio",
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};
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static const char *ipu_sels[] = {
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"mmdc_ch0_axi_podf",
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"pll2_pfd2_396m",
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"pll3_120m",
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"pll3_pfd1_540m",
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};
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static const char *ldb_di_sels[] = {
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"pll5_video_div",
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"pll2_pfd0_352m",
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"pll2_pfd2_396m",
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"mmdc_ch1_axi_podf",
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"pll3_usb_otg",
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};
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static const char *ipu_di_pre_sels[] = {
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"mmdc_ch0_axi",
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"pll3_usb_otg",
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"pll5_video_div",
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"pll2_pfd0_352m",
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"pll2_pfd2_396m",
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"pll3_pfd1_540m",
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};
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static const char *ipu1_di0_sels[] = {
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"ipu1_di0_pre",
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"dummy",
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"dummy",
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"ldb_di0_podf",
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"ldb_di1_podf",
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};
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static const char *ipu1_di1_sels[] = {
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"ipu1_di1_pre",
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"dummy",
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"dummy",
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"ldb_di0_podf",
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"ldb_di1_podf",
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};
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static const char *ipu2_di0_sels[] = {
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"ipu2_di0_pre",
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"dummy",
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"dummy",
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"ldb_di0_podf",
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"ldb_di1_podf",
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};
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static const char *ipu2_di1_sels[] = {
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"ipu2_di1_pre",
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"dummy",
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"dummy",
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"ldb_di0_podf",
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"ldb_di1_podf",
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};
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static struct clk_div_table clk_enet_ref_table[] = {
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{ .val = 0, .div = 20, },
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{ .val = 1, .div = 10, },
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@ -179,6 +239,86 @@ static struct clk_div_table clk_enet_ref_table[] = {
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{ },
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};
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static struct clk_div_table post_div_table[] = {
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{ .val = 2, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 0, .div = 4, },
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{ /* sentinel */ }
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};
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static struct clk_div_table video_div_table[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 2, .div = 1, },
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{ .val = 3, .div = 4, },
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{ /* sentinel */ }
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};
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static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
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{
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clks[pll5_post_div] = imx_clk_divider_table("pll5_post_div", "pll5_video", anab + 0xa0, 19, 2, post_div_table);
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clks[pll5_video_div] = imx_clk_divider_table("pll5_video_div", "pll5_post_div", anab + 0x170, 30, 2, video_div_table);
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clks[ipu1_sel] = imx_clk_mux("ipu1_sel", cb + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
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clks[ipu2_sel] = imx_clk_mux("ipu2_sel", cb + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
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clks[ldb_di0_sel] = imx_clk_mux_p("ldb_di0_sel", cb + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
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clks[ldb_di1_sel] = imx_clk_mux_p("ldb_di1_sel", cb + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
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clks[ipu1_di0_pre_sel] = imx_clk_mux_p("ipu1_di0_pre_sel", cb + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
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clks[ipu1_di1_pre_sel] = imx_clk_mux_p("ipu1_di1_pre_sel", cb + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
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clks[ipu2_di0_pre_sel] = imx_clk_mux_p("ipu2_di0_pre_sel", cb + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
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clks[ipu2_di1_pre_sel] = imx_clk_mux_p("ipu2_di1_pre_sel", cb + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
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clks[ipu1_di0_sel] = imx_clk_mux_p("ipu1_di0_sel", cb + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
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clks[ipu1_di1_sel] = imx_clk_mux_p("ipu1_di1_sel", cb + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
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clks[ipu2_di0_sel] = imx_clk_mux_p("ipu2_di0_sel", cb + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
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clks[ipu2_di1_sel] = imx_clk_mux_p("ipu2_di1_sel", cb + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
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clks[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3);
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clks[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3);
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clks[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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clks[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
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clks[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
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clks[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
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clks[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3);
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clks[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3);
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clks[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3);
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clks[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", cb + 0x38, 12, 3);
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clkdev_add_physbase(clks[ipu1_podf], MX6_IPU1_BASE_ADDR, "bus");
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clkdev_add_physbase(clks[ipu1_di0_sel], MX6_IPU1_BASE_ADDR, "di0");
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clkdev_add_physbase(clks[ipu1_di1_sel], MX6_IPU1_BASE_ADDR, "di1");
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clkdev_add_physbase(clks[ipu2_podf], MX6_IPU2_BASE_ADDR, "bus");
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clkdev_add_physbase(clks[ipu2_di0_sel], MX6_IPU2_BASE_ADDR, "di0");
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clkdev_add_physbase(clks[ipu2_di1_sel], MX6_IPU2_BASE_ADDR, "di1");
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clkdev_add_physbase(clks[ldb_di0_sel], 0x020e0008, "di0_pll");
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clkdev_add_physbase(clks[ldb_di1_sel], 0x020e0008, "di1_pll");
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clkdev_add_physbase(clks[ipu1_di0_sel], 0x020e0008, "di0_sel");
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clkdev_add_physbase(clks[ipu1_di1_sel], 0x020e0008, "di1_sel");
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clkdev_add_physbase(clks[ipu2_di0_sel], 0x020e0008, "di2_sel");
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clkdev_add_physbase(clks[ipu2_di1_sel], 0x020e0008, "di3_sel");
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clkdev_add_physbase(clks[ldb_di0], 0x020e0008, "di0");
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clkdev_add_physbase(clks[ldb_di1], 0x020e0008, "di1");
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clkdev_add_physbase(clks[ahb], 0x00120000, "iahb");
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clkdev_add_physbase(clks[pll3_pfd1_540m], 0x00120000, "isfr");
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clk_set_parent(clks[ipu1_di0_sel], clks[ipu1_di0_pre]);
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clk_set_parent(clks[ipu1_di1_sel], clks[ipu1_di1_pre]);
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clk_set_parent(clks[ipu2_di0_sel], clks[ipu2_di0_pre]);
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clk_set_parent(clks[ipu2_di1_sel], clks[ipu2_di1_pre]);
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clk_set_parent(clks[ipu1_di0_pre_sel], clks[pll5_video_div]);
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clk_set_parent(clks[ipu1_di1_pre_sel], clks[pll5_video_div]);
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clk_set_parent(clks[ipu2_di0_pre_sel], clks[pll5_video_div]);
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clk_set_parent(clks[ipu2_di1_pre_sel], clks[pll5_video_div]);
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if ((imx_silicon_revision() != IMX_CHIP_REV_1_0) ||
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cpu_is_mx6dl()) {
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clk_set_parent(clks[ldb_di0_sel], clks[pll5_video_div]);
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clk_set_parent(clks[ldb_di1_sel], clks[pll5_video_div]);
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}
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}
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static int imx6_ccm_probe(struct device_d *dev)
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{
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void __iomem *base, *anatop_base, *ccm_base;
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@ -281,7 +421,6 @@ static int imx6_ccm_probe(struct device_d *dev)
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clks[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
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clks[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
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clkdev_add_physbase(clks[uart_serial_podf], MX6_UART1_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[uart_serial_podf], MX6_UART2_BASE_ADDR, NULL);
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clkdev_add_physbase(clks[uart_serial_podf], MX6_UART3_BASE_ADDR, NULL);
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@ -310,10 +449,16 @@ static int imx6_ccm_probe(struct device_d *dev)
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clkdev_add_physbase(clks[ipg_per], MX6_PWM3_BASE_ADDR, "per");
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clkdev_add_physbase(clks[ipg_per], MX6_PWM4_BASE_ADDR, "per");
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if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
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imx6_add_video_clks(anatop_base, ccm_base);
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writel(0xffffffff, ccm_base + CCGR0);
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writel(0xf0ffffff, ccm_base + CCGR1); /* gate GPU3D, GPU2D */
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writel(0xffffffff, ccm_base + CCGR2);
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writel(0x3fff0000, ccm_base + CCGR3); /* gate OpenVG, LDB, IPU1, IPU2 */
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if (IS_ENABLED(CONFIG_DRIVER_VIDEO_IMX_IPUV3))
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writel(0xffffffff, ccm_base + CCGR3); /* gate OpenVG */
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else
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writel(0x3fffffff, ccm_base + CCGR3); /* gate OpenVG, LDB, IPU1, IPU2 */
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writel(0xffffffff, ccm_base + CCGR4);
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writel(0xffffffff, ccm_base + CCGR5);
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writel(0xffff3fff, ccm_base + CCGR6); /* gate VPU */
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@ -27,6 +27,12 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
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return clk_mux(name, reg, shift, width, parents, num_parents, 0);
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}
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static inline struct clk *imx_clk_mux_p(const char *name, void __iomem *reg,
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u8 shift, u8 width, const char **parents, u8 num_parents)
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{
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return clk_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT);
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}
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static inline struct clk *imx_clk_gate(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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@ -26,6 +26,9 @@
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#define MX6_SPBA_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x3C000)
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#define MX6_VPU_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x40000)
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#define MX6_IPU1_BASE_ADDR 0x02400000
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#define MX6_IPU2_BASE_ADDR 0x02800000
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/* ATZ#1- On Platform */
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#define MX6_AIPS1_ON_BASE_ADDR (MX6_ATZ1_BASE_ADDR + 0x7C000)
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